LNK574 LinkZero-LP ™ 零空载功耗的集成离线式开关IC 产品特色 零空载功耗实现最低系统成本 • 断开负载后自动进入零输入功率模式 • 检测负载重新连接并自动重启动调节 • 对现有LinkSwitch-LP设计可简单升级 • 非常严格的IC参数容差可提高系统制造良品率 • 适合低成本无箝位设计 • 频率调制技术可极大降低EMI滤波元件的成本 • 增大的封装爬电距离可提高系统的应用可靠性 + DC AC IN Output D LinkZero-LP S PI-5508-072610 先进的保护/安全特性 • (a)TypicalApplicationSchematic 精确的迟滞热关断保护 – 自动恢复功能可降低电源在应用现场 VO 的故障率 • 通用输入范围可在全世界范围内使用 • 自动重启动功能在短路及开环电路故障状况下可将输出功率降 • 简单的开/关控制，无需环路补偿 • 高带宽提供快速的无过冲启动及出色的瞬态负载响应 FB BP/M Rated Output Power = VR × IR VR 低85%以上 EcoSmart™ – 高效节能 • 230VAC下的空载功耗低至4mW（注释1） • 无需增加任何元件，轻松满足全球所有的节能标准 • 开/关控制可在极轻负载时具备恒定的效率 应用 • 手机或无绳电话、PDA、电动工具、MP3或便携式音频设备、 剃须刀等使用的充电器 IR (b)OutputCharacteristic 图1.典型应用–非简化的电路(a)及输出特性包络(b) 输出功率表 说明 LinkZero-LP是流行器件LinkSwitch-LP的升级版本，后者是业界 在 设 计 充 电 器 / 适 配 器 时 所 用 元 件 数 最 少 且 待 机 功 率 最 低 的 开关IC。LinkZero-LP控制器采用新的控制技术，能使器件自动 IO PI-5510-082310 230VAC±15% 产品4 LNK574DG 85-265VAC 适配器2 开放式3 适配器2 开放式3 3W 3W 3W 3W 进入空载模式并从控制模式中唤醒，而AC输入功率不足5mW。 表1.输出功率表 IEC16301规定待机功率的测量值必须最低达到10mW的精确度， 注释： 1. IEC16301第4.5条规定低于5mW的待机功率为零功耗。 2. 典型连续输出功率是在无风冷密闭适配器中、环境温度为+50°C的条件下测量 得到的。 3. 最大的实际持续输出功率是在开放式设计及有足够的散热、环境温度为50ºC的 条件下测量得到的。 4. 封装：D:SO-8C。 而LinkZero-LP在230VAC下的待机功耗远低于5mW，因此根据 IEC定义其待机功耗可舍入为零。这种低功率水平在大部分功率 表中也是无法测量出来的。严格指定的反馈(FB)引脚电压参考能 使通用输入初级侧稳压电源在5%负载到满载之间实现精确恒压。 启动及工作时的功率直接来自于漏极引脚，无需使用启动电路。 通过内部振荡频率的抖动大大降低了准峰值和平均值的EMI， 从而降低滤波器成本。 www.powerint.com December2010 LNK574 BYPASS/ MULTI FUNCTION (BP/M) PU OPEN LOOP PULL UP + REGULATOR 5.85 V OVERVOLTAGE PROTECTION + + GENERATOR FEEDBACK REF 1.70 V - 1.37 V 3V 6.5 V 5.85 V 4.85 V + AUTO-RESTART COUNTER FEEDBACK (FB) RESET + DRAIN (D) BYPASS PIN UNDERVOLTAGE - FAULT CURRENT LIMIT + JITTER - 0.9 V VI LIMIT CLOCK CC CUT BACK 1.70 V - 0.9 V ADJ DCMAX S Q R Q OSCILLATOR POWER DOWN COUNTER 160 fOSC CYCLES SYSTEM POWER DOWN/ RESTART EVENT COUNTER RESET LEADING EDGE BLANKING PU PI-5509-111810 SOURCE (S) 图2.功能结构图 引脚功能描述 漏极(D)引脚： 功率MOSFET的漏极连接点。在开启及稳态工作时提供内部操 D Package (SO-8C) 作电流。 旁路/多功能可编程(BP/M)引脚： BP/M 一个外部旁路电容连接到这个引脚，用于生成内部的5.85V供电 FB 电源。电容的值可建立断电时长。电容的最小值为0.1μF。 8 2 7 6 如果流入该引脚的电压超过6.5V(I SD ) 以上，过压保护将禁止开 ) 1 ) 关。 D 4 5 S S S S 反馈(FB)引脚： 在正常操作下，功率MOSFET的开关由此引脚控制。当一个高 于内部VFB参考电压的电压施加到反馈引脚时，MOSFET开关将 被禁止。 PI-5507-060210 图3.引脚配置 在恒压模式下，VFB 参考电压从满载时的1.70 V内部调整到空载 时的1.37 V，在恒流模式下则从1.70 V内部调整到0.9 V。低于 0.9V时，元件将进入自动重启动模式。 源极(S)引脚： 这个引脚是功率MOSFET的源极连接点。它也是旁路和反馈引 脚的接地参考。 2 版本B12/07/10 www.powerint.com LNK574 LinkZero-LP功能描述 行，此周期中随后产生的反馈引脚电压的变化对MOSFET状态 LinkZero-LP在一片晶圆上包括一个700V的功率MOSFET开关及 都不构成影响。 一个电源控制器。与通常的PWM（脉冲宽度调制）控制器不 反馈输入恒流模式 同，它使用了一个简单的开/关控制来调节输出电压。这个控制 当反馈引脚电压在满载条件下降低到1.70V以下时，振荡器频率 器包括了以下电路：一个振荡器、反馈（检测）5.85V稳压器、 开始线性下降，到自动重启动阈值电压0.9V时频率通常会降到 欠压/过压保护旁路引脚、过热保护、频率抖动、电流限流、前 43%的水平上。这一功能在输出电压低于额定稳压阈值电压V R 沿消隐旁路引脚在断电和旁路模式下箝位。此外，该控制器还采 情况下可限定电源的输出功率（参见图1）。 用了拥有专利的断电模式，可自动将待机功耗降至大部分功率 5.85 V稳压器 表都难以测量的超低水平。 只要MOSFET处在关断状态，5.85 V稳压器就会从漏极吸收电流， 断电模式 将连接到旁路引脚的旁路电容充电到5.85 当总负载（电源输出负载加偏置绕组负载）降至满载的约0.6% 时，LinkZero-LP使用存储在旁路电容中的能量。内部电路极低 时，器件进入断电模式。开关将被禁止，此时，内部控制器会 的功率耗散使LinkZero-AX可使用从漏极吸收的电流持续工作。 检测到已两次跳过160个周期，且在两组160个已跳过开关周期 之间只有一个带载开关周期。在断电期间，旁路引脚将从5.85V V。当MOSFET导通 一个0.1µF的旁路电容就足够实现高频率的去耦及能量存储。 放电到约3V，此时，LinkZero-LP将唤醒，并将旁路引脚重新充 6.45 V分流稳压器及8.5 V箝位 电到5.85V。唤醒频率由用户所选择的旁路引脚电容决定（请参 另外，当有电流从外部提供给旁路引脚时，一个6.45V的分流稳 见图22，了解旁路引脚电容的选择方法）。旁路引脚重新充电 压箝位电路会将旁路引脚电压箝在6.5 V。在非隔离设计中，这 到5.85 V后，LinkZero-LP会检测负载条件是否已发生变化，如果 有助于通过电阻从偏置绕组或电源输出端对器件进行外部供 未发生变化，LinkZero-LP将进入新的断电周期，否则会恢复正 电，从而降低器件功耗并提高电源效率。 常工作（请参见“应用范例”部分，了解断电模式工作原理的 详细信息。） 6.5 V分流稳压器只在正常工作模式下带有负载。在断电模式下， 振荡器 电压较高时（典型值为8.5V）将对旁路引脚进行箝位。 典型的振荡器频率内部设置在100kHz的平均水平。一个内部电 路会检测MOSFET的导通并调整振荡器的频率，以便振荡器频率 旁路引脚欠压保护 在大占空比（低输入电压）下达到约100 kHz，在小占空比（ 如果旁路引脚的电压被拉升到6.5 V（BP以上且分流稳压器中的 高输入电压）下达到约78 kHz。进行这种内部频率调整是为了 电流超过6.5mA，将设定锁存，功率MOSFET将停止开关。要对 让峰值功率点始终高于输入电压。此振荡器产生两个信号：最 此锁存进行复位，必须将旁路引脚的电压拉低到1.5V以下。 大占空比信号(DCMAX)及显示每个开关周期开始的时钟信号。 旁路引脚过压保护 振荡器具有的电路可导入少量的频率抖动，通常为6%的开关频率 如果旁路引脚的电压被拉升到6.45(BPSHUNT )以上且分流稳压器中 以将EMI降低到最小。频率抖动的调制速率设置在1kHz的水平， 目的是降低平均及准峰值的EMI，并给予优化。频率抖动与振荡 的电流超过8mA，将设定锁存，功率MOSFET将停止开关。要对 此锁存进行复位，必须将旁路引脚的电压拉低到1.5V以下。 器频率成正比，测量时应把示波器触发设定在漏极电压波形的 过热保护 下降沿来测量。当反馈引脚电压从1.70 V降低到1.37 V时，振荡 热关断电路检测结的温度。阈值设置在142°C并具备70°C的迟 器频率将线性降低。 滞范围。当结温度超过这个阈值(142°C)，功率MOSFET开关被 反馈输入电路恒压模式 禁止，直到结温度下降70°C，MOSFET才会重新使能。 反馈输入电路的参考电压在满载时设定为1.70V，在空载时逐步 电流限流点 降低到1.37V。当反馈引脚电压根据负载情况达到VFB 参考电压 电流限流电路检测功率MOSFET的电流。当电流超过内部阈值 （1.70 V至1.37 V）时，反馈电路的输出端会产生一个低逻辑电 (I LIMIT )时，在该周期剩余阶段会关断功率MOSFET。在功率 平（禁止）。在每个周期开始时，对输出进行采样。如果高， 功率MOSFET会在那个周期导通（使能），否则功率MOSFET将 仍处于关断状态（禁止）。由于采样仅在每个周期开始时进 MOSFET导通后，前沿消隐电路会将电流限流比较器抑制片刻 (tLEB)。通过设置前沿消隐时间，可以防止由电容及整流管反向恢 复时间产生的电流尖峰引起导通的MOSFET提前误关断。 3 www.powerint.com 版本B12/07/10 LNK574 自动重启动 一旦出现故障，比如输出短路，LinkZero-LP进入自动重启动 该设计采用简单的偏置绕组电压反馈方式，由LinkZero-LP进行开/ 操作。每当反馈引脚电压超过反馈引脚的自动重启动阈值电压 关控制。C5上的电压由反馈引脚参考电压以及R3和R4形成的分压 (VFB(AR))的典型值0.9 V时，一个由振荡器计时的内部计数器会进行 电阻决定。电容C4对反馈引脚提供高频滤波，以避免开关周期脉 复位。如果反馈引脚电压下降到VFB(AR)并超过了145ms到170ms 冲束流。反馈引脚参考电压随负载变化，在空载时设定为1.37V， （具体取决于输入电压大小），功率MOSFET开关被禁止。自 满载时逐步升高到1.70 V，用来提供电缆压降补偿。在恒压(CV)阶 动重启动电路以一个12%典型占空比对功率MOSFET进行交替 段，LinkZero-LP器件使能/禁止开关周期以维持反馈引脚参考电 使能和禁止，直到故障排除为止。 压。二极管D6及低成本陶瓷电容C5提供初级反馈绕组波形的整流 滤波功能。在高负载条件下，当超过最大功率阈值时，IC切换到 反馈引脚开环情况 恒流(CC)阶段。在此阶段，反馈引脚电压开始随电源输出电压的 当检测到反馈引脚的开环情况时，内部拉升电流源会将反馈引 下降而降低。为了维持恒流输出，内部振荡器的频率在此阶段逐 脚电压拉升到1.70 V以上，并且LinkZero-LP在160个时钟周期后 渐降低，直到达到起始频率的48%。当反馈引脚电压下降到低于 停止开关。 自动重启动阈值（反馈引脚通常为0.9V）时，电源进入自动重启 动模式。在此模式下，电源将关断1.2 s，然后重新导通170 ms。 应用范例 自动重启动功能可在输出短路情况下减小平均输出电流。 图4所示为一个使用LinkZero-LP设计的典型的6V,330mA、 LinkZero-LP器件通过漏极引脚进行自偏置。不过，为了提升高压 恒压/恒流(CV/CC)输出电源的电路。 下的效率，可以使用可选元件二极管D5和电阻R2形成外部偏置。 AC输入差模滤波可由C1、C2和L1形成的π型滤波器得以 实现。LinkZero-LP具有专利的频率抖动功能，无需使用任何Y 断电(PD)模式占空比和空载功耗由旁路引脚电容C3决定。使用较 电容或共模电感。绕线式电阻RF1属于可熔阻燃型电阻，也可以 高值的电容可以降低空载功耗。C3电容值较高时，会增大断电 用作保险丝来限定浪涌电流。 C6 R5 220 pF 5.1 Ω 100 V 5 D1 1N4007 D2 1N4007 6 V, 350 mA 9 4 8 NC RF1 10 Ω 2W C7 330 µF 16 V D7 SS15 RTN 2 1 C1 3.3 µF 400 V 85 - 265 VAC D3 1N4007 D4 1N4007 R1 4.7 kΩ T1 EF16 C2 3.3 µF 400 V D LinkZero-LP U1 LNK574DG FB D5 1N4148 R2 82 kΩ R3 113 kΩ 1% C5 220 nF 50 V D6 DL4003 BP/M S L1 1.0 mH C3 220 nF 50 V R4 9.09 kΩ 1% C4 1 nF 50 V PI-6086-072110 图4.一个2.1W、6V、350mA充电器的电路图 4 版本B12/07/10 www.powerint.com LNK574 模式下的输出纹波–请参见下面的LinkZero-LP设计指南部分。 断时长也决定了输出电压的纹波。 由于在LinkZero-LP制造过程中使用了流限调节技术，使得限流 点容差非常精确，同时采用了专利的变压器结构技术，得以在 如果图4中没有使用元件D5和R2，该时间将仅由C3的取值 初级电路中实现无箝位电路的设计。因此，峰值漏极电压在 决定。不过，如果使用D5和R2提供外部引脚电源，则在C5和 265VAC输入时可以控制在550V以下，对700V耐压(BV DSS )的 C3中储存的总能量将决定在旁路引脚电压达到VBPPDRESET(~3V)之 MOSFET来说具有非常大的裕量。 前断电模式的关断时长。 输出的整流滤波由输出整流管D7和滤波电容C7来实现。由于自 在以上任一情况下，C5都会在断电模式关断期间通过R3和R4 动重启动特性，平均短路输出电流大大低于1A，因而可以使用低 进行完全放电（D5可防止旁路电容C3通过此路径放电）。 电流额定值和低成本的整流管D7。输出电路只要能处理电源输出 因此，C5的电容值应尽可能地小，以便降低在下一个断开模式 短路时的持续短路电流就可以了。虽然在本设计中不用使用假负 导通期间开始时与此电容放电相关的电源空载输入功耗。C5的最 载电阻，但在电源输出端使用时可降低空载模式下的输出电压。 LinkZero-LP断电(PD)模式设计指南 小值由反馈电阻R3和R4所设定的时间系数决定，以避免C5上的 过量逐周期纹波影响输出电压稳压。C5的典型取值介于100 nF和 330nF之间。 当电源输出负载降低到足够低的水平，以致两次跳过160个连续 开关周期，且在两组160个已跳过开关周期之间只有一个带载开 当使用D5和R2时，偏置绕组电容C5的最小值再次由电压稳压 关周期时，LinkZero-LP进入断电模式。此时，功耗水平约为 性能决定，因此在必要时通常需要减小旁路引脚电容C3的值， LinkZero-LP满载功率能力的0.6%。 以缩短断电模式的关断时长。建议C3的最小值取47nF。 不过，即使完全断开功率输出负载，输出端的任何假负载电阻 PCB布局注意事项 和与偏置绕组相连的元件仍可代表变压器的负载。因此，设计 出的与偏置绕组相连的反馈电路应能代表小于电源满载0.6%的 LinkZero-LP PCB板布局的注意事项 负载。否则，LinkZero-LP将无法检测到输出的空载情况，也不 布局 会进入断电模式，因而无法实现零空载输入功率。 参见图5LinkZero-LP(U1)的推荐电路板布局。 在图4的设计中，电源满载输出功率为2.1W(6V,350mA)。 单点接地 因此，设计出的偏置绕组负载应小于该功率的0.6%(<12.6mW)。 在输入滤波电容与连接源极引脚的铜铂区域使用一个单一接地 以图4中的设计为例，偏置绕组电容C5的平均空载电压约为20 V。 点(Kelvin)。 因此，在该偏置电压下，R3、R4及R2（如果使用）的负载取值 旁路电容(CBP)、反馈引脚噪声滤波电容(CFB)及反馈电阻 应能代表小于12.6mW的负载。在该设计示例中，R2路径的功耗 约为3.3 mW，R3及R4的功耗也约为3.3 mW。因此，6.6 mW的 总功耗能够满足确保在电源负载断开后电源进入断电模式所需的 条件。因此，可以通过调整与偏置绕组相连的电路的功耗值， 来调整LinkZero-LP进入断电模式时的电源输出功率阈值。 为减小环路面积，这两个电容的物理位置应分别尽量接近旁路 和源极引脚，以及反馈和源极引脚。另请注意，为降低噪声干 扰，反馈电阻RFB1和RFB2应靠近反馈引脚放置。 初级环路面积 连接输入滤波电容、变压器初级及LinkZero-LP的初级环路面积 因此可以看出，如果需要，只需在电源输出端添加一个假负载 电阻或将偏置绕组的负载提高到大于电源最大功率能力的0.6% （加上裕量），就可以避免进入断电模式。 当LinkZero-LP处于断电模式时，旁路引脚电压放电至VBPPDRESET (~3 V)所花费的时间决定了断电模式的关断时长。断电模式的关 应尽可能小。 初级箝位电路 可以使用一个外部箝位来控制MOSFET在关断状态时漏极引脚 的峰值电压。在初级绕组上使用一个RCD箝位或一个齐纳稳 压管(~200V)及二极管箝位即能够实现。在任何情况下，为改善 EMI，从箝位元件到变压器再到LinkZero-LP(U1)的电路路径应保 证最小。 5 www.powerint.com 版本B12/07/10 LNK574 CB DB RS CS DBP RBP DO RFB2 CFB CO CBP RFB1 R6 Transformer U1 J3 Ð DC IN T1 + PI-6098-082310 图5.一个2.1W,6V,350mA充电器的PCB布局 散热考量 LinkZero-LP(U1)之下的铜铂区域不仅仅是一个接地点，而且还 起到一个散热片的作用。因它连接到安静的源极节点，应将这 个区域扩大以使U1实现良好的散热。这同样适用于输出二极管 的阴极。 Y电容 快速设计校验 对于任何使用LinkZero-LP的电源设计，都应经过全面测试以确 保在最差条件下元件的规格没有超过规定范围。建议至少进行 如下测试： 1. 最大漏极电压–校验在最高输入电压和峰值（过载）输出功 率时VDS没有超过660V。给700V的BVDSS规格增加50V的裕 应将Y电容（如使用）直接放置在初级输入滤波电容正极和变压 量，使得在设计变更时留有一定的设计裕量，尤其是在无箝 器次级的共地/返回极接脚之间。这样放置会使高幅值的共模浪 位电路设计中。 涌电流远离U1。注意：如果在输入端使用了π型EMI滤波器， 那么滤波器内的电感应放置在输入滤波电容的负极之间。 输出二极管(DO) 要达到最佳的性能，连接次级绕组、输出二极管(DO)及输出滤波 电容(CO)的环路区域面积应最小。此外，与二极管的阴极和阳极 连接的铜铂区域应足够大，以便用来散热。最好在电气安静的 阴极留有更大的铜铂区域。阳极铺铜区域过大会增加高频传导 及辐射EMI。电阻RS与CS形成次级侧RC缓冲电路。 2. 最大漏极电流–在最高环境温度、最大输入电压及峰值输出 （过载）功率情况下，检查漏极电流以确定变压器是否出现 饱和，另外也要检测电源开启时是否出现过高的前沿导通电 流尖峰。在稳态工作下重复以上操作，校验前沿电流尖峰在 t LEB(MIN)结束时低于ILIMIT(MIN)。在任何条件下，最大漏极电流应 低于规定的绝对最大额定值。 3. 热检测–在规定的最大输出功率、最小输入电压及最高环境温 度情况下，检查LinkZero-LP、变压器、输出二极管及输出电容 的温度没有超标。应有足够的温度裕量以保证LinkZero-LP不 会因元件与元件间RDS(ON)的差异而引起过热问题，请参见数 据手册中关于RDS(ON)的说明。建议在低压输入及最大输出功率 的情况下，LinkZero-LP源极引脚的最高温度不高于100°C， 这样就可以适应上述参数的变化。 6 版本B12/07/10 www.powerint.com LNK574 绝对最大额定值(1,6) 漏极电压....................................................................-0.3V至700V LNK574峰值漏极电流..........................................200(375)mA(2) 峰值负向脉冲漏极电流................................................. -100mA(3) 反馈电压........................................................................-0.3V至9V 反馈电流............................................................................. 100mA 旁路引脚电压................................................................-0.3V至9V 断电模式下的旁路引脚电压................................... -0.3V至11V(7) 贮存温度............................................................... -65°C至150°C 工作结温........................................................... -40°C至150°C(4) 引线温度............................................................................ 260°C(5) 注释： 1. 所有电压都是以TA=25°C时的源极为参考点。 2. 在漏源极电压不超过400V时允许使用更高的峰值漏极电流。 3. 持续时间不超过2μs。 4. 通常由内部电路控制。 5. 在距壳体1/16英寸处测量，持续时间5秒。 6.在短时间内施加器件允许的最大额定值不会引起产品永久性的 损坏。但长时间用在器件允许的最大额定值时，会对产品的可靠 性造成影响。 7.流入引脚的最大电流为300μA。 热阻 热阻：D封装： (qJA)..................................100°C/W(2);80°C/W(3) (qJC)........................................................30°C/W(1) 参数 符号 注释： 1. 在靠近塑料表面的源极引脚测得。 2. 焊在0.36平方英寸(232mm2)、2盎司铜铂区域。 3. 焊在1平方英寸(645mm2)、2盎司铜铂区域。 条件 源极=0V；TJ=-40至125°C 最小值 典型值 最大值 单位 93 100 107 kHz （除非另有说明） 控制功能 输出频率 fOSC 频率抖动 TJ=25°C VFB=1.70V，参见注释C 相对于平均频率抖动的峰峰值，TJ=25°C ±3 % TJ=25°C VFB=VFB(AR) 参见注释B 43 % % 自动重启动操作频率 与fOSC的比率 fOSC(AR) fOSC 最大占空比 DCMAX 60 63 无跳过周期时的反馈 引脚电压 VFB 1.63 1.70 存在99.4%跳过周期 时的反馈引脚电压 VFB(NL) 自动重启动时的反馈 引脚电压 VFB(AR) 1.77 1.37 0.8 0.9 V V 1.05 V 7 www.powerint.com 版本B12/07/10 LNK574 参数 符号 条件 源极=0V；TJ=-40至125°C 最小值 典型值 最大值 单位 （除非另有说明） 控制功能（继上） 开关最短导通时间 tON(MIN) 700 ns IS1 反馈电压>VFB （MOSFET未开启） 150 200 260 IS2 0.9V≤VFB≤1.70V （MOSFET开启） 200 250 310 ICH1 VBP=0V,TJ=25°C -5.5 -3.8 -1.8 ICH2 VBP=4V,TJ=25°C -3.8 -2.5 -1.0 VBP 5.60 5.85 6.10 V 旁路引脚电压迟滞 VBP(H) 0.8 1.0 1.2 V 旁路引脚分流电压 BPSHUNT 6.1 6.5 6.9 V 漏极供电电流 旁路引脚充电电流 旁路引脚电压 mA mA 电路保护 ILIMIT di/dt=40mA/ms TJ=25°C 126 136 146 mA 功率因数 I2f di/dt=40mA/ms TJ=25°C 1665 1850 2091 A2Hz 前沿消隐时间 tLEB TJ=25°C 220 265 旁路引脚关断阈值电流 ISD VBP=BPSHUNT See Note E 5.0 6.5 8.0 mA 热关断温度 TSD 参见注释B 135 142 150 °C 热关断迟滞 TSD(H) 参见注释B 70 断电模式下的关断状态 漏极漏电流 IDSS(PD) TJ=25°C, VDRAIN=325V 参见图23 6.5 9 mA 断电模式下的旁路引脚 过压保护 VBP(PDP) IBP=300mA TJ≤100°C 7.25 8.5 10.9 V 旁路引脚通电复位阈值 （断电模式或在电源启 动时） VBP(PU) 1.5 3 4 V 电流限流点 ns °C 断电(PD)模式 8 版本B12/07/10 www.powerint.com LNK574 参数 符号 条件 源极=0V；TJ=-40至125°C 最小值 典型值 最大值 TJ=25°C 48 55 TJ=100°C 76 88 单位 （除非另有说明） 输出 导通电阻 RDS(ON) 击穿电压 BVDSS ID=13mA VBP=6.2V,TJ=25°C 漏极供电电压 自动重启动导通时间 自动重启动关断时间 输出使能延时 VIN=85VAC,TJ=25°C, DCAR tEN 参见注释D 参见图8 W 700 V 50 V 145 ms 1.0 s 14 ms 注释： A. IDSS为80%的BVDSS以及最大工作结温时最差的关断状态漏电流。 B. 此参数是通过表征法得到的。 C. 输出频率规格适用于最终应用中的低输入电压。设计出的控制器可在高压输入下降低约20%的输出频率，使低压和高压下的最 大输出功率保持平衡。 D. 在265VAC高压输入下，自动重启动导通/关断时间延长20%。 E. 如果流入旁路引脚的电流在 BPSHUNT 电压时达到ISD，LinkZero-LP将关断。 9 www.powerint.com 版本B12/07/10 LNK574 BP/M S FB S S 0-2 V 0.1 µF S1 D 470 Ω 5W S 50 V PI-6067-072110 图6.一般测试电路 DCMAX (internal signal) tP FB tEN VDRAIN tP = 1 fOSC PI-3707-112503 图8.输出使能定时 PI-4021-101305 DRAIN Current (mA) 图7.占空比测量 100 2 µs 0 -100 Time (µs) 图9.峰值负脉冲漏极电流波形 10 版本B12/07/10 www.powerint.com LNK574 典型性能特性 1.0 0.9 -50 -25 0 25 50 PI-6065-071910 1.2 Output Frequency (Normalized to 25 °C) PI-2213-012301 Breakdown Voltage (Normalized to 25 °C) 1.1 1.0 0.8 0.6 0.4 0.2 0 75 100 125 150 -50 -25 Junction Temperature (°C) 25 50 75 100 125 Junction Temperature (°C) 图10.击穿电压相对于温度的变化 图11.频率随温度的变化 1.0 0.8 PI-4057-071905 Current Limit (Normalized to 25 °C) 1.2 1.1 FEEDBACK Pin Voltage (Normalized to 25 °C) PI-6066-071910 1.4 1.0 0.6 0.4 0.2 0.9 0 0 50 100 -50 -25 150 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) 图12.限流点相对于温度的变化 图13.反馈引脚电压与温度的特性曲线 6 5 4 3 2 1 200 175 DRAIN Current (mA) PI-2240-012301 7 PI-3927-083104 -50 BYPASS Pin Voltage (V) 0 25 °C 150 100 °C 125 100 75 50 25 0 0 0 0.2 0.4 0.6 0.8 1.0 0 4 6 8 10 12 14 16 18 20 DRAIN Voltage (V) Time (ms) 图14.旁路引脚启动波形(CBP=0.22μF) 2 图15.输出特性 11 www.powerint.com 版本B12/07/10 LNK574 典型性能特性（继上） 100 Frequency (kHz) 100 10 PI-6068-071910 110 PI-3928-083104 Drain Capacitance (pF) 1000 90 80 70 1 60 0 100 200 300 400 500 0 600 10 20 Drain Voltage (V) 60 70 1.5 1.4 6.0 7.0 1.3 40 30 20 10 0 -10 -20 -30 0 10 20 30 40 50 60 70 80 90 100 0.0 Output Load (%) -6 -8 -10 -12 -14 -16 -18 -20 3.0 4.0 5.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 PI-6072-072110 FEEDBACK Pin Current (µA) -4 2.0 图19.反馈引脚输入的输入特性曲线 PI-6071-072110 -2 1.0 FEEDBACK Pin Voltage (V) 图18.恒压模式下反馈引脚稳压阈值随输出负载的变化 0 PI-6070-072110 50 FEEDBACK Pin Current (µA) 1.6 FEEDBACK Pin Current (µA) 50 图17.频率降低随占空比（线电压）的变化 PI-6069-072110 FEEDBACK Pin Voltage (V) 1.7 40 Duty Cycle (%) 图16.CDSS相对漏极电压的变化 1.8 30 Auto-Restart 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FEEDBACK Pin Voltage (V) Frequency Normalized to 1 图20.恒流模式下反馈引脚的输入特性曲线（1.7V至0.9V） 图21.频率在恒流模式下降低并归一化 12 版本B12/07/10 www.powerint.com LNK574 典型性能特性（继上） 0.9 9 Drain Current (µA) 0.8 0.7 0.6 0.5 0.4 0.3 8 7 6 5 4 3 0.2 2 0.1 1 0 PI-6111-081810 10 PI-6110-090810 BYPASS Pin Capacitor (µF) 1 0 0 200 400 600 800 1000 1200 1400 Power Down Period (ms) 图22.断电关断时间随旁路引脚电容的变化。VBP起始值为 5.85V（温度=25°C） -50 -25 0 25 50 75 100 125 Temperature (°C) 图23.断电模式下典型漏极电流随温度的变化 13 www.powerint.com 版本B12/07/10 LNK574 SO-8C (D Package) 4 B 0.10 (0.004) C A-B 2X 2 DETAIL A 4.90 (0.193) BSC A 4 8 D 5 2 3.90 (0.154) BSC GAUGE PLANE SEATING PLANE 6.00 (0.236) BSC C 0-8 1.04 (0.041) REF 0.10 (0.004) C D 2X Pin 1 ID 1 4 0.25 (0.010) BSC 0.40 (0.016) 1.27 (0.050) 0.20 (0.008) C 2X 7X 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) M C A-B D 1.27 (0.050) BSC 1.25 - 1.65 (0.049 - 0.065) 1.35 (0.053) 1.75 (0.069) o DETAIL A 0.10 (0.004) 0.25 (0.010) 0.10 (0.004) C H 7X SEATING PLANE 0.17 (0.007) 0.25 (0.010) C Reference Solder Pad Dimensions + 2.00 (0.079) + D07C 4.90 (0.193) + + 1.27 (0.050) Notes: 1. JEDEC reference: MS-012. 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. 0.60 (0.024) PI-4526-040110 元件订购信息 • LinkZero产品系列 • LinkZero-LP序列号 • 封装信息 D 塑封SO-8C • 封装材料 G 绿色：无卤素和符合RoHS • 带装和卷轴装及其他包装形式 空白 LNK 574 D G - TL TL 标准配置 带装&卷轴装，至少2500个，仅适用D封装不适用于P封装。 14 版本B12/07/10 www.powerint.com LNK574 15 www.powerint.com 版本B12/07/10 版本 注释： 日期 A 初始版本 10/12/10 B 更新了文字及参数表格。 12/07/10 有关最新产品信息，请访问：www.powerint.com PowerIntegrationsreservestherighttomakechangestoitsproductsatanytimetoimprovereliabilityormanufacturability.Power Integrationsdoesnotassumeanyliabilityarisingfromtheuseofanydeviceorcircuitdescribedherein.POWERINTEGRATIONSMAKES NOWARRANTYHEREINANDSPECIFICALLYDISCLAIMSALLWARRANTIESINCLUDING,WITHOUTLIMITATION,THEIMPLIED WARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENTOFTHIRDPARTYRIGHTS. Patent Information Theproductsandapplicationsillustratedherein(includingtransformerconstructionandcircuitsexternaltotheproducts)maybecovered byoneormoreU.S.andforeignpatents,orpotentiallybypendingU.S.andforeignpatentapplicationsassignedtoPowerIntegrations. AcompletelistofPowerIntegrationspatentsmaybefoundatwww.powerint.com.PowerIntegrationsgrantsitscustomersalicense undercertainpatentrightsassetforthathttp://www.powerint.com/ip.htm. Life Support Policy POWERINTEGRATIONSPRODUCTSARENOTAUTHORIZEDFORUSEASCRITICALCOMPONENTSINLIFESUPPORTDEVICESOR SYSTEMSWITHOUTTHEEXPRESSWRITTENAPPROVALOFTHEPRESIDENTOFPOWERINTEGRATIONS.Asusedherein: 1. ALifesupportdeviceorsystemisonewhich,(i)isintendedforsurgicalimplantintothebody,or(ii)supportsorsustainslife,and(iii) whosefailuretoperform,whenproperlyusedinaccordancewithinstructionsforuse,canbereasonablyexpectedtoresultinsignificant injuryordeathtotheuser. 2. Acriticalcomponentisanycomponentofalifesupportdeviceorsystemwhosefailuretoperformcanbereasonablyexpectedtocause thefailureofthelifesupportdeviceorsystem,ortoaffectitssafetyoreffectiveness. ThePIlogo,TOPSwitch,TinySwitch,LinkSwitch,DPA-Switch,PeakSwitch,EcoSmart,Clampless,E-Shield,Filterfuse,StakFET,PIExpert andPIFACTSaretrademarksofPowerIntegrations,Inc.Othertrademarksarepropertyoftheirrespectivecompanies. ©2010,PowerIntegrations,Inc. Power Integrations全球销售支持网络 全球总部 5245HellyerAvenue SanJose,CA95138,USA. Main:+1-408-414-9200 CustomerService: Phone:+1-408-414-9665 Fax:+1-408-414-9765 e-mail:[email protected] 中国（上海） Room1601/1610,Tower1 KerryEverbrightCity No.218TianmuRoadWest Shanghai,P.R.C.200070 Phone:+86-21-6354-6323 Fax:+86-21-6354-6325 e-mail:[email protected] 中国（深圳） RmA,B&C4thFloor,BlockC, ElectronicsScienceand TechnologyBldg.,2070 ShennanZhongRd, Shenzhen,Guangdong, China,518031 Phone:+86-755-8379-3243 Fax:+86-755-8379-5828 e-mail:[email protected] 德国 Rüeckertstrasse3 D-80336,Munich Germany Phone:+49-89-5527-3910 Fax:+49-89-5527-3920 e-mail:[email protected] 印度 #1,14thMainRoad Vasanthanagar Bangalore-560052India Phone:+91-80-4113-8020 Fax:+91-80-4113-8023 e-mail:[email protected] 意大利 ViaDeAmicis2 20091BressoMI Italy Phone:+39-028-928-6000 Fax:+39-028-928-6009 e-mail:[email protected] 日本 KoseiDai-3Bldg. 2-12-11,Shin-Yokohama, Kohoku-ku Yokohama-shiKanagwan 222-0033Japan Phone:+81-45-471-1021 Fax:+81-45-471-3717 e-mail:[email protected] 韩国 RM602,6FL KoreaCityAirTerminalB/D,159-6 Samsung-Dong,Kangnam-Gu, Seoul,135-728,Korea Phone:+82-2-2016-6610 Fax:+82-2-2016-6630 e-mail:[email protected] 台湾 5F,No.318,NeiHuRd.,Sec.1 NeiHuDist. Taipei,Taiwan114,R.O.C. Phone:+886-2-2659-4570 Fax:+886-2-2659-4550 e-mail:[email protected] 欧洲总部 1stFloor,St.James’sHouse EastStreet,Farnham SurreyGU97TJ UnitedKingdom Phone:+44(0)1252-730-141 Fax:+44(0)1252-727-689 e-mail:[email protected] 技术支持热线 WorldWide+1-408-414-9660 新加坡 51NewtonRoad 技术支持传真 #15-08/10GoldhillPlaza WorldWide+1-408-414-9760 Singapore,308900 Phone:+65-6358-2160 Fax:+65-6358-2015 e-mail:[email protected] LNK574 LinkZero-LP ™ Zero No-Load Consumption Integrated Off-Line Switcher Product Highlights Lowest System Cost with Zero No-Load • Automatically enters zero input power mode when load is disconnected • Detects load reconnection and automatically restarts regulation • Simple upgrade to existing LinkSwitch-LP designs • Very tight IC parameter tolerances improve system manufacturing yield • Suitable for low-cost clampless designs • Frequency jittering greatly reduces EMI filter cost • Extended package creepage improves system field reliability Applications • Chargers for cell/cordless phones, PDAs, power tools, MP3/ portable audio devices, shavers, etc. Description LinkZero-LP is an upgrade to the popular LinkSwitch-LP, the industry’s lowest component count charger/adapter and standby power switcher IC. The LinkZero-LP controller incorporates new technology which enables the device to automatically enter into and wake up from no-load mode while taking less than 5 mW from the AC power. IEC 62301 specifies measurements of standby power to a minimum accuracy of 10 mW, and so LinkZero-LP’s consumption of substantially less than 5 mW at 230 VAC rounds to zero based on the IEC definition. This low power level is also immeasurable on most power meters. The tightly specified FEEDBACK (FB) pin voltage reference enables universal input primary side regulated power supplies with accurate constant voltage from 5% to full load. The start-up and operating power are derived directly from the DRAIN pin which eliminates start-up circuitry. The internal oscillator frequency is jittered to significantly reduce both quasi-peak and average EMI, minimizing filter cost. www.powerint.com Output D LinkZero-LP FB BP/M S PI-5508-072610 Advanced Protection/Safety Features • Accurate hysteretic thermal shutdown protection – automatic recovery reduces field returns • Universal input range allows worldwide operation • Auto-restart reduces delivered power by >85% during shortcircuit and open loop fault conditions • Simple ON/OFF control, no loop compensation needed • High bandwidth provides excellent transient load response with no overshoot EcoSmart™ – Energy Efficient • No-load consumption as low as 4 mW at 230 VAC input (Note 1) • Easily meets all global energy efficiency regulations with no added components • ON/OFF control provides constant efficiency to very light loads + DC AC IN (a) Typical Application Schematic VO Rated Output Power = VR × IR VR IR IO PI-5510-082310 (b) Output Characteristic Figure 1. Typical Application – Not a Simplified Circuit (a) and Output Characteristic Envelope (b). Output Power Table 230 VAC ±15% Product4 LNK574DG 85-265 VAC Adapter2 Open Frame3 Adapter2 Open Frame3 3W 3W 3W 3W Table 1. Output Power Table. Notes: 1. IEC 62301 Clause 4.5 rounds standby power use below 5 mW to zero. 2. Typical continuous power in a non-ventilated enclosed adapter measured at +50 °C ambient. 3. Maximum practical continuous power in an open frame design with adequate heatsinking, measured at 50 °C ambient. 4. Packages: D: SO-8C. December 2010 LNK574 BYPASS/ MULTI FUNCTION (BP/M) PU OPEN LOOP PULL UP + REGULATOR 5.85 V OVERVOLTAGE PROTECTION + + GENERATOR FEEDBACK REF 1.70 V - 1.37 V 3V 6.5 V 5.85 V 4.85 V + AUTO-RESTART COUNTER FEEDBACK (FB) RESET + DRAIN (D) BYPASS PIN UNDERVOLTAGE - FAULT CURRENT LIMIT + JITTER - 0.9 V VI LIMIT CLOCK CC CUT BACK 1.70 V - 0.9 V ADJ DCMAX S Q R Q OSCILLATOR POWER DOWN COUNTER 160 fOSC CYCLES SYSTEM POWER DOWN/ RESTART EVENT COUNTER RESET LEADING EDGE BLANKING PU PI-5509-111810 Figure 2 SOURCE (S) Functional Block Diagram. Pin Functional Description DRAIN (D) Pin: The power MOSFET drain connection provides internal operating current for both startup and steady-state operation. BYPASS/MULTI-FUNCTIONAL PROGRAMMABLE (BP/M) Pin: An external bypass capacitor for the internally generated 5.85 V supply is connected to this pin. The value of capacitor establishes the power down period. The minimum value of capacitor is 0.1 mF. An overvoltage protection disables the switching if the current into the pin exceeds 6.5 mA (ISD). FEEDBACK (FB) Pin: During normal operation, switching of the power MOSFET is controlled by this pin. MOSFET switching is disabled when a voltage greater than an internal VFB reference voltage is applied to the FEEDBACK pin. D Package (SO-8C) BP/M FB 1 8 2 7 6 D 4 5 S S S S PI-5507-060210 Figure 3. Pin Configuration. The VFB reference voltage is internally adjusted from 1.70 V at full load to 1.37 V at no-load in CV mode, and 1.70 V to 0.9 V in CC mode. Below 0.9 V the part enters auto-restart operation. SOURCE (S) Pin: This pin is the power MOSFET source connection. It is also the ground reference for the BYPASS and FEEDBACK pins. 2 Rev. B 12/07/10 www.powerint.com LNK574 LinkZero-LP Functional Description LinkZero-LP comprises a 700 V power MOSFET switch with a power supply controller on the same die. Unlike conventional PWM (pulse width modulation) controllers, it uses a simple ON/ OFF control to regulate the output voltage. The controller consists of the following circuits, an oscillator, feedback (sense) 5.85 V regulator, BYPASS pin under/overvoltage protection, over-temperature protection, frequency jittering, current limit, leading edge blanking BYPASS pin clamp in power down and bypass mode. The controller includes a proprietary power down mode that automatically reduces standby consumption to levels that are immeasurable on most power meters. sampled at the beginning of each cycle. If high, the power MOSFET is turned on for that cycle (enabled), otherwise the power MOSFET remains off (disabled). Since the sampling is done only at the beginning of each cycle, subsequent changes in the FEEDBACK pin voltage during the remainder of the cycle are ignored. Feedback Input CC Mode When the FEEDBACK pin voltage at full load falls below 1.70 V, the oscillator frequency linearly reduces to typically 43% at the auto-restart threshold voltage of 0.9 V. This function limits the power supply output power at output voltages below the rated voltage regulation threshold VR (see Figure 1). Power Down Mode The device enters into power down mode (where MOSFET switching is disabled) when the total load (power supply output plus bias winding loads) has reduced to ~0.6% of full load. The internal controller detects this condition by sensing when 160 cycles have been skipped twice with only one active switching cycle in between the two sets of 160 skipped switching cycles. During the power down period the BYPASS pin capacitor will discharge from 5.85 V down to about 3 V at which point the LinkZero-LP will wake up and charge the BYPASS pin back up to 5.85 V. The wake up frequency is determined by the user through the choice of the BYPASS pin capacitor value (see Figure 22 for BYPASS pin capacitor choice). Once the BYPASS pin has recharged 5.85 V LinkZero-LP senses if the load condition has changed or not, if not the LinkZero-LP will enter into a new power down cycle or otherwise resumes normal operation (See Applications Example section for more details of power down mode operation). 5.85 V Regulator The BYPASS pin voltage is regulated by drawing a current from the DRAIN whenever the MOSFET is off if needed to charge up the BYPASS pin to a typical voltage of 5.85 V. When the MOSFET is on, LinkZero-LP runs off of the energy stored in the bypass capacitor. Extremely low power consumption of the internal circuitry allows LinkZero-LP to operate continuously from the current drawn from the DRAIN pin. A bypass capacitor value of 0.1 µF is sufficient for both high frequency decoupling and energy storage. Oscillator The typical oscillator frequency is internally set to an average of 100 kHz. An internal circuit senses the on-time of the MOSFET switch and adjusts the oscillator frequency so that at large duty cycle (low line voltage) the frequency is about 100 kHz and at small duty cycle (high line voltage) the oscillator frequency is about 78 kHz. This internal frequency adjustment is used to make the peak power point constant over line voltage. Two signals are generated from the oscillator: the maximum duty cycle signal (DCMAX) and the clock signal that indicates the beginning of a switching cycle. The 6.5 V shunt regulator is only active in normal operation, and when in power down mode a clamp at a higher voltage (typical 8.5 V) will clamp the BYPASS pin. The oscillator incorporates circuitry that introduces a small amount of frequency jitter, typically 6% of the switching frequency, to minimize EMI. The modulation rate of the frequency jitter is set to 1 kHz to optimize EMI reduction for both average and quasi-peak emissions. The frequency jitter, which is proportional to the oscillator frequency, should be measured with the oscilloscope triggered at the falling edge of the drain voltage waveform. The oscillator frequency is linearly reduced when the FEEDBACK pin voltage is lowered from 1.70 V down to 1.37 V. Feedback Input Circuit CV Mode The feedback input circuit reference is set at 1.70 V at full load and gradually reduces down to 1.37 V at no-load. When the FEEDBACK pin voltage reaches a VFB reference voltage (1.70 V to 1.37 V) depending on the load, a low logic level (disable) is generated at the output of the feedback circuit. This output is 6.5 V Shunt Regulator and 8.5 V Clamp In addition, there is a shunt regulator that helps maintain the BYPASS pin at 6.5 V when current is provided to the BYPASS pin externally. This facilitates powering the device externally through a resistor from the bias winding or power supply output in non-isolated designs, to decrease device dissipation and increase power supply efficiency. BYPASS Pin Undervoltage Protection The BYPASS pin undervoltage circuitry disables the power MOSFET when the BYPASS pin voltage drops below 4.85 V. Once the BYPASS pin voltage drops below 4.85 V, it must rise back to 5.85 V to enable (turn on) the power MOSFET. BYPASS Pin Overvoltage Protection If the BYPASS pin gets pulled above 6.5 V (BPSHUNT )and the current into the shunt exceeds 6.5 mA a latch will be set and the power MOSFET will stop switching. To reset the latch the BYPASS pin has to be pulled down to below 1.5 V. Over-Temperature Protection The thermal shutdown circuit senses the die temperature. The threshold is set at 142 °C typical with a 70 °C hysteresis. When the die temperature rises above this threshold (142 °C) the power MOSFET is disabled and remains disabled until the die temperature falls by 70 °C, at which point the MOSFET is re-enabled. Current Limit The current limit circuit senses the current in the power MOSFET. When this current exceeds the internal threshold (ILIMIT ), the power MOSFET is turned off for the remaining of that cycle. The leading edge blanking circuit inhibits the current limit 3 www.powerint.com Rev. B 12/07/10 LNK574 comparator for a short time (tLEB) after the power MOSFET is turned on. This leading edge blanking time has been set so that current spikes caused by capacitance and rectifier reverse recovery time will not cause premature termination of the MOSFET conduction. Wire-wound types are recommended for designs that operate ≥132 VAC to withstand the instantaneous power when AC is first applied as C1 and C2 charge. The power supply utilizes simplified bias winding voltage feedback, enabled by the LinkZero-LP ON/OFF control. The voltage across C5 is determined by the FEEDBACK pin reference voltage and the resistor divider formed by R3 and R4. Capacitor C4 provides high frequency filtering on the FEEDBACK pin to avoid switching cycle pulse bunching. The FEEDBACK pin reference voltage, which varies with load, is set to 1.37 V at no-load and gradually increases to 1.70 V at full load to provide cable drop compensation. In the constant voltage (CV) region, the LinkZero-LP device enables/disables switching cycles to maintain the FEEDBACK pin reference voltage. Diode D6 and low cost ceramic capacitor C5 provide rectification and filtering of the primary feedback winding waveform. At increased loads, beyond the maximum power threshold, the IC transitions into the constant current (CC) region. In this region, the FEEDBACK pin voltage begins to reduce as the power supply output voltage falls. In order to maintain a constant output current, the internal oscillator frequency is reduced in this region until it reaches typically 48% of the starting frequency. When the FEEDBACK pin voltage drops below the auto-restart threshold (typically 0.9 V on the FEEDBACK pin), the power supply enters the auto-restart mode. In this mode, the power supply will turn off for 1.2 s and then turn back on for 170 ms. The auto-restart function reduces the average output current during an output short-circuit condition. Auto-Restart In the event of a fault condition such as output short-circuit, LinkZero-LP enters into auto-restart operation. An internal counter clocked by the oscillator gets reset every time the FEEDBACK pin voltage exceeds the FEEDBACK pin autorestart threshold voltage (VFB(AR) typical 0.9 V). If the FEEDBACK pin voltage drops below VFB(AR) for more than 145 ms to 170 ms depending on the line voltage, the power MOSFET switching is disabled. The auto-restart alternately enables and disables the switching of the power MOSFET at a duty cycle of typically 12% until the fault condition is removed. Open Loop Condition on the FEEDBACK Pin When an open loop condition on the FEEDBACK pin is detected, an internal pull up current source pulls the FEEDBACK pin up to above 1.70 V and LinkZero-LP stops switching after 160 clock cycles. Applications Example The circuit shown in Figure 4 is a typical isolated zero no-load 6 V, 350 mA, constant voltage, and constant current (CV/CC) output power supply using LinkZero-LP. AC input differential filtering is accomplished by the π filter formed by C1, C2 and L1. The proprietary frequency jitter feature of the LinkZero-LP eliminates the need for any Y capacitor or commonmode inductor. Wire-wound resistor RF1 is a fusible, flame proof resistor which is used as a fuse as well as to limit inrush current. The LinkZero-LP device is self biased through the DRAIN pin. However, to improve efficiency at high line, an external bias may be added using optional components diode D5 and resistor R2. The power down (PD) mode duty cycle and the no-load power C6 R5 220 pF 5.1 Ω 100 V 5 D1 1N4007 D2 1N4007 6 V, 350 mA 9 4 8 NC RF1 10 Ω 2W C7 330 µF 16 V D7 SS15 RTN 2 1 C1 3.3 µF 400 V 85 - 265 VAC D3 1N4007 D4 1N4007 R1 4.7 kΩ T1 EF16 C2 3.3 µF 400 V D LinkZero-LP U1 LNK574DG FB D5 1N4148 R2 82 kΩ R3 113 kΩ 1% C5 220 nF 50 V D6 DL4003 BP/M S L1 1.0 mH C3 220 nF 50 V R4 9.09 kΩ 1% C4 1 nF 50 V PI-6086-072110 Figure 4. Schematic of 2.1 W, 6 V, 350 mA, 0.00 W Adapter/Charger. 4 Rev. B 12/07/10 www.powerint.com LNK574 consumption is determined by the BYPASS pin capacitor C3. No-load power consumption can be reduced by a capacitor with higher value. Higher C3 capacitor values will tend to increase the output ripple in PD mode - See LinkZero-LP Design Considerations section below. A clampless primary circuit is achieved due to the very tight tolerance current limit trimming techniques used in manufacturing the LinkZero-LP, plus the transformer construction techniques used. The peak drain voltage is therefore limited to typically less than 550 V at 265 VAC, providing significant margin to the 700 V minimum drain voltage specification (BVDSS). When the LinkZero-LP is in PD mode, the time taken for the BYPASS pin voltage to discharge to VBPPDRESET (~3 V) determines the duration of the PD off-time. The duration of the PD off time also determines the ripple on the output voltage. Output rectification and filtering is achieved with output rectifier D7 and filter capacitor C7. Due to the auto-restart feature, the average short circuit output current is significantly less than 1 A, allowing low current rating and low cost rectifier D7 to be used. Output circuitry is designed to handle a continuous short circuit on the power supply output. Although not necessary in this design, a preload resistor may be used at the output of the supply to reduce output voltage at no-load. In either case, C5 is completely discharged through R3 and R4 during the PD off time (D5 prevents the BYPASS capacitor C3 being discharged through this path). C5 is therefore kept as small as possible to reduce the power supply no-load input power consumption associated with recharging this capacitor at the start of the next PD on time. The minimum value of C5 is determined by the time constant set up with the feedback resistors R3 and R4 to avoid excessive cycle by cycle ripple on C5 influencing the output voltage regulation. The typical choice for C5 is between 100 nF and 330 nF. LinkZero-LP Power Down (PD) Mode Design Considerations The LinkZero-LP goes into PD mode when the output power supply load is reduced enough that 160 consecutive switching cycles are skipped twice with only one active switching cycle in between the two sets of 160 skipped switching cycles. This corresponds to ~0.6% of the full load power capability of the LinkZero-LP. Even when the power supply output load is completely removed, any preload resistor on the output and the components connected to the bias winding still represent a load on the transformer. The feedback circuitry connected to the bias winding should therefore be designed to represent <0.6% of the power supply full load. Otherwise LinkZero-LP will not be able to detect a no-load condition on the output and will not enter PD mode thereby disabling the benefit of zero no-load input power. In the case of the design of Figure 4, the power supply full load output power is 2.1 W (6 V, 350 mA). The bias winding load should therefore be designed to be <<0.6% of this (<12.6 mW). In the example of Figure 4, the average no-load voltage across bias winding capacitor C5 is approximately 20 V. The loading of R3, R4 and R2 (if used) should therefore be chosen to present <12.6 mW load with this bias voltage. In the case shown, the R2 path consumes ~3.3 mW and R3 and R4 also consumes ~3.3 mW. So the total consumption of 6.6 mW meets the criteria necessary to ensure the power supply will enter PD mode when the power supply load is removed. Adjusting the power consumption of the circuitry connected to the bias winding can therefore be used to adjust the power supply output power threshold at which the LinkZero-LP goes into PD mode. It can be seen therefore that, if desired, PD mode can be avoided altogether simply by adding a preload resistor on the output of the power supply or increasing the load on the bias winding to >0.6% (plus margin) of the power supply maximum power capability. If components D5 and R2 are not used in Figure 4, this time is determined purely by the choice of C3. If however D5 and R2 are used to provide an external BYPASS pin supply, then a combination of the energy stored in C5 and C3 determine the PD off time before the BYPASS pin voltage reaches the VBP(PU) (~3 V). When D5 and R2 are used, the minimum value of bias winding capacitor C5 is again governed by voltage regulation performance so the value of BYPASS pin capacitor C3 is typically reduced to reduce PD off time period if required. A minimum C3 value of 47 nF is recommended. PCB Layout Considerations LinkZero-LP Layout Considerations Layout See Figure 5 for a recommended circuit board layout for LinkZero-LP (U1). Single Point Grounding Use a single point ground (Kelvin) connection from the input filter capacitor to the area of copper connected to the SOURCE pins. Bypass Capacitor (CBP), FEEDBACK Pin Noise Filter Capacitor (CFB) and Feedback Resistors To minimize loop area, these two capacitors should be physically located as near as possible to the BYPASS and SOURCE pins, and FEEDBACK pin and SOURCE pins respectively. Also note that to minimize noise pickup, feedback resistors RFB1 and RFB2 are placed close to the FEEDBACK pin. Primary Loop Area The area of the primary loop that connects the input filter capacitor, transformer primary and LinkZero-LP should be kept as small as possible. Primary Clamp Circuit An external clamp may be used to limit peak voltage on the DRAIN pin at turn off. This can be achieved by using an RCD clamp or a Zener (~200 V) and diode clamp across the primary winding. In all cases, to minimize EMI, care should be taken to minimize the circuit path from the clamp components to the transformer and LinkZero-LP (U1). 5 www.powerint.com Rev. B 12/07/10 LNK574 DB CB RS CS DBP RBP DO RFB2 CFB CO CBP RFB1 R6 Transformer U1 J3 – HV DC IN T1 + – + LV DC OUT PI-6098-092410 Figure 5. PCB Layout of a 2.1 W, 6 V, 350 mA Charger. Thermal Considerations The copper area underneath the LinkZero-LP (U1) acts not only as a single point ground, but also as a heatsink. As it is connected to the quiet source node, this area should be maximized for good heat sinking of U1. The same applies to the cathode of the output diode. Y Capacitor The placement of the Y-type capacitor (if used) should be directly from the primary input filter capacitor positive terminal to the common/return terminal of the transformer secondary. Such a placement will route high magnitude common-mode surge currents away from U1. Note: If an input π EMI filter is used, the inductor in the π filter should be placed between the negative terminals on the input filter capacitors. Output Diode (DO) For best performance, the area of the loop connecting the secondary winding, the output diode (DO) and the output filter capacitor (CO)should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminals of the diode for heat sinking. A larger area is preferred at the electrically “quiet” cathode terminal. A large anode area can increase high frequency conducted and radiated EMI. Resistor RS and CS represent the secondary side RC snubber. Quick Design Checklist The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – Verify that VDS does not exceed 660 V at the highest input voltage and peak (overload) output power. This margin to the 700 V BVDSS specification gives margin for design variation, especially in clampless designs. 2. Maximum drain current – At maximum ambient temperature, maximum input voltage and peak output (overload) power, verify drain current waveforms for any signs of transformer saturation and excessive leading-edge current spikes at startup. Repeat under steady state conditions and verify that the leading-edge current spike event is below ILIMIT(MIN) at the end of the tLEB(MIN). Under all conditions, the maximum drain current should be below the specified absolute maximum ratings. 3. Thermal check – At specified maximum output power, minimum input voltage and maximum ambient temperature, verify that the temperature specifications are not exceeded for LinkZero-LP, transformer, output diode and output capacitors. Enough thermal margin should be allowed for part-to-part variation of the RDS(ON) of LinkZero-LP as specified in the data sheet. Under low line and maximum power, maximum LinkZero-LP source pin temperature of 100 °C is recommended to allow for these variations. 4. Negative drain voltages – clampless designs may allow the drain voltage to ring below source and cause reverse currents to flow from source to drain. Verify that any such current remains within the envelope shown in Figure 9. As with any power supply design, all LinkZero-LP designs should be verified on the bench to make sure that component specifications are not exceeded under worst-case conditions. 6 Rev. B 12/07/10 www.powerint.com LNK574 Absolute Maximum Ratings(1,6) DRAIN Voltage ............................................ ..............-0.3 V to 700 V Peak DRAIN Current LNK574...............................200 (375) mA(2) Peak Negative Pulsed Drain Current ............................. -100 mA(3) Feedback Voltage ......................................................... -0.3 V to 9 V Feedback Current ................................................................ 100 mA BYPASS Pin Voltage .................................................... -0.3 V to 9 V BYPASS Pin Voltage in Power Down Mode......... -0.3 V to 11 V(7) Storage Temperature ............................................ -65 °C to 150 °C Operating Junction Temperature...................... -40 °C to 150 °C(4) Lead Temperature ................................................................ 260 °C(5) Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. Higher peak DRAIN current allowed while DRAIN source voltage does not exceed 400 V. 3. Duration not to exceed 2 ms. 4. Normally limited by internal circuitry. 5. 1/16 in. from case for 5 seconds. 6. Maximum ratings specified may be applied, one at a time without causing permanent damage to the product. Exposure to Absolute Maximum ratings for extended periods of time may affect product reliability. 7. Maximum current into pin is 300 mA. Thermal Resistance Thermal Resistance: D Package: (qJA) ..................................100 °C/W(2); 80 °C/W(3) (qJC) ..........................................................30 °C/W(1) Parameter Notes: 1. Measured on the SOURCE pin close to plastic interface. 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. copper clad. 3. Soldered to 1 sq. in. (645 mm2), 2 oz. copper clad. Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max Units fOSC TJ = 25 °C VFB = 1.70 V, See Note C 93 100 107 kHz Control Functions Output Frequency Frequency Jitter Peak-Peak Jitter Compared to Average Frequency, TJ = 25 °C ±3 % TJ = 25 °C VFB = VFB(AR) See Note B 43 % % Ratio of Output Frequency at Auto-Restart to fOSC fOSC(AR) fOSC Maximum Duty Cycle DCMAX 60 63 FEEDBACK Pin Voltage at No Skipped Cycles VFB 1.63 1.70 FEEDBACK Pin Voltage at 99.4% Skipped Cycles VFB(NL) FEEDBACK Pin Voltage at AutoRestart VFB(AR) 1.77 1.37 0.8 0.9 V V 1.05 V 7 www.powerint.com Rev. B 12/07/10 LNK574 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max Units Control Functions (cont.) Minimum Switch ON-Time tON(MIN) BYPASS Pin Voltage BYPASS Pin Voltage Hysteresis BYPASS Pin Shunt Voltage ns IS1 FeedBack Voltage > VFB (MOSFET not Switching) 150 200 260 IS2 0.9 V ≤ VFB ≤ 1.70 V (MOSFET Switching) 200 250 310 ICH1 VBP = 0 V, TJ = 25 °C -5.5 -3.8 -1.8 ICH2 VBP = 4 V, TJ = 25 °C -3.8 -2.5 -1.0 VBP 5.60 5.85 6.10 V VBP(H) 0.8 1.0 1.2 V BPSHUNT 6.1 6.5 6.9 V DRAIN Supply Current BYPASS Pin Charge Current 700 mA mA Circuit Protection ILIMIT di/dt = 40 mA/ms TJ = 25 °C 126 136 146 mA Power Coefficient I2f di/dt = 40 mA/ms TJ = 25 °C 1665 1850 2091 A2Hz Leading Edge Blanking Time tLEB TJ = 25 °C 220 265 BYPASS Pin Shutdown Threshold Current ISD VBP = BPSHUNT See Note E 5.0 6.5 8.0 mA Thermal Shutdown Temperature TSD See Note B 135 142 150 °C Thermal Shutdown Hysteresis TSD(H) See Note B 70 Off-State Drain Leakage in Power Down Mode IDSS(PD) TJ = 25 °C, VDRAIN = 325 V See Figure 23 6.5 9 mA BYPASS Pin Overvoltage Protection in Power Down Mode VBP(PDP) IBP = 300 mA TJ ≤ 100 °C 7.25 8.5 10.9 V BYPASS Pin Power Up Reset Threshold (in Power Down Mode or at Power Supply Start-up) VBP(PU) 1.5 3 4 V Current Limit ns °C Power Down (PD) Mode 8 Rev. B 12/07/10 www.powerint.com LNK574 Parameter Symbol Conditions SOURCE = 0 V; TJ = -40 to 125 °C (Unless Otherwise Specified) Min Typ Max TJ = 25 °C 48 55 TJ = 100 °C 76 88 Units Output ON-State Resistance RDS(ON) Breakdown Voltage BVDSS ID = 13 mA VBP = 6.2 V, TJ = 25 °C DRAIN Supply Voltage Auto-Restart ON-Time tAR Auto-Restart OFF-Time Output Enable Delay 700 V 50 V VIN = 85 VAC, TJ = 25 °C, See Note D tEN W See Figure 8 145 ms 1.0 s 14 ms NOTES: A. IDSS is the worse case off state leakage specification at 80% of BVDSS and maximum operating junction temperature. B. This parameter is derived from characterization. C. Output frequency specification applies to low line input voltage in the final application. The controller is designed to reduce output frequency by approximately 20% at high line input voltages to balance low line and high line maximum output power. D. The auto-restart on-time/off-time is increased by 20% at high line input 265 VAC. E. LinkZero-LP shuts down if current into BYPASS pin reaches ISD at BPSHUNT voltage. 9 www.powerint.com Rev. B 12/07/10 LNK574 BP/M S FB S S 0-2 V 0.1 µF S1 D 470 Ω 5W S 50 V PI-6067-072110 Figure 6. General Test Circuit. DCMAX (internal signal) tP FB tEN VDRAIN tP = 1 fOSC PI-3707-112503 Figure 8. Output Enable Timing. PI-4021-101305 DRAIN Current (mA) Figure 7. Duty Cycle Measurement. 100 2 ms 0 -100 Time (ms) Figure 9. Peak Negative Pulsed DRAIN Current Waveform. 10 Rev. B 12/07/10 www.powerint.com LNK574 Typical Performance Characteristics 1.0 0.9 -50 -25 0 25 50 PI-6065-071910 1.2 Output Frequency (Normalized to 25 °C) PI-2213-012301 Breakdown Voltage (Normalized to 25 °C) 1.1 1.0 0.8 0.6 0.4 0.2 0 75 100 125 150 -50 -25 Junction Temperature (°C) 25 50 75 100 125 Junction Temperature (°C) Figure 10. Breakdown vs. Temperature. Figure 11. Frequency vs. Temperature. 1.0 0.8 PI-4057-071905 Current Limit (Normalized to 25 °C) 1.2 1.1 FEEDBACK Pin Voltage (Normalized to 25 °C) PI-6066-071910 1.4 1.0 0.6 0.4 0.2 0.9 0 0 50 100 -50 -25 150 0 25 50 75 100 125 150 Temperature (°C) Temperature (°C) Figure 12. Current Limit vs. Temperature. Figure 13. FEEDBACK Pin Voltage vs. Temperature. 6 5 4 3 2 1 200 175 DRAIN Current (mA) PI-2240-012301 7 PI-3927-083104 -50 BYPASS Pin Voltage (V) 0 25 °C 150 100 °C 125 100 75 50 25 0 0 0 0.2 0.4 0.6 0.8 Time (ms) Figure 14. BYPASS Pin Start-up Waveform (CBP = 0.22 mF). 1.0 0 2 4 6 8 10 12 14 16 18 20 DRAIN Voltage (V) Figure 15. Output Characteristics. 11 www.powerint.com Rev. B 12/07/10 LNK574 Typical Performance Characteristics (cont.) 100 Frequency (kHz) 100 10 PI-6068-071910 110 PI-3928-083104 Drain Capacitance (pF) 1000 90 80 70 1 60 0 100 200 300 400 500 0 600 10 20 Drain Voltage (V) 60 1.5 1.4 70 40 30 20 10 0 -10 -20 -30 0 10 20 30 40 50 60 70 80 90 100 0.0 Output Load (%) -6 -8 -10 -12 -14 -16 -18 -20 3.0 4.0 5.0 6.0 7.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 PI-6072-072110 FEEDBACK Pin Current (µA) -4 2.0 Figure 19. FEEDBACK Pin Input Characteristics. PI-6071-072110 -2 1.0 FEEDBACK Pin Voltage (V) Figure 18. FEEDBACK Pin Regulation Voltage Threshold vs. Output Load in CV Mode. 0 PI-6070-072110 FEEDBACK Pin Current (µA) 1.6 50 1.3 FEEDBACK Pin Current (µA) 50 Figure 17. Frequency Reduction vs. Duty Cycle (Line Voltage). PI-6069-072110 FEEDBACK Pin Voltage (V) 1.7 40 Duty Cycle (%) Figure 16. CDSS vs. Drain Voltage. 1.8 30 Auto-Restart 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 FEEDBACK Pin Voltage (V) Frequency Normalized to 1 Figure 20. FEEDBACK Pin Input Characteristics in CC Mode (1.7 V to 0.9 V). Figure 21. Frequency Cut Back in CC Mode Normalized to 1. 12 Rev. B 12/07/10 www.powerint.com LNK574 Typical Performance Characteristics (cont.) 0.9 9 Drain Current (µA) 0.8 0.7 0.6 0.5 0.4 0.3 8 7 6 5 4 3 0.2 2 0.1 1 0 PI-6111-081810 10 PI-6110-112310 BYPASS Pin Capacitor (µF) 1 0 0 200 400 600 800 1000 1200 1400 Power Down Off-Time (ms) Figure 22. Power Down Off-Time vs. BYPASS Pin Capacitor. VBP Start at 5.85 V (Temperature = 25 °C) -50 -25 0 25 50 75 100 125 Temperature (°C) Figure 23. Typical Drain Current vs. Temperature in Power Down Mode. 13 www.powerint.com Rev. B 12/07/10 LNK574 SO-8C (D Package) 4 B 0.10 (0.004) C A-B 2X 2 DETAIL A 4.90 (0.193) BSC A 4 8 D 5 2 3.90 (0.154) BSC GAUGE PLANE SEATING PLANE 6.00 (0.236) BSC C 0-8 1.04 (0.041) REF 0.10 (0.004) C D 2X 1 Pin 1 ID 4 0.25 (0.010) BSC 0.40 (0.016) 1.27 (0.050) 0.20 (0.008) C 2X 7X 0.31 - 0.51 (0.012 - 0.020) 0.25 (0.010) M C A-B D 1.27 (0.050) BSC 1.25 - 1.65 (0.049 - 0.065) 1.35 (0.053) 1.75 (0.069) o DETAIL A 0.10 (0.004) 0.25 (0.010) 0.10 (0.004) C H 7X SEATING PLANE 0.17 (0.007) 0.25 (0.010) C Reference Solder Pad Dimensions + 2.00 (0.079) + D07C 4.90 (0.193) + + 1.27 (0.050) Notes: 1. JEDEC reference: MS-012. 2. Package outline exclusive of mold flash and metal burr. 3. Package outline inclusive of plating thickness. 4. Datums A and B to be determined at datum plane H. 5. Controlling dimensions are in millimeters. Inch dimensions are shown in parenthesis. Angles in degrees. 0.60 (0.024) PI-4526-040110 Part Ordering Information • LinkZero Product Family • LinkZero-LP Series Number • Package Identifier D Plastic SO-8C • Package Material G GREEN: Halogen Free and RoHS Compliant • Tape & Reel and Other Options Blank LNK 574 D G - TL TL Standard Configurations Tape & Reel, 2.5 k pcs minimum for D Package. Not available for P Package. 14 Rev. B 12/07/10 www.powerint.com LNK574 Notes 15 www.powerint.com Rev. B 12/07/10 Revision Notes Date A Internal release. 10/12/10 B Updated text and parameter tables. 12/07/10 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CPAZero, SENZero, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2010, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters 5245 Hellyer Avenue San Jose, CA 95138, USA. Main: +1-408-414-9200 Customer Service: Phone: +1-408-414-9665 Fax: +1-408-414-9765 e-mail: [email protected] China (Shanghai) Room 1601/1610, Tower 1 Kerry Everbright City No. 218 Tianmu Road West Shanghai, P.R.C. 200070 Phone: +86-21-6354-6323 Fax: +86-21-6354-6325 e-mail: [email protected] China (Shenzhen) Rm A, B & C 4th Floor, Block C, Electronics Science and Technology Bldg., 2070 Shennan Zhong Rd, Shenzhen, Guangdong, China, 518031 Phone: +86-755-8379-3243 Fax: +86-755-8379-5828 e-mail: [email protected] Germany Rueckertstrasse 3 D-80336, Munich Germany Phone: +49-89-5527-3910 Fax: +49-89-5527-3920 e-mail: [email protected] India #1, 14th Main Road Vasanthanagar Bangalore-560052 India Phone: +91-80-4113-8020 Fax: +91-80-4113-8023 e-mail: [email protected] Italy Via De Amicis 2 20091 Bresso MI Italy Phone: +39-028-928-6000 Fax: +39-028-928-6009 e-mail: [email protected] Japan Kosei Dai-3 Bldg. 2-12-11, Shin-Yokohama, Kohoku-ku Yokohama-shi Kanagwan 222-0033 Japan Phone: +81-45-471-1021 Fax: +81-45-471-3717 e-mail: [email protected] Korea RM 602, 6FL Korea City Air Terminal B/D, 159-6 Samsung-Dong, Kangnam-Gu, Seoul, 135-728, Korea Phone: +82-2-2016-6610 Fax: +82-2-2016-6630 e-mail: [email protected] Taiwan 5F, No. 318, Nei Hu Rd., Sec. 1 Nei Hu Dist. Taipei, Taiwan 114, R.O.C. Phone: +886-2-2659-4570 Fax: +886-2-2659-4550 e-mail: [email protected] Europe HQ 1st Floor, St. James’s House East Street, Farnham Surrey GU9 7TJ United Kingdom Phone: +44 (0) 1252-730-141 Fax: +44 (0) 1252-727-689 e-mail: [email protected] Applications Hotline World Wide +1-408-414-9660 Singapore 51 Newton Road Applications Fax #15-08/10 Goldhill Plaza World Wide +1-408-414-9760 Singapore, 308900 Phone: +65-6358-2160 Fax: +65-6358-2015 e-mail: [email protected] Design Example Report Title <5 mW No-load Input Power, 2.1 W CV/CC Charger Using LinkZeroTM-LP LNK574DG Specification 85 VAC – 265 VAC Input; 6 V, 0.35 A Output Application LinkZero-LP Reference Design Author Applications Engineering Department Document Number DER-258 Date December 7, 2010 Revision 1.2 Summary and Features Ultra low no-load consumption, <5 mW at 230 VAC Primary side CV/CC controller eliminates secondary side control and optocoupler, provides low cost, low part count solution. EcoSmartTM – 70% average efficiency, exceeds standards requirement of 67%, and thus meets all existing and proposed harmonized energy efficiency standards including: CECP (China), CEC, EPA, AGO, European Commission FEEDBACK pin reference voltage varies with output load to provide excellent cross regulation as well as cable drop compensation. Meets EN550022 and CISPR-22 Class B conducted EMI with 10 dB margin. PATENT INFORMATION The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations' patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at <http://www.powerint.com/ip.htm>. Power Integrations 5245 Hellyer Avenue, San Jose, CA 95138 USA. Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 Table of Contents 1 2 3 4 Introduction.................................................................................................................3 Power Supply Specification ........................................................................................4 Circuit Diagram...........................................................................................................5 Circuit Description ......................................................................................................6 4.1 Input Rectification and Filtering ...........................................................................6 4.2 LinkZero-LP Primary ...........................................................................................6 4.3 Design of External Bias for LinkZero-LP..............................................................6 4.4 Primary Clamp and Transformer Construction ....................................................6 4.5 Output Rectification .............................................................................................7 4.6 Ultra-low No-load Input Power.............................................................................7 5 PCB Layout ................................................................................................................8 6 Bill of Materials ...........................................................................................................9 7 Transformer Specification.........................................................................................10 7.1 Electrical Diagram .............................................................................................10 7.2 Electrical Specifications.....................................................................................10 7.3 Materials............................................................................................................10 7.4 Transformer Build Diagram ...............................................................................11 7.5 Transformer Construction..................................................................................11 8 Transformer Design Spreadsheet.............................................................................12 9 Performance Data ....................................................................................................14 9.1 Efficiency ...........................................................................................................14 9.2 Active Mode CEC Measurement Data...............................................................15 9.2.1 USA Energy Independence and Security Act 2007 ....................................16 9.2.2 ENERGY STAR EPS Version 2.0 ..............................................................16 9.3 No-load Input Power..........................................................................................17 9.4 Available Standby Output Power.......................................................................18 9.5 Line and Load Regulation..................................................................................19 10 Thermal Performance ...........................................................................................20 11 Waveforms............................................................................................................21 11.1 Drain Voltage and Current, Normal Operation...................................................21 11.2 Output Voltage Start-Up Profile .........................................................................21 11.3 Drain Voltage and Current Start-Up Profile .......................................................22 11.4 Load Transient Response .................................................................................23 11.5 Output Ripple Measurements............................................................................24 11.5.1 Ripple Measurement Technique ................................................................24 11.5.2 Measurement Results ................................................................................25 12 Conducted EMI .....................................................................................................26 13 Statistical Data for the Design...............................................................................28 14 Revision History ....................................................................................................29 Important Note: Although this board was designed to satisfy safety isolation requirements, it has not been agency approved. Therefore, all testing should be performed using an isolation transformer to provide the AC input to the power supply. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 2 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 1 Introduction This report describes a universal input, 6 V, 350 mA flyback power supply using a LNK574DG device from the LinkZero-LP family of ICs. It contains the complete specification of the power supply, a detailed circuit diagram, the entire bill of materials required to build the supply, extensive documentation of the power transformer, along with test data and oscillographs of important electrical waveforms. Figure 1 – Populated Circuit Board Photographs. Page 3 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 2 Power Supply Specification The table below represents the minimum acceptable performance of the design. Actual performance is listed in the results section. Description Input Voltage Frequency No-load Input Power Output Output Voltage Output Ripple Voltage Output Current Total Output Power Continuous Output Power Efficiency Average efficiency Symbol Min Typ Max Units Comment VIN fLINE 85 47 265 64 5 VAC Hz mW 2 Wire – no P.E. 50/60 See V-I Curves, Figure 9, for limits 200 VOUT VRIPPLE IOUT 350 V mV mA POUT 2.1 W 70 % 6 67 230 VAC 20 MHz bandwidth Environmental Conducted EMI Meets CISPR22B / EN55015B Designed to meet IEC950, UL1950 Class II Safety Surge Ambient Temperature DM 0.5 kV CM 1 kV TAMB -5 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com 40 o C 1.2/50 s surge, IEC 1000-4-5, Series Impedance: Differential Mode: 2 Common Mode: 12 Free convection, sea level Page 4 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 3 Circuit Diagram Figure 2 – Schematic. Page 5 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 4 Circuit Description This flyback power supply was designed around the LNK574DG, U1 in Figure 2. The output voltage is sensed through the bias winding and fed back to U1 through resistor divider R3 and R4. That feedback is used by U1 to maintain Constant Voltage (CV) regulation of the output. 4.1 Input Rectification and Filtering Diodes D1-D4 rectifies the AC input which is then filtered by capacitors C1 and C2. Inductor L1, C1 and C2 form a pi (π) filter that attenuates differential mode conducted EMI. Resistor R1 provides high frequency damping. Shielding techniques (E-Shield™) were used in the construction of T1 to reduce common mode EMI displacement currents. This filter arrangement, the proprietary E-Shield techniques together with the IC frequency jitter function provide excellent EMI performance even without a Y capacitor or clamp network on the primary side. 4.2 LinkZero-LP Primary The power supply utilizes simplified bias winding voltage feedback, enabled by LNK574DG ON/OFF control. The voltage across C5 is determined by the FEEDBACK (FB) pin reference voltage and the resistor divider formed by R3 and R4. The FB pin reference voltage, which varies with load, is set to 1.36 V at no load and gradually increases to 1.70 V at full load to provide good output load regulation as well as cable drop compensation. In the CV region, U1 enables/disables switching cycles to maintain the FB pin reference voltage. Diode D6 and low cost ceramic capacitor C5 provide rectification and filtering of the primary feedback winding waveform. At increased loads, beyond the maximum power threshold, the IC transitions into the Constant Current (CC) region. In this region, the FB pin voltage begins to reduce as the power supply output voltage falls. In order to maintain a constant output current, the internal oscillator frequency is reduced in this region until it reaches typically 48% of the starting frequency. When the FB pin voltage drops below the auto-restart threshold (typically 0.9 V on the FB pin), the power supply enters the auto-restart mode. In this mode, the power supply will turn off for 1.2 s and then turn back on for 170 ms. The auto-restart function reduces the average output current during an output short-circuit condition. 4.3 Design of External Bias for LinkZero-LP Diode D5 and R2 form the external bias circuit and although this is not necessary for the operation of the LinkZero-LP family, its use can help to significantly improve the average efficiency of a power supply, especially at 230 VAC. During steady-state operation the external bias circuit supplies the IC bias current. Resistor R2 is chosen such that the bias winding supplies 200 A to 300 A into the BP pin. 4.4 Primary Clamp and Transformer Construction A clampless primary circuit is achieved due to the very tight tolerance current limit trimming techniques used in manufacturing the LNK574DG, plus the transformer construction techniques used. Peak drain voltage is therefore limited to typically less than Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 6 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 550 V at 265 VAC – providing significant margin to the 700 V maximum drain voltage (BVDSS). 4.5 Output Rectification Output rectification is provided by diode D7 and filtering is provided by capacitor C7. Resistor R5 and capacitor C6 provide high frequency filtering for improved EMI. 4.6 Ultra-low No-load Input Power The LinkZero-LP has a built in “power-down” (PD) mode wherein when 160 consecutive switching cycles have been skipped, the chip goes into the PD mode and inhibits switching and in addition, dramatically reduces its internal power consumption. The PD mode occurs when the output load has reduced to about 0.3% of full load. During PD mode the internal circuitry of the device completely shuts down and thus the capacitor connected to BYPASS (BP) pin C3 is discharged from 5.8 V. The controller wakes up to check output load conditions at a frequency determined by the user through the choice of the BP pin capacitor value. Once the BP pin voltage reaches 3 V, U1 powers up again and resumes switching. The no-load power consumption can be reduced further with a higher value for BP pin capacitor C3. If the load increases such that fewer than 160 cycles were skipped, the IC resumes normal operation. When U1 is in PD mode, the time taken for the BP pin voltage to discharge to VBPPDRESET (~3 V) determines the duration of the PD off-time. The duration of the PD off-time also determines the ripple on the output voltage. The total energy stored in C5 and C3 determine the PD off-time (and also the output ripple in PD mode). The typical choice for C5 is between 100 nF and 330 nF and for C3 is between 47 nF and 470 nF. Page 7 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 5 PCB Layout Figure 3 – Printed Circuit Board Layout (Dimensions in Inches). Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 8 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 6 Bill of Materials Ref Des C1 C2 C3 C4 C5 C6 Item 1 2 3 4 5 Qty 2 1 1 1 1 6 1 7 8 4 1 C7 D1 D2 D3 D4 D5 9 10 11 12 13 14 15 16 17 19 20 21 1 1 1 1 1 1 1 1 1 1 1 1 D6 D7 J3 L1 R1 R2 R3 R4 R5 RF1 T1 U1 Description 3.3 F, 400 V, Electrolytic, (8 x 11.5) 220 nF, 50 V, Ceramic, X7R, 0805 1000 pF, 50 V, Ceramic, X7R, 0805 220 nF, 50 V, Ceramic, X7R, 1206 220 pF, 100 V, Ceramic, X7R, 0805 330 F, 16 V, Electrolytic, Very Low ESR, 72 M, (8 x 11.5) Manufacturer P/N TAQ2G3R3MK0811MLL3 GRM21BR71H224KA01L ECJ-2VB1H102K ECJ-3YB1H224K ECJ-2VB2A221K Manufacturer Taicon Corporation Murata Panasonic Panasonic Panasonic EKZE160ELL331MHB5D Nippon Chemi-Con 1000 V, 1 A, Rectifier, DO-41 75 V, 300 mA, Fast Switching, DO-35 200 V, 1 A, Rectifier, Glass Passivated, DO-213AA (MELF) 50 V, 1 A, Schottky, DO-214AC 6 ft, 26 AWG, 2.1 mm connector (custom) 1 mH, 0.15 A, Ferrite Core 4.7 k, 5%, 1/8 W, Thick Film, 0805 82 k, 5%, 1/10 W, Thick Film, 0603 113 k, 1%, 1/16 W, Thick Film, 0603 9.09 k, 1%, 1/16 W, Thick Film, 0603 5.1 , 5%, 1/8 W, Thick Film, 0805 10 , 2 W, Fusible/Flame Proof Wire Wound Bobbin, EF16, Horizontal, 9 pins (5x4) LinkZero-LP, LNK574DG, SO-8 1N4007-E3/54 1N4148TR Vishay Vishay DL4003-13-F SS15-TP 3PH323A0 SBCP-47HY102B ERJ-6GEYJ472V ERJ-3GEYJ823V ERJ-3EKF1133V ERJ-3EKF9091V ERJ-6GEYJ5R1V CRF253-4 10R EF16HP09-QO LNK574DG Diodes Inc Micro commercial Co. Anam Instruments Tokin Panasonic Panasonic Panasonic Panasonic Panasonic Vitrohm TDK Power Integrations Note – All parts are RoHS compliant Page 9 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 7 Transformer Specification 7.1 Electrical Diagram 5 WD #2 Primary WD #1 feedback 108T #35 4 2 27T #35 x2 1 WD #3 Balance 9 WD #4 9T TIW #28 x 2 8 Secondary NC 9 T # 29 x 3 5 Figure 4 – Transformer Electrical Diagram. 7.2 Electrical Specifications Electrical Strength Primary Inductance Resonant Frequency Primary Leakage Inductance 7.3 1 second, 60 Hz, from pins 1-5 to pins 6-9 Pins 5-4, all other windings open, measured at 100 kHz, 0.4 VRMS Pins 5-4, all other windings open Pins 4-5, with pins 7-9 shorted, measured at 100kHz, 0.4 VRMS 3000 VAC 2.75 mH, 10% 520 kHz (Min.) 50 H (Max.) Materials Item [1] [2] [3] [4] [5] [6] [7] Description Core: PC44 EF16-Z, TDK or equivalent gapped for AL of 235.8 nH/T2 Bobbin: EE16X16H, Horizontal 9 pin Magnet Wire: #35 AWG Magnet Wire: #29 AWG Triple Insulated Wire: #28 AWG Tape: 3M 1298 Polyester Film, 2.0 mils thick, 9.8 mm wide Varnish Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 10 of 30 07-Dec-10 7.4 DER-258 2.1 W Universal Input Charger Transformer Build Diagram 8 9 Secondary Winding Balance Shield 5 NC 5 Primary Winding 4 1 2 Feedback Winding Figure 5 – Transformer Build Diagram. 7.5 Transformer Construction Bobbin Preparation WD#1 Feedback Insulation WD#2 Primary Insulation WD #3 Balance Shield Insulation WD #4 Secondary Insulation Grind Core Secure and Varnish Page 11 of 30 Primary pin side of the bobbin orients to the left hand side. Start on pin 2, wind 27 bifilar turns of item [3] from left to right. Wind with tight tension across entire bobbin evenly. Finish on pin 1. 1 layer of tape [6] for insulation Start on pin 4, wind 54 turns of item [3] from left to right. After finishing the first layer, placing one layer of tape [6]. Continue to wind the wire from right to left with another 54 turns. Finish on pin 5. 1 layer of tape [6] for insulation. Start on any pin on the secondary temporarily. Wind 9 trifilar turns of item [4], wind from right to left with tight tension uniformly, and connect end of winding to pin 5. Cut out wire connected to secondary side and leave this end not connected 1 layer of tape [6] for insulation. Start at pin 9, wind 9 bifilar turns of item [5] from right to left. Wind uniformly. After finishing the 9th turn, bring the wire back and finish it on pin 8. 3 layers of tape [6] for insulation. Grind the core to get 2.75 mH. Secure the core with tape. Secure the core with tape. Dip varnish for 3 minutes. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 8 Transformer Design Spreadsheet LinkZero-LP 052410; Rev.1.0; Copyright Power Integrations 2010 INPUT INFO ENTER APPLICATION VARIABLES VACMIN 85 VACMAX 265 fL 50 VO 6.00 IO 0.32 OUTPUT Volts Volts Hertz Volts Amps PO 1.92 Feedback Type BIAS Bias Winding Clampless design YES Clamples s N 0.70 0.7 Z 0.45 0.45 tC 2.90 CIN 10.00 Input Rectification Type UNIT Watts mSecond s uFarads F F LinkZero-LP 052410_Rev1-0.xls; LinkZero-LP Flyback Transformer Design Spreadsheet Minimum AC Input Voltage Maximum AC Input Voltage AC Mains Frequency Output Voltage (main) measured at the end of output cable (For CV/CC designs enter typical CV tolerance limit) Power Supply Output Current (For CV/CC designs enter typical CC tolerance limit) Output Power (VO x IO + dissipation in output cable) Choose 'BIAS' for Bias winding feedback and 'OPTO' for Optocoupler feedback from the 'Feedback Type' drop down box at the top of this spreadsheet Choose 'YES' from the 'Clampless Design' drop down box at the top of this spreadsheet for a clampless design. Choose 'NO' to add an external clamp circuit. Clampless design lowers the total cost of the power supply Efficiency Estimate at output terminals. For CV only designs enter 0.7 if no better data available Loss Allocation Factor (Secondary side losses / Total losses) Bridge Rectifier Conduction Time Estimate Input Capacitance Choose H for Half Wave Rectifier and F for Full Wave Rectification from the 'Rectification' drop down box at the top of this spreadsheet ENTER LinkZero-LP VARIABLES LinkZero-LP Auto LinkZero-LP device. LNK574 LNK57 4 Chosen Device ILIMITMIN ILIMITMAX fSmin 0.126 0.146 93000 Amps Amps Hertz I^2fMIN 1664.64 A^2Hz I^2fTYP 1849.6 A^2Hz 78 10 0.5 Volts Volts Volts VOR VDS VD 78.00 KP 1.60 ENTER TRANSFORMER CORE/CONSTRUCTION VARIABLES Core Type EF16 EF16 EF16 P/N: Core EF16_BOBBIN P/N: Bobbin AE 0.201 cm^2 LE 3.76 cm AL 1100 nH/T^2 BW 10 mm M L NS NB 0 9 2 9 28 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com mm Minimum Current Limit Maximum Current Limit Minimum Device Switching Frequency I^2f Minimum value (product of current limit squared and frequency is trimmed for tighter tolerance) I^2f typical value (product of current limit squared and frequency is trimmed for tighter tolerance) Reflected Output Voltage LinkZero-LP on-state Drain to Source Voltage Output Winding Diode Forward Voltage Drop Ripple to Peak Current Ratio (0.9<KRP<1.0 : 1.0<KDP<6.0) User-Selected transformer core PC40EF16-Z EF16_BOBBIN Core Effective Cross Sectional Area Core Effective Path Length Ungapped Core Effective Inductance Bobbin Physical Winding Width Safety Margin Width (Half the Primary to Secondary Creepage Distance) Number of primary layers Number of Secondary Turns Number of Bias winding turns Page 12 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger VB 19.50 Volts R1 113.00 k-ohms R2 8.87 k-ohms RBP 86.6 k-ohms CFB 680.00 CBP 220.00 Recommended Bias 1N4003 Diode DC INPUT VOLTAGE PARAMETERS VMIN 103 VMAX 375 CURRENT WAVEFORM SHAPE PARAMETERS DMAX 0.37 IAVG 0.03 IP 0.1260 IR 0.1260 IRMS 0.05 TRANSFORMER PRIMARY DESIGN PARAMETERS LP 2724 LP_TOLERANCE 10 pF nF Volts Volts Minimum DC Input Voltage Maximum DC Input Voltage Amps Amps Amps Amps Maximum Duty Cycle Average Primary Current Minimum Peak Primary Current Primary Ripple Current Primary RMS Current uHenries % NP 108 ALG 234 nH/T^2 BM 1832 Gauss BAC 916 Gauss ur 1637 LG 0.10 mm BWE OD 20 0.185 mm mm INS 0.04 mm DIA 0.145 mm 35 AWG CM 32 Cmils Cmils/A mp Info 676 TRANSFORMER SECONDARY DESIGN PARAMETERS Lumped parameters ISP 1.51 ISRMS 0.62 IRIPPLE 0.53 CMS 124 Amps Amps Amps Cmils AWGS 29 AWG 0.29 mm DIAS ODS 1.11 mm INSS VOLTAGE STRESS PARAMETERS 0.41 mm VDRAIN PIVS Page 13 of 30 Typical Primary Inductance. +/- 10% Primary inductance tolerance Primary Winding Number of Turns AWG CMA Bias Winding Voltage Upper Resistor in the resistor divider component between bias wiinding and FB pin of LinkZero-LP Lower Resistor in the resistor divider component between bias wiinding and FB pin of LinkZero-LP Optional BP pin resistor (connected between BP pin and bias winidng) to improve efficiency FB pin resistor (Improve noise sensitivity) BP pin capacitor Place this diode on the return leg of the bias winding for optimal EMI. - Volts 37 Volts Gapped Core Effective Inductance Maximum Operating Flux Density, BM<2000 is recommended AC Flux Density for Core Loss Curves (0.5 X Peak to Peak) Relative Permeability of Ungapped Core !!! Info. Gap sizes below 0.1 mm may cause manufacturing tolerancing problems - please verify with magnetics vendor. Increase LG > 0.1 mm (increase NS, decrease VOR,bigger Core) Effective Bobbin Width Maximum Primary Wire Diameter including insulation Estimated Total Insulation Thickness (= 2 * film thickness) Bare conductor diameter Primary Wire Gauge (Rounded to next smaller standard AWG value) Bare conductor effective area in circular mils CAN DECREASE CMA < 500 (decrease L(primary layers),increase NS,use smaller Core) Peak Secondary Current Secondary RMS Current Output Capacitor RMS Ripple Current Secondary Bare Conductor minimum circular mils Secondary Wire Gauge (Rounded up to next larger standard AWG value) Secondary Minimum Bare Conductor Diameter Secondary Maximum Outside Diameter for Triple Insulated Wire Maximum Secondary Insulation Wall Thickness Peak Drain Voltage is highly dependent on Transformer capacitance and leakage inductance. Please verify this on the bench and ensure that it is below 650 V to allow 50 V margin for transformer variation. Output Rectifier Maximum Peak Inverse Voltage Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 9 Performance Data The ON/OFF control scheme employed by LinkZero-LP helps to yield virtually constant efficiency across the 25% to 100% load range required for compliance with EPA, CEC, CECP and AGO energy efficiency standards for external power supplies (EPS). This performance is automatic with ON/OFF control. There are no special burst modes that require the designer to consider specific thresholds within the load range in order to achieve compliance with global energy efficiency standards. All measurements performed at room temperature, 50 Hz input frequency. 9.1 Efficiency 80 85 VAC 115 VAC 230 VAC 265 VAC Efficiency (%) 75 70 65 60 55 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 Output Current (A) Figure 6 – Efficiency vs. Output Current, Room Temperature, 60 Hz. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 14 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger Percent of Full Load 25 50 75 100 Average US EISA (2007) requirement ENERGY STAR 2.0 requirement Efficiency (%) 115 VAC 230 VAC 74.9 74.6 73.7 72.9 74.0 68.9 70.0 70.9 70.2 70.0 57 67 9.2 Active Mode CEC Measurement Data The external power supply requirements below all require meeting active mode efficiency and no-load input power limits. Minimum active mode efficiency is defined as the average efficiency of 25, 50, 75 and 100% of output current (based on the nameplate output current rating). For adapters that are single input voltage only then the measurement is made at the rated single nominal input voltage (115 VAC or 230 VAC), for universal input adapters the measurement is made at both nominal input voltages (115 VAC and 230 VAC). To meet the standard the measured average efficiency (or efficiencies for universal input supplies) must be greater than or equal to the efficiency specified by the standard. The test method can be found here: http://www.energystar.gov/ia/partners/prod_development/downloads/power_supplies/EP SupplyEffic_TestMethod_0804.pdf For the latest up to date information please visit the PI Green Room: http://www.powerint.com/greenroom/regulations.htm Page 15 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 9.2.1 USA Energy Independence and Security Act 2007 This legislation mandates all single output single output adapters, including those provided with products, manufactured on or after July 1st, 2008 must meet minimum active mode efficiency and no load input power limits. Active Mode Efficiency Standard Models Nameplate Output (PO) Minimum Efficiency in Active Mode of Operation 0.5 PO 0.09 ln (PO) + 0.5 0.85 ln = natural logarithm <1W 1 W to 51 W > 51 W No-load Energy Consumption Nameplate Output (PO) Maximum Power for No-load AC-DC EPS All 0.5 W This requirement supersedes the legislation from individual US States (for example CEC in California). 9.2.2 ENERGY STAR EPS Version 2.0 This specification takes effect on November 1st, 2008. Active Mode Efficiency Standard Models Nameplate Output (PO) Minimum Efficiency in Active Mode of Operation 1W 0.48 PO + 0.14 > 1 W to 49 W > 49 W 0.0626 ln (PO) + 0.622 0.87 ln = natural logarithm Active Mode Efficiency Low Voltage Models (VO<6 V and IO 550 mA) Nameplate Output (PO) Minimum Efficiency in Active Mode of Operation 1W 0.497 PO + 0.067 > 1 W to 49 W 0.075 ln (PO) + 0.561 > 49 W 0.86 ln = natural logarithm No-load Energy Consumption (both models) Nameplate Output (PO) Maximum Power for No-load AC-DC EPS 0 to < 50 W 0.3 W 50 W to 250 W 0.5 W Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 16 of 30 07-Dec-10 9.3 DER-258 2.1 W Universal Input Charger No-load Input Power 7 Input Power (mW) 6 5 4 3 2 1 80 100 120 140 160 180 200 220 240 Input Voltage (VAC) Figure 7 – No-load Input Power vs. Input Line Voltage, Room Temperature, 50 Hz. Page 17 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com 260 DER-258 2.1 W, Universal Input Charger 07-Dec-10 9.4 Available Standby Output Power The chart below shows the available output power vs. line voltage for an input power of 0.3 W, 0.5 W, 1 W and 2 W. 2 1.8 0.3 W 0.5 W 1W 2W Standby Power (W) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 80 100 120 140 160 180 200 220 240 260 Input Votage (VAC) Figure 8 – Available Output Power for 0.2 W, 0.5 W, 1 W and 2 W Input Power. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 18 of 30 07-Dec-10 Output Voltage (VDC) 9.5 DER-258 2.1 W Universal Input Charger Line and Load Regulation 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 85 VAC 230 VAC MIN 0 100 200 300 400 500 600 700 800 115 VAC 265 VAC MAX 900 1000 1100 1200 Output Current (mA) Figure 9 – Load and Line Regulation, Room Temperature. Page 19 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 10 Thermal Performance Temperature measurements of key components were taken using T-type thermocouples. The thermocouples were soldered directly to a SOURCE pin of the LNK574DG device and to the cathode of the output rectifier D7. The thermocouples were glued to the external core and winding surfaces of transformer T1. Temperature °C 85 VAC 265 VAC Ambient Inside Box* 51.0 51.0 LNK574DG 72.0 90.0 Transformer 70.0 73.0 Output Diode 63.0 67.0 *To simulate operation inside sealed enclosure at 40 C external ambient. Item These results show that all the parts in the board have thermal margin to run at 50 ºC ambient. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 20 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 11 Waveforms 11.1 Drain Voltage and Current, Normal Operation Figure 10 – 85 VAC, Full Load. Upper: VDRAIN, 100 V / div. (MAX DRAIN VOLTAGE = 250 V). Lower: IDRAIN, 0.1 A, 10 s / div. Figure 11 – 265 VAC, Full Load. Upper: VDRAIN, 200 V / div. (MAX DRAIN VOLTAGE = 500 V). Lower: IDRAIN, 0.1 A, 10 s / div. 11.2 Output Voltage Start-Up Profile Start-up into full resistive load and no-load were both verified. An 18 resistor was used for the load, to maintain a 0.35 A under steady-state conditions. Figure 12 – Start-Up Profile, 115 VAC. Fast Trace is at No-load. Slower Trace is at Maximum Load. 1 V, 5 ms / div. Page 21 of 30 Figure 13– Start-Up Profile, 230 VAC. Fast Trace is at No-load. Slower Trace is at Maximum Load. 1 V, 5 ms / div. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 11.3 Drain Voltage and Current Start-Up Profile Figure 14 – 85 VAC Input and Maximum Load. Upper: VDRAIN, 100 V / div. Lower: IDRAIN, 0.1 A, 1 ms / div. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Figure 15 – 265 VAC Input and Maximum Load. Upper: VDRAIN, 200 V / div. Lower: IDRAIN, 0.1 A, 1 ms / div. Page 22 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 11.4 Load Transient Response Figure 16 – Transient Response, 115VAC, 2 mA to 350 mA to 2 mA. Upper: VOUT 1 V / div. Lower: IOUT 0.2 A, 10 ms / div. Figure 17 – Transient Response, 230VAC, 2 mA to 350 mA to 2 mA. Upper: VOUT 1 V / div. Lower: IOUT 0.2 A, 10 ms / div. Figure 18 – Transient Response, 115VAC, 170 mA to 262 mA to 170 mA. Upper: VOUT 0.2 V / div. Lower: IOUT 0.2 A, 10 ms / div. Figure 19 – Transient Response, 230VAC, 170 mA to 262 mA to 170 mA. Upper: VOUT 0.2 V / div. Lower: IOUT 0.2 A, 10 ms / div. Page 23 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 11.5 Output Ripple Measurements 11.5.1 Ripple Measurement Technique A modified oscilloscope test probe was used to take output ripple measurements, in order to reduce the pickup of spurious signals. Using the probe adapter pictured below, the output ripple was measured with a 1 F electrolytic, and a 0.1 F ceramic capacitor connected as shown. Probe Ground Probe Tip Figure 20 – Oscilloscope Probe Prepared for Ripple Measurement (End Cap and Ground Lead Removed). Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 24 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 11.5.2 Measurement Results The maximum voltage ripple at the output terminals of the power supply was measured as 80 mV, well below 200 mV specification limit. Figure 21 – Ripple, 85 VAC, Full Load. 100 s, 50 mV / div. Figure 22 – Ripple, 115 VAC, Full Load. 20 s, 50 mV / div. Figure 23 – Ripple, 230 VAC, Full Load. 100 s, 50 mV / div. Figure 24 – Ripple, 265 VAC, Full Load. 100 s, 50 mV / div. Page 25 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 12 Conducted EMI Conducted emissions tests were performed at 115 VAC and 230 VAC at maximum load. Measurements were taken with an Artificial Hand connected to a load resistor. EMI of line and neutral were scanned into one picture and the load resistance was adjusted for maximum power output. Composite EN55022B / CISPR22B conducted limits are shown. In all cases there was excellent (~10 dB) margin. Figure 25 – Conducted EMI at 115 VAC, Artificial Hand, 6.2 V, 0.362 A. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 26 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger Figure 26 – Conducted EMI at 230 VAC, Artificial Hand, 6.05 V, 0.373 A. Page 27 of 30 Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 13 Statistical Data for the Design The following is some statistical data collected from 50 DER-258 design boards to demonstrate the repeatability and variation of certain measurements over a relatively large sample size, line voltage and temperature. Figure 27 – Cold Temperature Regulation. CVCC Response Measured at -5 ºC and 90 VAC. Figure 28 – Cold Temperature Regulation. CVCC Response Measured at -5 ºC and 265 VAC. Figure 29 – High Ambient Regulation. CVCC Response Measured at 40 ºC and 90 VAC. Figure 30 – High Ambient Regulation. CVCC Response Measured at 40 ºC and 265 VAC. Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com Page 28 of 30 07-Dec-10 DER-258 2.1 W Universal Input Charger 14 Revision History Date 07-Dec-10 Page 29 of 30 Author PL Revision 1.2 Description & changes Initial Release Reviewed Apps and Mktg Power Integrations Tel: +1 408 414 9200 Fax: +1 408 414 9201 www.powerint.com DER-258 2.1 W, Universal Input Charger 07-Dec-10 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. PATENT INFORMATION The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of Power Integrations’ patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. The PI Logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, CAPZero, SENZero, LinkZero, HiperLCS, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StackFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©Copyright 2010 Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations WORLD HEADQUARTERS 5245 Hellyer Avenue San Jose, CA 95138, USA. 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