19-4195; Rev 2; 9/10
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``````````````````````````````` ࢾ৪ቧᇦ
PART
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
48 TQFN-EP*
ިဉਜ਼ጛኧ߅ስ
MAX19515ETM+
ܣቑါጥܭਜ਼ࢅၫૹݧ
+ܭာᇄ)Qc*0९SpITܪᓰࡼॖᓤă
*FQ! >! ൡă
ၫᔊ૦ࢻਫ਼
୭ᒙᏴၫᓾ೯ࡼᔢઁ߲ă
TQJဵNpupspmb-! Jod/ࡼܪă
________________________________________________________________ Maxim Integrated Products
1
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षᆰNbyjnࡼᒦᆪᆀᐶǖdijob/nbyjn.jd/dpnă
NBY2:626
``````````````````````````````````` গၤ
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ABSOLUTE MAXIMUM RATINGS
OVDD, AVDD to GND............................................-0.3V to +3.6V
CMA, CMB, REFIO, INA+, INA-, INB+,
INB- to GND ......................................................-0.3V to +2.1V
CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN
to GND ..........-0.3V to the lower of (VAVDD + 0.3V) and +3.6V
DCLKA, DCLKB, D9A–D0A, D9B–D0B, DORA, DORB
to GND..........-0.3V to the lower of (VOVDD + 0.3V) and +3.6V
Continuous Power Dissipation (TA = +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/°C
above +70°C).............................................................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
INL
fIN = 3MHz
-0.8
±0.25
+0.8
LSB
Differential Nonlinearity
DNL
fIN = 3MHz
-0.7
±0.2
+0.7
LSB
Offset Error
OE
Internal reference
-0.4
±0.1
+0.4
%FS
Gain Error
GE
External reference = 1.25V
-1.5
±0.3
+1.5
%FS
ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)
Differential Input-Voltage Range
VDIFF
Differential or single-ended inputs
Common-Mode Input-Voltage
Range
VCM
(Note 2)
1.5
0.4
Fixed resistance
Input Resistance
RIN
Input Current
Input Capacitance
1.4
V
> 100
Differential input resistance, common mode
connected to inputs
4
IIN
Switched capacitance input current, each
input
35
CPAR
Fixed capacitance to ground, each input
0.7
Switched capacitance, each input
1.2
CSAMPLE
VP-P
kΩ
μA
pF
CONVERSION RATE
Maximum Clock Frequency
fCLK
Minimum Clock Frequency
fCLK
Data Latency
2
65
MHz
30
Figures 9, 10
9
_______________________________________________________________________________________
MHz
Cycles
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Small-Signal Noise Floor
Signal-to-Noise Ratio
SSNF
SNR
fIN = 70MHz, < -35dBFS
-60.4
fIN = 3MHz
60.2
fIN = 70MHz
59.3
fIN = 175MHz
Signal-to-Noise Plus Distortion
Ratio
fIN = 70MHz
Spurious-Free Dynamic Range
(4th and Higher Harmonics)
Second Harmonic
SFDR2
HD2
Third Harmonic
HD3
Total Harmonic Distortion
Third-Order Intermodulation
Full-Power Bandwidth
THD
IM3
fIN = 70MHz
85
73
81
fIN = 3MHz
82
74.4
dBc
84
fIN = 175MHz
fIN = 70MHz
dB
59.6
59.3
fIN = 3MHz
SFDR1
dBFS
59.7
58.8
fIN = 175MHz
Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)
60.1
59.8
fIN = 3MHz
SINAD
dBFS
dBc
82
fIN = 175MHz
82
fIN = 3MHz
-86
fIN = 70MHz
-86
fIN = 175MHz
-82
fIN = 3MHz
-86
fIN = 70MHz
-86
fIN = 175MHz
-82
fIN = 3MHz
-80
fIN = 70MHz
-79
fIN = 175MHz
-77
fIN = 70MHz ±1.5MHz, -7dBFS
-90
fIN = 175MHz ±2.5MHz, -7dBFS
-80
-73
dBc
-74
dBc
-71.8
dBc
dBc
FPBW
850
Aperture Delay
tAD
850
ps
Aperture Jitter
tAJ
0.3
psRMS
1
Cycles
Overdrive Recovery Time
±10% beyond full scale
MHz
_______________________________________________________________________________________
3
NBY2:626
ELECTRICAL CHARACTERISTICS (continued)
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERCHANNEL CHARACTERISTICS
Crosstalk
fINA or fINB = 70MHz at -1dBFS
95
fINA or fINB = 175MHz at -1dBFS
85
dBc
Gain Match
fIN = 70MHz
±0.05
dB
Offset Match
fIN = 70MHz
±0.1
%FSR
Phase Match
fIN = 70MHz
±0.5
Degrees
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage
VCOM
Default programmable setting
0.85
0.9
0.95
1.25
1.27
V
INTERNAL REFERENCE
REFIO Output Voltage
REFIO Temperature Coefficient
VREFOUT
1.23
V
TCREF
< ±60
ppm/°C
REFIO Input-Voltage Range
VREFIN
1.25 +5/
-10%
V
REFIO Input Resistance
RREFIN
10
±20%
kΩ
0.4 to 2.0
VP-P
EXTERNAL REFERENCE
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage
Self-biased
Differential Input Common-Mode
Voltage
1.2
DC-coupled clock signal
Input Resistance
RCLK
Input Capacitance
CCLK
V
1.0 to 1.4
Differential, default
10
kΩ
Differential, internal termination selected
100
Ω
Common mode
9
kΩ
To ground, each input
3
pF
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (VCLK- < 0.1V)
Single-Ended Mode Selection
Threshold (VCLK-)
0.1
Allowable Logic Swing (VCLK+)
0 - VAVDD
Single-Ended Clock Input High
Threshold (VCLK+)
Input Leakage (CLK-)
Input Capacitance (CLK+)
4
V
1.5
V
Single-Ended Clock Input Low
Threshold (VCLK+)
Input Leakage (CLK+)
0.3
VCLK+ = VAVDD = 1.8V or 3.3V
+0.5
VCLK+ = 0V
-0.5
VCLK- = 0V
-150
V
-50
3
_______________________________________________________________________________________
V
μA
μA
pF
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUT (SYNC)
Allowable Logic Swing
0 - VAVDD
Sync Clock Input High Threshold
V
1.5
V
Sync Clock Input Low Threshold
0.3
VSYNC = VAVDD = 1.8V or 3.3V
Input Leakage
VSYNC = 0V
+0.5
-0.5
Input Capacitance
V
μA
4.5
pF
0 - VAVDD
V
DIGITAL INPUTS (SHDN, CS)
Allowable Logic Swing
Input High Threshold
1.5
V
Input Low Threshold
0.3
VSHDN/VSPEN = VAVDD = 1.8V or 3.3V
Input Leakage
VSHDN/VSPEN = 0V
Input Capacitance
+0.5
-0.5
CDIN
V
μA
3
pF
0 - VAVDD
V
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE
Allowable Logic Swing
Input High Threshold
1.5
V
Input Low Threshold
0.3
VSCLK/VSDIN/VCS = VAVDD = 1.8V or 3.3V
Input Leakage
VSCLK/VSDIN/VCS = 0V
Input Capacitance
+0.5
-0.5
CDIN
3
V
μA
pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = VAVDD)—PARALLEL CONTROL MODE (Figure 5)
Input Pullup Current
Input Pulldown Current
Open-Circuit Voltage
VOC
VSCLK/VSDIN/VCS = VAVDD = 1.8V
7
12
17
VSCLK/VSDIN/VCS = VAVDD = 3.3V
16
21
26
VSCLK/VSDIN/VCS = 0V, VAVDD = 1.8V
-65
-50
-35
VSCLK/VSDIN/VCS = 0V, VAVDD = 3.3V
-105
-90
-75
VAVDD = 1.8V
1.35
1.45
1.55
VAVDD = 3.3V
2.58
2.68
2.78
μA
μA
V
DIGITAL OUTPUTS (75Ω, D0–D9 (A and B Channel), DCLKA, DCLKB, DORA, DORB)
Output-Voltage Low
VOL
Output-Voltage High
VOH
Three-State Leakage Current
ILEAK
ISINK = 200μA
ISOURCE = 200μA
0.2
VOVDD
- 0.2
VOVDD applied
GND applied
V
+0.5
-0.5
V
μA
_______________________________________________________________________________________
5
NBY2:626
ELECTRICAL CHARACTERISTICS (continued)
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-MANAGEMENT CHARACTERISTICS
Wake-Up Time from Shutdown
tWAKE
Internal reference, CREFIO = 0.1μF (10τ)
5
ms
Wake-Up Time from Standby
tWAKE
Internal reference
15
μs
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)
SCLK Period
tSCLK
50
ns
SCLK to CS Setup Time
tCSS
10
ns
SCLK to CS Hold Time
tCSH
10
ns
SDIN to SCLK Setup Time
tSDS
Serial-data write
10
ns
SDIN to SCLK Hold Time
tSDH
Serial-data write
0
SCLK to SDIN Output Data Delay
tSDD
Serial-data read
ns
10
ns
TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9) (Default Timing, see Table 5)
Clock Pulse-Width High
tCH
7.69
ns
Clock Pulse-Width Low
tCL
7.69
ns
tCH/tCLK
30 to 70
%
Clock Duty Cycle
Data Delay After Rising Edge of
CLK+
tDD
CL = 10pF, VOVDD = 1.8V (Note 2)
3.4
CL = 10pF, VOVDD = 3.3V
5.3
7.1
4.1
ns
Data to DCLK Setup Time
tSETUP
CL = 10pF, VOVDD = 1.8V (Note 2)
12.8
13.4
ns
Data to DCLK Hold Time
tHOLD
CL = 10pF, VOVDD = 1.8V (Note 2)
1.4
2.0
ns
TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10) (Default Timing, see Table 5)
Clock Pulse-Width High
Clock Pulse-Width Low
Clock Duty Cycle
Data Delay After Rising Edge of
CLK+
tCH
7.69
ns
tCL
7.69
ns
tCH/tCLK
30 to 70
tDD
CL = 10pF, VOVDD = 1.8V (Note 2)
3.3
CL = 10pF, VOVDD = 3.3V
5.2
%
7.0
4.0
ns
Data to DCLK Setup Time
tSETUP
CL = 10pF, VOVDD = 1.8V (Note 2)
5.0
5.9
ns
Data to DCLK Hold Time
tHOLD
CL = 10pF, VOVDD = 1.8V (Note 2)
1.2
1.8
ns
DCLK Duty Cycle
tDCH/tCLK
CL = 10pF, VOVDD = 1.8V (Note 2)
44
50
56
%
MUX Data Duty Cycle
tCHA/tCLK
CL = 10pF, VOVDD = 1.8V (Note 2)
44
50
56
%
TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)
Setup Time for Valid Clock Edge
tSUV
Edge mode (Note 2)
0.7
ns
Hold-Off Time for Invalid Clock
Edge
tSDH
Edge mode (Note 2)
0.5
ns
Minimum Synchronization Pulse
Width
6
Relative to input clock period
2
_______________________________________________________________________________________
Cycles
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
VAVDD
Digital Output Supply Voltage
VOVDD
Low-level VAVDD
1.7
1.9
High-level VAVDD (regulator mode, invoked
automatically)
2.3
3.5
1.7
Dual channel
Analog Supply Current
Analog Power Dissipation
Digital Output Supply Current
IAVDD
PDA
IOVDD
3.5
47
28
Standby mode
8.5
12
Power-down mode
0.65
0.9
Power-down mode, VAVDD = 3.3V
1.6
Dual channel
85
Dual channel, VAVDD = 3.3V
155
Single channel active
50
Standby mode
15
22
Power-down mode
1.2
1.6
Power-down mode, VAVDD = 3.3V
2.9
Dual-channel mode, CL = 10pF
13
< 0.1
V
55
Single channel active
Power-down mode
V
mA
99
mW
mA
Note 1: Specifications ≥ +25°C guaranteed by production test, specifications < +25°C guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
_______________________________________________________________________________________
7
NBY2:626
ELECTRICAL CHARACTERISTICS (continued)
``````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
3MHz SINGLE-ENDED INPUT FFT PLOT
-100
-60
-100
-120
10
15
20
25
FREQUENCY (MHz)
30
175MHz INPUT FFT PLOT
10
15
20
25
FREQUENCY (MHz)
30
0
-100
0
-40
-60
-80
-100
-120
10
15
20
25
30
5
10
15
20
25
FREQUENCY (MHz)
0.8
0
0.2
DNL (LSB)
0.4
0.2
0
-0.2
90
0
-0.2
SFDR2
SFDR1
80
75
-THD
70
65
-0.6
-0.6
60
-0.8
-0.8
55
-1.0
-1.0
50
1024
SNR
0
256
512
768
DIGITAL OUTPUT CODE
30
85
-0.4
256
512
768
DIGITAL OUTPUT CODE
10
15
20
25
FREQUENCY (MHz)
PERFORMANCE vs. INPUT FREQUENCY
-0.4
0
5
95
PERFORMANCE (dBFS)
0.6
0.4
MAX19515 toc03
-80
30
MAX19515 toc08
1.0
MAX19515 toc07
0.6
-60
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.8
-40
-120
0
FREQUENCY (MHz)
1.0
30
-100
-120
5
10
15
20
25
FREQUENCY (MHz)
fIN1 = 172.49286MHz
fIN2 = 177.50202MHz
-20
AMPLITUDE (dBFS)
-80
0
5
175MHz TWO-TONE IMD
fIN1 = 71.496925MHz
fIN2 = 68.504600MHz
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-60
5
0
MAX19515 toc04
fIN = 175.096626MHz
AIN = -0.512dBFS
SNR = 59.073dB
SINAD = 59.022dB
THD = -78.338dBc
SFDR1 = 81.806dBc
SFDR2 = 84.255dBc
-40
-80
70MHz TWO-TONE IMD PLOT
0
-20
-60
-120
0
MAX19515 toc05
5
-40
-100
-120
0
8
MAX19515 toc02
-80
fIN = 70.1014328MHz
AIN = -0.532dBFS
SNR = 59.432dB
SINAD = 58.388dB
THD = -79.349dBc
SFDR1 = 84.227dBc
SFDR2 = 81.877dBc
-20
MAX19515 toc06
-80
-40
70MHz INPUT FFT PLOT
0
AMPLITUDE (dBFS)
-60
fIN = 2.99877166748047MHz
AIN = -0.546dBFS
SNR = 59.675dB
SINAD = 59.632dB
THD = -79.673dBc
SFDR1 = 88.737dBc
SFDR2 = 82.290dBc
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
MAX19515 toc01
fIN = 2.99877166MHz
AIN = -0.532dBFS
SNR = 59.682dB
SINAD = 59.641dB
THD = -79.826dBc
SFDR1 = 83.946dBc
SFDR2 = 82.852dBc
-20
0
1024
MAX19515 toc09
3MHz INPUT FFT PLOT
0
INL (LSB)
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
0
50
SINAD
100 150 200 250 300 350 400
INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
80
SFDR1
70
65
SNR
100
PERFORMANCE (dBFS)
85
SFDR1
-THD
SFDR2
90
80
-THD
70
SFDR1
85
80
75
-THD
70
SNR
65
60
60
55
SINAD
80
75
-THD
70
SNR
65
60
SFDR1
80
75
-THD
70
65
SNR
60
55
55
SINAD
50
0.35
0.55
0.75
0.95
1.15
1.35
COMMON-MODE VOLTAGE (V)
SFDR1
80
75
-THD
70
65
SNR
60
55
SINAD
50
1.70 1.75 1.80 1.85 1.90
ANALOG SUPPLY VOLTAGE (V)
1.95
2.3
44
42
40
38
36
34
49
48
47
46
45
44
43
42
41
30
40
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (MHz)
MAX19515 toc17
50
32
2.5
2.7
2.9
3.1
3.3
ANALOG SUPPLY VOLTAGE (V)
3.5
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT (mA)
46
SFDR2
85
SINAD
1.65
MAX19515 toc16
48
90
50
ANALOG SUPPLY CURRENT
vs. SAMPLING FREQUENCY
50
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGE
SFDR2
85
PERFORMANCE (dBFS)
SFDR2
85
90
MAX19515 toc13
SFDR1
90
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (Msps)
0
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGE
PERFORMANCE
vs. COMMON-MODE VOLTAGE
95
-70 -60 -50 -40 -30 -20 -10
ANALOG INPUT AMPLITUDE (dBFS)
MAX19515 toc15
-80
70
PERFORMANCE (dBFS)
60
50
49
ANALOG SUPPLY CURRENT (mA)
20
30
40
50
INPUT FREQUENCY (MHz)
MAX19515 toc14
10
SINAD
50
50
MAX19515 toc18
55
0
PERFORMANCE (dBFS)
SFDR2
90
60
50
ANALOG SUPPLY CURRENT (mA)
SINAD
SNR
95
PERFORMANCE (dBFS)
SFDR2
75
110
MAX19515 toc11
90
MAX19515 toc10
SINGLE-ENDED PERFORMANCE (dBFS)
95
PERFORMANCE
vs. SAMPLING FREQUENCY
PERFORMANCE
vs. ANALOG INPUT AMPLITUDE
MAX19515 toc12
SINGLE-ENDED PERFORMANCE
vs. INPUT FREQUENCY
48
47
46
45
44
43
42
41
40
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
1.65
1.70
1.75 1.80 1.85
SUPPLY VOLTAGE (V)
1.90
_______________________________________________________________________________________
1.95
9
NBY2:626
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
47
46
45
44
43
42
10
8
6
4
2
25
MAX19515 toc21
VOVDD = 1.8V
VOVDD = 3.6V
DIGITAL SUPPLY CURRENT (mA)
48
12
MAX19515 toc20
49
DIGITAL SUPPLY CURRENT (mA)
MAX19515 toc19
50
ANALOG SUPPLY CURRENT (mA)
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
20
15
10
5
41
0
2.7
2.9
3.1
SUPPLY VOLTAGE (V)
3.3
3.5
0
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (Msps)
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
23
SUPPLY CURRENT (mA)
21
19
VOVDD = 3.6V
17
15
VOVDD = 1.8V
13
11
9
25
DUAL BUS
DIGITAL SUPPLY CURRENT (mA)
MAX19515 toc22
25
20
15
10
5
30
MAX19515 toc24
2.5
MAX19515 toc23
2.3
MULTIPLEXED BUS
DIGITAL SUPPLY CURRENT (mA)
40
25
20
15
10
5
7
5
0
0
60
80
PERFORMANCE
vs. CLOCK DUTY CYCLE
PERFORMANCE vs. TEMPERATURE
SFDR1
SFDR2
-THD
70
SNR
65
SFDR1
90
85
PERFORMANCE (dBFS)
80
75
95
MAX19515 toc25
90
85
80
SFDR2
-THD
75
70
SNR
65
60
SINAD
10
40
45
50
55
CLOCK DUTY CYCLE (%)
60
65
0.03
0.02
0.01
0
-0.01
-0.04
SINAD
50
35
0.04
-0.03
55
55
GAIN ERROR vs. TEMPERATURE
0.05
-0.02
60
30
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
SUPPLY VOLTAGE (V)
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
SUPPLY VOLTAGE (V)
MAX19515 toc27
0
20
40
TEMPERATURE (°C)
GAIN ERROR (%)
-20
MAX19515 toc26
-40
PERFORMANCE (dBFS)
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
-0.05
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
-40
-20
0
20
40
TEMPERATURE (°C)
______________________________________________________________________________________
60
80
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
REFERENCE VOLTAGE
vs. TEMPERATURE
REFERENCE VOLTAGE (V)
-0.1
-0.2
-0.3
-0.4
-0.5
1.2495
1.2474
1.2453
-0.6
-0.7
60
80
VCM = 1.2V
1.2
VCM = 1.05V
1.0
VCM = 0.9V
0.8
VCM = 0.75V
VCM = 0.6V
0.6
VCM = 0.45V
0.4
0.2
-40
-20
0
20
40
TEMPERATURE (°C)
60
MAX19515 toc31
0.06
80
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
INPUT CURRENT
vs. COMMON-MODE VOLTAGE
GAIN ERROR vs. SUPPLY VOLTAGE
0.08
60
55
0.02
0
-0.02
REGULATOR MODE
INPUT CURRENT (μA)
0.04
50
45
40
35
-0.04
30
-0.06
25
-0.08
MAX19515 toc32
0
20
40
TEMPERATURE (°C)
GAIN ERROR (%)
-20
VCM = 1.35V
1.4
0
1.2432
-40
1.6
MAX19515 toc30
0
MAX19515 toc29
0.1
OFFSET ERROR (mV)
1.2516
MAX19515 toc28
0.2
COMMON-MODE REFERENCE VOLTAGE
vs. TEMPERATURE
COMMON-MODE REFERENCE VOLTAGE (V)
OFFSET ERROR vs. TEMPERATURE
20
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
COMMON-MODE VOLTAGE (V)
______________________________________________________________________________________
11
NBY2:626
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
``````````````````````````````````````````````````````````````````````````` ୭ႁී
୭
߂
1, 12, 13, 48
AVDD
ෝผ࢟Ꮞ࢟ኹăಽ1/2μG࢟ྏඛৈBWEEၒྜྷ࣪)2Ă59*ਜ਼)23Ă24*വᒗHOEă
2
CMA
ᄰࡸBࡼৢෝၒྜྷ࢟ኹᓰă
3
INA+
ᄰࡸBࡼෝผၒྜྷᑵ࣡ă
4
INA-
ᄰࡸBࡼෝผၒྜྷঌ࣡ă
5
SPEN
ࢅ࢟ຳᎌTQJဧถăདࣅᆐ࢟ຳဟLjဧถ݀ా߈ܠෝါă
6
REFIO
ᓰၒྜྷ0ၒ߲ăဧดݝᓰဟLjᄰਭጙৈࡍ᎖1/2μGࡼ࢟ྏവᒗHOEăਈ᎖ᅪݝᓰࢯᑳࡼ
ቧᇦLj༿ݬఠᓰၒྜྷ0ၒ߲)SFGJP*ݝॊă
7
SHDN
࢟ຳᎌਈ఼ࣥᒜăྙਫSPENᆐ࢟ຳ)݀ా߈ܠෝါ*LjᐌᏴTIEOࡼሆଢ଼ዘࣅࡀআᆡă
8
I.C.
9
INB+
ᄰࡸCࡼෝผၒྜྷᑵ࣡ă
10
INB-
ᄰࡸCࡼෝผၒྜྷঌ࣡ă
11
CMB
ᄰࡸCࡼৢෝၒྜྷ࢟ኹᓰă
14
SYNC
ဟᒩॊຫෝါᄴݛၒྜྷă
15
CLK+
ဟᒩၒྜྷᑵ࣡ă
16
CLK-
ဟᒩၒྜྷঌ࣡ăྙਫDML.LjDML,ᐌᆐ࣡൝࢟ຳဟᒩၒྜྷǗ॥ᐌLjDML,0DML.ᆐᔈມᒙތॊ
ဟᒩၒྜྷă
12
ถ
ดݝጯೌLjೌݙă
17, 18
GND
19
DORB
LjჅᎌၒྜྷਜ਼FQ! )ൡ*ೌᏴጙă
ᄰࡸCၫިሢă
20
DCLKB
ᄰࡸCၫဟᒩă
21
D0B
ᄰࡸCࡼྯზၫᔊၒ߲Lj1ᆡ)MTC*ă
22
D1B
ᄰࡸCࡼྯზၫᔊၒ߲Lj2ᆡă
23
D2B
ᄰࡸCࡼྯზၫᔊၒ߲Lj3ᆡă
24
D3B
ᄰࡸCࡼྯზၫᔊၒ߲Lj4ᆡă
25, 36
OVDD
26
D4B
ᄰࡸCࡼྯზၫᔊၒ߲Lj5ᆡă
27
D5B
ᄰࡸCࡼྯზၫᔊၒ߲Lj6ᆡă
28
D6B
ᄰࡸCࡼྯზၫᔊၒ߲Lj7ᆡă
29
D7B
ᄰࡸCࡼྯზၫᔊၒ߲Lj8ᆡă
30
D8B
ᄰࡸCࡼྯზၫᔊၒ߲Lj9ᆡă
31
D9B
ᄰࡸCࡼྯზၫᔊၒ߲Lj:ᆡ)NTC*ă
32
D0A
ᄰࡸBࡼྯზၫᔊၒ߲Lj1ᆡ)MTC*ă
33
D1A
ᄰࡸBࡼྯზၫᔊၒ߲Lj2ᆡă
34
D2A
ᄰࡸBࡼྯზၫᔊၒ߲Lj3ᆡă
35
D3A
ᄰࡸBࡼྯზၫᔊၒ߲Lj4ᆡă
37
D4A
ᄰࡸBࡼྯზၫᔊၒ߲Lj5ᆡă
38
D5A
ᄰࡸBࡼྯზၫᔊၒ߲Lj6ᆡă
39
D6A
ᄰࡸBࡼྯზၫᔊၒ߲Lj7ᆡă
ၫᔊ࢟Ꮞ࢟ኹLjᄰਭ1/2μG࢟ྏඛৈPWEEၒྜྷവᒗHOEă
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
୭
߂
ถ
40
D7A
ᄰࡸBࡼྯზၫᔊၒ߲Lj8ᆡă
41
D8A
ᄰࡸBࡼྯზၫᔊၒ߲Lj9ᆡă
42
D9A
ᄰࡸBࡼྯზၫᔊၒ߲Lj:ᆡ)NTC*ă
43
DORA
ᄰࡸBၫިሢă
44
DCLKA
ᄰࡸBၫဟᒩă
45
SDIN/FORMAT
46
SCLK/DIV
47
CS/OUTSEL
—
EP
TQJၫၒྜྷ0ৃါăࡩSPENᆐࢅ࢟ຳဟLjᆐࠈቲၫၒྜྷǗࡩSPENᆐ࢟ຳဟLjᒙၒ߲ၫৃါă
ࠈቲဟᒩ0ဟᒩॊຫăࡩSPENᆐࢅ࢟ຳဟLjᆐࠈቲဟᒩǗࡩSPENᆐ࢟ຳဟLjᔫဟᒩॊຫၒྜྷă
ࠈాኡᐋ0ၫၒ߲ෝါăࡩSPENᆐࢅ࢟ຳဟLjᆐࠈాኡᐋǗࡩSPENᆐ࢟ຳဟLjኡᐋၫၒ߲ෝါă
ൡăดೌݝᒗHOELjೌࡵࡍෂ૩ށLjጲᄋᔢଛྲེă
``````````````````````````````` ሮᇼႁී
NBY2:626ݧ೫21ĂཝތॊĂഗၺሣஉ৩)ᅄ2*Ljถ৫
ᏴဣሚႥᓞધࡼᄴဟଢ଼ᒗᔢࢅăၒྜྷݧዹږᑍ
ඛۍৈဟᒩᒲ໐ᓆᄰਭഗၺሣLjၒྜྷࡵၒ߲ࡼᔐዓဟ
ᆐ:ৈဟᒩᒲ໐ăഗၺሣᓞધࡼඛጙၒྜྷ࢟ኹᓞ
ધ߅ၫᔊၒ߲ܠ൩ă߹ᔢઁጙᅪLjඛၒྜྷ࢟ኹਜ਼ၫᔊ
ၒ߲ܠ൩ᒄମࡼᇙۻތहࡍ݀႙ᒗሆጙăၫᔊᇙތኀᑵ
᎖ޡݗඛBED୷܈ࡼມތLj݀ཀྵۣࣀݙ൩ăᅄ3Ⴥ
ာᆐNBY2:626ࡼถౖᅄă
+
MAX19515
Σ
x2
−
FLASH
ADC
DAC
IN_+
STAGE 1
STAGE 2
STAGE 9
IN_-
STAGE 10
END OF PIPELINE
DIGITAL ERROR CORRECTION
ෝผၒྜྷਜ਼ৢෝᓰ
ෝผၒྜྷቧᔫࡵෝผၒྜྷ)JOB,0JOB.JOC,0JOC.*࣡Lj
ೌۻᒗၒྜྷݧዹఎਈ)ᅄ4*LjࡩၒྜྷݧዹఎਈܕဟLj
ၒྜྷቧᄰਭၒྜྷఎਈࡴᄰ࢟ᔜᔫࡵནዹ࢟ྏăၒྜྷ
ఎਈࡌఎၾମ࣪ၒྜྷቧቲݧዹăഗၺሣBED࣪ݧዹ
࢟ኹቲࠀಯLj݀Ᏼ:ৈဟᒩᒲ໐ઁᄋၫᔊၒ߲உਫă
Ᏼၒྜྷఎਈܕఎဪሆጙࠨݧዹᒄ༄Ljݧዹ࢟ྏۻআᆡ
ࡵၒྜྷৢෝ࢟ኹă
ৢෝມᒙభᎅᅪݝᄋᑗᄰਭ3lΩ࢟ᔜᎅดݝᄋăᒇ
ഗẮ።ᒦLjቧᏎ와ݝມኹਜ਼ມഗǗୣഗẮ
።ᒦLjၒྜྷ࢟ഗᎅৢෝၒྜྷ࢟ኹᄋăಿྙLjၒྜྷ࢟
ഗభᄰਭܤኹࠨླྀᔝࡼᒦቦߥᄿᄋăᑗᄰਭࠈ
D0_ THROUGH D9_
ᅄ2/! ഗၺሣஉ৩—ॊౖᅄ
ాᒙሤ።ࡼดݝࡀLjᎅดݝ3lΩ࢟ᔜᄋၒྜྷᒇഗ
࢟ഗ)ᅄ4*ăᎅด࢟ݝᔜᄋၒྜྷ࢟ഗဟLj࢟ᔜࡼኹଢ଼
્ଢ଼ࢅၒྜྷৢෝ࢟ኹăৢෝၒྜྷᓰ࢟ኹᄰਭభ߈ܠ
ࡀᒙᏴ1/56Wᒗ2/46WपᆍดLjጲ1/26Wᆐޠݛቲ
ᒙLj෦ཱྀᒙᆐ1/:1Wă።কถᆐᒇഗẮདࣅ࢟
വᄋৢෝၒ߲ᓰă
______________________________________________________________________________________
13
NBY2:626
```````````````````````````````````````````````````````````````````````````` ୭ႁී)ኚ*
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
CLOCK
MAX19515
INA+
T/H
INA-
PIPELINE
ADC
DIGITAL
ERROR
CORRECTION
D0A–D9A
DORA
DCLKA
CMA
REFIO
CMB
REFERENCE
AND BIAS
SYSTEM
INTERNAL
REFERENCE
GENERATOR
PIPELINE
ADC
DIGITAL
ERROR
CORRECTION
DATA
AND
OUTPUT
FORMAT
OUTPUT
DRIVERS
OVDD
(1.8V TO 3.3V)
D0B–D9B
INB+
T/H
INB-
DORB
DCLKB
CLOCK
CLK+
CLOCK
DIVIDER
CLK-
DUTYCYCLE
EQUALIZER
SYNC
AVDD
(1.8V OR
2.5V TO 3.3V)
REGULATOR
AND
POWER CONTROL
1.8V INTERNAL
CS
SERIAL PORT
AND
CONTROL REGISTERS
SCLK
SDIN
SHDN
INTERNAL CONTROL
GND
SPEN
ᅄ3/! ถౖᅄ
AVDD
CMA
RSWITCH
120Ω
INA+
CSAMPLE
1.2pF
CPAR
0.7pF
2kΩ
*VCOM
AVDD
2kΩ
RSWITCH
120Ω
INACPAR
0.7pF
CSAMPLE
1.2pF
SAMPLING CLOCK
MAX19515
*VCOM PROGRAMMABLE FROM 0.45V TO 1.35V. SEE COMMON-MODE REGISTER (08h)
ᅄ4/! ดݧݝዹۣߒ)U0I*࢟വ
14
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
INTERNAL GAIN—BYPASS REFIO
EXTERNAL GAIN CONTROL—DRIVE REFIO
36kΩ
REFIO
1.250V
BANDGAP
REFERENCE
10kΩ
BUFFER
DECODER
0.1μF
EXTERNAL BYPASS
CS
SCLK
SDIN
23/32 AVDD
TO
CONTROL
LOGIC
156kΩ
SCALE AND
INTERNAL REFERENCE
LEVEL SHIFT
(CONTROLS ADC GAIN)
3/32 AVDD
ᅄ5/! ଼છࡼᓰᏇಯᅄ
ᅄ6/! ଼છࡼ݀ాၒྜྷᏇಯᅄ
ܭ2/! ݀ా୭ถ
SPEN
SDIN/FORMAT
SCLK/DIV
CS/OUTSEL
DESCRIPTION
0
SDIN
SCLK
CS
SPI interface active. Features are programmed through the
serial port (see the Serial Programming Interface section).
1
0
X
X
Two’s complement
1
AVDD
X
X
Offset binary
1
Unconnected
X
X
Gray code
1
X
0
X
Clock divide-by-1
1
X
AVDD
X
Clock divide-by-2
1
X
Unconnected
X
Clock divide-by-4
1
X
X
0
CMOS (dual bus)
1
X
X
AVDD
MUX CMOS (channel A data bus)
1
X
X
Unconnected
MUX CMOS (channel B data bus)
Y! >! ᇄਈă
ᓰၒྜྷ0ၒ߲)SFGJP*
SFGJPࢯஂᓰ࢟ኹLj࠭ऎࢯᑳBEDࡼ൸߈पᆍăᅄ5ᆐ
଼છࡼᓰᏇಯᅄăดࡒݝᇺ࢟ኹᓰᏎᄋดݝᓰ࢟
ኹăࡒᇺ࢟ኹளਭદߡ݀ᄰਭጙৈ21lΩ࢟ᔜᔫࡵSFGJPă
ಽጙৈ1/2μG࢟ྏSFGJPവᒗHOEăࡒᇺ࢟ኹၒྜྷࡵ
ጙৈ܈ಿࢯஂਜ਼࢟ຳᓞધ࢟വLjᎅক࢟വޘညཀྵࢾBED൸
߈पᆍࡼดݝᓰ࢟ኹăᔫᏴSFGJP࣡ࡼᅪ࢟ݝኹభ
ጲࢯஂBED൸߈पᆍLjᏤࢯᑳपᆍᆐ,60.26&ăSFGJP
ᒗBEDࡼᐐፄࠅၒၫᆐǖ
WGT >! 2/6! y! \WSFGJP02/36^! ॰ᄂ
߈ܠਜ਼ా
భᄰਭೝᒬऱज఼ᒜNBY2:626ࡼᔫෝါăಽTQJా
భጲ఼ᒜჅᎌถኡሲLjಽ݀ాᐌభ఼ᒜᎌሢࡼጙᔝޟ
ถă߈ܠෝါᄰਭSPENၒྜྷኡᐋLjSPENདࣅᆐࢅ
࢟ຳဟኡᐋTQJాǗSPENདࣅᆐ࢟ຳဟኡᐋ݀ాă
݀ా
݀ాᄋ೫ጙৈ୭ా߈ܠLjถ৫ᒙᎌሢࡼଂᒬถă
SPENೌᒗBWEELjဧถ݀ాăਈ᎖୭ถ༿ݬఠ
ܭ2Lj଼છࡼ݀ాၒྜྷᏇಯᅄ༿ݬఠᅄ6ă
______________________________________________________________________________________
15
NBY2:626
29/32 AVDD
AVDD
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
CS
SCLK
SDIN
R/W
A6
A5
A4
A3
A2
A1
D7
D6
D5
D4
D3
D2
D1
D0
DATA
WRITE OR READ
ADDRESS
R/W
A0
0 = WRITE
1 = READ
ᅄ7/! ࠈాᄰቧᒲ໐
tCSH
tCSS
CS
tSCLK
SCLK
tSDS
tSDH
tSDD
SDIN
WRITE
READ
ᅄ8/! ࠈాဟኔᅄ
ࠈቲా߈ܠ
ࠈాᄰਭCSĂTEJOਜ਼TDMLၒྜྷ࣪NBY2:626ࡼ఼ᒜࡀ
ቲ߈ܠăࡩCSᆐࢅ࢟ຳဟLjᏴTDMLࡼဍዘLjࠈቲ
ၫۻᓆᆡጤྜྷTEJOǗࡩCSᆐ࢟ຳဟLjNBY2:626
TEJOਜ਼TDMLࡼၫăᏴඛࠨࣗ0ቖݷᔫઁLjDT࣒ܘኍᏘ
ࡵܤ࢟ຳăTEJOጐభᔫᆐࣗན఼ᒜࡀࡼࠈቲၫ
ၒ߲ăࠈాᑽߒᏴጙৈᄰቧᒲ໐ดࡼၷᔊஂࠅၒăጙৈ
ᔊஂᆐ఼ᒜᔊஂLj۞౪ᒍਜ਼ࣗ0ቖᒎഎLjቖྜྷNBY2:626 <
औৈᔊஂᆐၫᔊஂLjቖྜྷNBY2:626࠭NBY2:626
߲ࣗă
16
ᅄ7Ⴥာᆐࠈాᄰቧᒲ໐ăጙৈTEJOᆡཀྵࢾকᄰቧᒲ໐
ቲቖݷᔫࣗݷᔫ)1ࡔܭቖݷᔫǗ2ࡔݷࣗܭᔫ*ăႲઁ
8ᆡᒎࢾገቖྜྷࣗནࡼࡀᒍăᔢઁ9ৈTEJOᆡ
ᆐࡀၫăჅᎌᒍਜ਼ၫᆡᏴቖྜྷਜ਼ࣗནဟᆐ
NTCᏴ༄ăࣗݷᔫ໐ମLjNBY2:626ࠈాᏴTDML9ৈ
ဍዘᒄઁࡼሆଢ଼ዘገࣗནၫ)E8*႙ᒗTEJOăᎅ᎖TEJO
ၒྜྷࡼᔢቃۣߒဟମᆐഃLjჅጲᓍ఼۸ᏴTDMLࡼ9ৈ
ဍዘઁభႲဟᄫᒏTEJOདࣅăႲઁࡼၫᆡᏴTDMLࡼ
ሆଢ଼ዘ႙ᒗTEJOăࣗݷᔫࡼၒ߲ၫᏴTDMLࡼဍዘۻ
ჄࢾLjᅄ8߲೫ሮᇼࡼࠈాဟኔᅄă
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ᒜࡀۻআᆡࡵ෦ཱྀᒋă࣪ࡀ1Biࡼࣗݷᔫऩૄᓨ
ზᔊஂLjᄏፃ༿ݬఠܭ3Ⴥာࡼቧᇦႁීă
ܭ3/! ࡀ1Biࡼᓨზᔊஂ
BIT NO.
VALUE
DESCRIPTION
7
0
6
0
5
0 or 1
1 = ROM read in progress
4
0 or 1
1 = ROM read completed and register data is valid (checksum is OK)
3
0
2
1
Reserved
1
0 or 1
Reserved
0
0 or 1
1 = Duty-cycle equalizer DLL is locked
Reserved
Reserved
Reserved
ઓ߈ܠࡀ
ܭ4/! ઓ߈ܠࡀ
ADDRESS
POR DEFAULT
FUNCTION
00h
00000011
Power management
01h
00000000
Output format
02h
00000000
Digital output power management
03h
10000000
Data/DCLK timing
04h
00000000
CHA data output termination control
05h
00000000
CHB data output termination control
06h
00000000
Clock divide/data format/test pattern
07h
Reserved
Reserved—do not use
08h
00000000
Common mode
0Ah
—
Software reset
࢟Ꮞಯ)11i*
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HPS_SHDN1 STBY_SHDN1 CHB_ON_SHDN1 CHA_ON_SHDN1 HPS_SHDN0 STBY_SHDN0 CHB_ON_SHDN0 CHA_ON_SHDN0
TIEOၒྜྷ)୭8*᎖఼ᒜྀፀೝৈ࢟Ꮞಯᓨზᒄମࡼ
ᓞધă࢟Ꮞಯࡀࢾፃ೫ඛৈ࢟Ꮞಯᓨზă෦ཱྀᓨ
ზሆLjTIEO > 2ဟਈࣥNBY2:626ǗTIEO > 1ဟऩૄࡵᅲ
ཝᔫᓨზă
______________________________________________________________________________________
17
NBY2:626
ᒍᆐ1Biࡼࡀᆐᄂၐถࡀăၫ6Biቖྜྷ
ࡀ1BiLjᐌࣅࡀআᆡăᒊቲকݷᔫဟLjჅᎌ఼
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
߹೫࢟ᏎಯLjIQT`TIEO2ਜ਼IQT`TIEO1થభጲࣅB,C
ଝजෝါăকෝါሆLj࣪ೝৈᄰࡸࡼஉਫནຳăNVY`DI
ᆡኡᐋၒ߲)B,C*03ၫࡼᔐሣă
఼ᒜᆡǖ
HPS_SHDN0
STBY_SHDN0
CHA_ON_SHDN0
CHB_ON_SHDN0
SHDN INPUT = 0*
HPS_SHDN1
STBY_SHDN1
CHA_ON_SHDN1
CHB_ON_SHDN1
X
0
0
0
Complete power-down
0
0
0
1
Channel B active, channel A full power-down
0
0
1
0
Channel A active, channel B full power-down
0
X
1
1
Channels A and B active
0
1
0
0
Channels A and B in standby mode
0
1
0
1
Channel B active, channel A standby
0
1
1
0
Channel A active, channel B standby
1
1
0
0
Channels A and B in standby mode
1
X
X
1
Channels A and B active, output is averaged
1
X
1
X
Channels A and B active, output is averaged
SHDN INPUT = 1**
*ࡩTIEO! >! 1ဟLjIQT`TIEO1ĂTUCZ`TIEO1ĂDIB`PO`TIEO1ਜ਼DIC`PO`TIEO1ᎌă
**ࡩTIEO! >! 2ဟLjIQT`TIEO2ĂTUCZ`TIEO2ĂDIB`PO`TIEO2ਜ਼DIC`PO`TIEO2ᎌă
Y! >! ᇄਈă
ᓖǖࡩIQT`TIEO`! >! 2! )B,Cଝजෝါ*ဟLjDIB`PO`TIEO`ਜ਼DIC`PO`TIEO`ܘኍ࣒ࢀ᎖1ݣభྜྷਈࣥࡗ૦ᓨზă
ၒ߲ৃါ)12i*
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
BIT_ORDER_B
BIT_ORDER_A
MUX_CH
MUX
0
8Ă7Ă6ᆡ
ᒙ1Ljᑵޟᔫ
5ᆡ
CJU`PSEFS`CǖDICၒ߲ᆡၿኔनሶ
1! >! ږᑍࢾፃࡼၫᔐሣ୭ၿኔ)෦ཱྀ*
2! >! ၫᔐሣ୭ࡼၿኔनሶ
4ᆡ
CJU`PSEFS`BǖDIBၒ߲ᆡၿኔनሶ
1! >! ږᑍࢾፃࡼၫᔐሣ୭ၿኔ)෦ཱྀ*
2! >! ၫᔐሣ୭ࡼၿኔनሶ
3ᆡ
NVY`DIǖআၫᔐሣኡᐋ
1! >! ᏴDIBআၫၒ߲)၅ሌၒ߲DIBၫLjႲઁၒ߲DICၫ*! )෦ཱྀ*
2! >! ᏴDICআၫၒ߲)၅ሌၒ߲DICၫLjႲઁၒ߲DIBၫ*
2ᆡ
NVYǖၫᔊၒ߲ෝါ
1! >! ၷവၫᔐሣၒ߲ෝါ)෦ཱྀ*
2! >! വআၫᔐሣၒ߲ෝါ
NVY`DIኡᐋၒ߲ᔐሣ
1ᆡ
18
ᒙ1Ljᑵޟᔫ
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
X
PD_DOUT_1
PD_DOUT_0
DIS_DOR
DIS_DCLK
8–5ᆡ
ᇄਈሲ
4Ă3ᆡ
QE`EPVU`2ĂQE`EPVU`1ǖਈࣥၫᔊၒ߲ᓨზ఼ᒜ
11! >! ၫᔊၒ߲ᆐྯზ)෦ཱྀ*
12! >! ၫᔊၒ߲ᆐࢅ࢟ຳ
21! >! ၫᔊၒ߲ᆐྯზ
22! >! ၫᔊၒ߲ᆐ࢟ຳ
2ᆡ
EJT`EPSǖEPSདࣅண
1! >! EPSᎌ)෦ཱྀ*
2! >! EPSண)ྯზ*
1ᆡ
EJT`EDMLǖEDMLདࣅண
1! >! EDMLᎌ)෦ཱྀ*
2! >! EDMLண)ྯზ*
______________________________________________________________________________________
19
NBY2:626
ၫᔊၒ߲࢟Ꮞಯ)13i*
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ၫ0EDMLဟኔ)14i*
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DA_BYPASS
DLY_HALF_T
DCLKTIME_2
DCLKTIME_1
DCLKTIME_0
DTIME_2
DTIME_1
DTIME_0
8ᆡ
EB`CZQBTTǖၫ࣪ᓰവ
1! >! ܪᓰᔫෝါ
2! >! വၫ࣪ᓰዓߕሣLjሤ࣪᎖ၒྜྷဟᒩࡼၒ߲ၫዓߕᔢቃ
ᒙEUJNF! >! 111cဟLj࠭ဟᒩဍዘࡵၫᓞધࡼဟମࡍᏖᆐ7ot! )෦ཱྀ*
7ᆡ
EMZ`IBMG`Uǖၫਜ਼EDMLዓߕU03
1! >! ܪᓰᔫෝါLjᇄዓߕ)෦ཱྀ*
2! >! ၫਜ਼EDMLၒ߲ዓߕU03!
ᏴNVYၫᔐሣෝါሆண
6Ă5Ă4ᆡ
EDMLUJNF`3ĂEDMLUJNF`2ĂEDMLUJNF`1ǖEDMLဟኔࢯᑳ)఼ᒜೝৈᄰࡸ*
111! >! ܪᓰᔫෝါ)෦ཱྀ*
112! >! ,U027
121! >! ,3U027
122! >! ,4U027
211! >! ۣഔLjᎌဧ
212! >! .2U027
221! >! .3U027
222! >! .4U027
3Ă2Ă1ᆡ
EUJNF`3ĂEUJNF`2ĂEUJNF`1ǖၫဟኔࢯᑳ)఼ᒜೝৈᄰࡸ*
111! >! ܪᓰᔫෝါ)෦ཱྀ*
112! >! ,U027
121! >! ,3U027
122! >! ,4U027
211! >! ۣഔLjᎌဧ
212! >! .2U027
221! >! .3U027
222! >! .4U027
20
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
CT_DCLK_2_A
CT_DCLK_1_A
CT_DCLK_0_A
CT_DATA_2_A
CT_DATA_1_A
CT_DATA_0_A
8Ă7ᆡ
ᇄਈሲ
6Ă5Ă4ᆡ
DU`EDML`3`BĂDU`EDML`2`BĂDU`EDML`1`BǖDIB! EDML఼࣡ᒜ
111! >! 61Ω )෦ཱྀ*
112! >! 86Ω
121! >! 211Ω
122! >! 261Ω
2yy! >! 411Ω
3Ă2Ă1ᆡ
DU`EBUB`3`BĂDU`EBUB`2`BĂDU`EBUB`1`BǖDIBၫၒ఼߲࣡ᒜ
111! >! 61Ω )෦ཱྀ*
112! >! 86Ω
121! >! 211Ω
122! >! 261Ω
2yy! >! 411Ω
DICၫၒ఼߲࣡ᒜ)16i*
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
CT_DCLK_2_B
CT_DCLK_1_B
CT_DCLK_0_B
CT_DATA_2_B
CT_DATA_1_B
CT_DATA_0_B
8Ă7ᆡ
ᇄਈሲ
6Ă5Ă4ᆡ
DU`EDML`3`CĂDU`EDML`2`CĂDU`EDML`1`CǖDIC! EDML఼࣡ᒜ
111! >! 61Ω )෦ཱྀ*
112! >! 86Ω
121! >! 211Ω
122! >! 261Ω
2yy! >! 411Ω
3Ă2Ă1ᆡ
DU`EBUB`3`CĂDU`EBUB`2`CĂDU`EBUB`1`CǖDICၫၒ఼߲࣡ᒜ
111! >! 61Ω )෦ཱྀ*
112! >! 86Ω
121! >! 211Ω
122! >! 261Ω
2yy! >! 411Ω
______________________________________________________________________________________
21
NBY2:626
DIBၫၒ఼߲࣡ᒜ)15i*
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ဟᒩॊຫ0ၫৃါ0ހ၂ෝ)ۇ17i*
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TEST_PATTERN
TEST_DATA
FORMAT_1
FORMAT_0
TERM_100
SYNC_MODE
DIV1
DIV0
8ᆡ
UFTU`QBUUFSOǖހ၂ෝۇኡᐋ
1! >! ࠭1ဍࡵ2134! )ມጤऔᒜ*݀ᒮআকਭ߈)ݧઁኚৃါ*! )෦ཱྀ*
2! >! Ᏼೝৈၫᄰࡸୣᄐၒ߲ǖE\:;1^! >! 1212121212ĂEPS! >! 2ਜ਼E\:;1^! >! 2121212121ĂEPS! >! 1
7ᆡ
UFTU`EBUBǖၫހ၂ෝါ
1! >! ܪᓰၫၒ߲)෦ཱྀ*
2! >! ၒ߲ހ၂ၫෝۇ
6Ă5ᆡ
GPSNBU`2ĂGPSNBU`1ǖၫᆡৃါ
11! >! औᒜݗ൩)෦ཱྀ*
12! >! ມጤऔᒜ
21! >! ৃಙ൩
22! >! औᒜݗ൩
4ᆡ
UFSN`211ǖኡᐋ211Ωဟᒩၒྜྷ࣡
1! >! ᇄ࣡)෦ཱྀ*
2! >! ތॊဟᒩၒྜྷో211Ω࣡
3ᆡ
TZOD`NPEFǖॊຫᄴݛෝါኡᐋ
1! >! ઘࣅෝါ)ᅄ22*! )෦ཱྀ*
2! >! ܟዘෝါ)ᅄ23*
2Ă1ᆡ
EJW2ĂEJW1ǖၒྜྷဟᒩॊຫኡᐋ
11! >! ᎌॊຫ)෦ཱྀ*
12! >! 3ॊຫ
21! >! 5ॊຫ
22! >! ᎌॊຫ
ۣഔ)18i*—༿ᇖቖྜྷকࡀ
22
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CMI_SELF_B
CMI_ADJ_2_B
CMI_ADJ_1_B
CMI_ADJ_0_B
CMI_SELF_A
CMI_ADJ_2_A
CMI_ADJ_1_A
CMI_ADJ_0_A
8ᆡ
DNJ`TFMG`CǖDICၒྜྷৢෝෝผၒྜྷ
1! >! ดৢݝෝ࢟ኹݙᔫࡵၒྜྷ࣡)෦ཱྀ*
2! >! ᄰਭ3lΩ࢟ᔜดৢݝෝ࢟ኹᔫࡵෝผၒྜྷ࣡
7Ă6Ă5ᆡ
DNJ`BEK`3`CĂDNJ`BEK`2`CĂDNJ`BEK`1`CǖDICၒྜྷৢෝ࢟ኹࢯᑳ
111! >! 1/:11W! )෦ཱྀ*
112! >! 2/161W
121! >! 2/311W
122! >! 2/461W
211! >! 1/:11W
212! >! 1/861W
221! >! 1/711W
222! >! 1/561W
4ᆡ
DNJ`TFMG`BǖDIBၒྜྷৢෝෝผၒྜྷ
1! >! ดৢݝෝ࢟ኹݙᔫࡵၒྜྷ࣡)෦ཱྀ*
2! >! ᄰਭ3lΩ࢟ᔜดৢݝෝ࢟ኹᔫࡵෝผၒྜྷ࣡
3Ă2Ă1ᆡ
DNJ`BEK`3`BĂDNJ`BEK`2`BĂDNJ`BEK`1`BǖDIBၒྜྷৢෝࢯᑳ
111! >! 1/:11W! )෦ཱྀ*
112! >! 2/161W
121! >! 2/311W
122! >! 2/461W
211! >! 1/:11W
212! >! 1/861W
221! >! 1/711W
222! >! 1/561W
ྟୈআᆡ)1Bi*
8–1ᆡ
TXSFTFUǖቖྜྷ6Biဟࣅྟୈআᆡ
______________________________________________________________________________________
23
NBY2:626
ৢෝ)19i*
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ဟᒩၒྜྷ
100Ω
TERMINATION
(PROGRAMMABLE)
CLK+
ၒྜྷဟᒩాᆐဟᒩॊຫࡼገཇᄋ೫ഉቶă
NBY2:626၊ཝތॊဟᒩ࣡൝࢟ຳဟᒩăᆐဣሚ
ތॊဟᒩᔫLj༿ތॊဟᒩೌᒗDML,ਜ਼DML.ၒྜྷă
ᏴকෝါሆLjดݝೂၒྜྷৢෝ࢟ኹጲᏤୣഗẮă
ྙਫৢෝ࢟ኹۻሢᒜᏴਖࢾࡼ2Wᒗ2/5Wဟᒩၒྜྷৢෝप
ᆍดLjᐌތॊဟᒩቧጐభጲݧᒇഗẮăᆐဣሚ
࣡ᔫLj༿DML.ೌᒗHOE݀༦൝࢟ຳቧདࣅ
DML,ၒྜྷăࡩDML.ၒྜྷ)ᑗۻሆ౯ᒗࢅ᎖ဟᒩෝ
ါଶ୷܈ހࡼඡሢ*ဟLjணތॊᒗ࣡ᓞધLj
൝࢟ຳनሤᄰവă
2:1 MUX
AVDD
5kΩ
50Ω
10kΩ
20kΩ
50Ω
SELECT
THRESHOLD
5kΩ
GND
CLK-
ဟᒩॊຫ
NBY2:626ᄋ೫ဟᒩॊຫኡሲăᄰਭࠈాᒙEJW1ਜ਼
EJW2ဧถဟᒩॊຫLjਈ᎖ဟᒩॊຫኡሲࡼሮᇼቧᇦLj
༿ݬఠဟᒩॊຫ0ၫৃါ0ހ၂ෝۇࡀ)17i*ăᑗᏴ
݀ా߈ܠᒙ)SPEN > 2*ᒦဧEJWၒྜྷဧถဟᒩॊຫă
SELF-BIAS TURNED OFF FOR
SINGLE-ENDED CLOCK
OR POWER-DOWN.
ᅄ9/! ଼છࡼဟᒩၒྜྷᏇಯᅄ
DUAL-BUS OUTPUT MODE
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
tAD
SAMPLING
INSTANT
SAMPLING
INSTANT
IN_
SAMPLING
INSTANT
tCLK
SAMPLE ON RISING EDGE
n
tCL
tCH
n+1
n+2
n+4
n+3
n+5
SAMPLE CLOCK
tDD
DATA, DOR
n-10
n-9
tDC
n-8
n-7
n-6
n-5
tHOLD
tSETUP
DCLK
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
ᅄ:/! ၷᔐሣၒ߲ෝါဟኔ
24
______________________________________________________________________________________
n-4
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
NBY2:626
MUX OUTPUT MODE
SAMPLING
INSTANT
tAD
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
IN_
tCLK
n
tCL
tCH
SAMPLE ON RISING EDGE
n+1
n+2
n+3
n+4
n+5
SAMPLE CLOCK
tCHA
tDD
DATA, DOR
tCHB
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
n-10
n-9
n-9
n-8
n-8
n-7
n-7
n-6
n-6
n-5
n-5
n-4
n-4
tDC
tHOLD
tDCH
tDCL
tSETUP
tHOLD
tSETUP
DCLK
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
MUX_CH (BIT 2, OUTPUT FORMAT 01h) DETERMINES THE OUTPUT BUS AND WHICH CHANNEL DATA IS PRESENTED.
ᅄ21/! আၒ߲ෝါဟኔ
ᇹᄻဟኔገཇ
ᅄ:ਜ਼ᅄ21ႁී೫ဟᒩၒྜྷਜ਼ၒ߲ĂෝผၒྜྷĂݧዹူୈ
ਜ਼ၫၒ߲ᒄମࡼਈᇹăNBY2:626Ᏼݧዹဟᒩࡼဍዘ
ቲݧዹăளਭ:ৈဟᒩࡼดݝዓߕઁLjᏴሆጙৈEDML
ࡼဍዘၒ߲ᎌၫăᏴဟᒩॊຫ።ᒦLjݧዹဟᒩ
ᆐॊຫઁࡼดݝဟᒩLjါྙሆǖ
[(CLK+ - CLK-)/DIVIDER]
ᄴݛ
ݧဟᒩॊຫဟLjดݝဟᒩࡼሤᆡభถᎧᇹᄻࡼGQHBĂ
ᆈ఼ᒜNBY2:626ࡼဟᒩݙᄴሤăᎌೝᒬऱါభ
ጲᄴݛดݝဟᒩǖઘࣅᄴݛਜ਼ܟዘᄴݛăဟᒩॊຫ0ၫ
ৃါ0ހ၂ෝۇࡀ)17i*ࡼTZOD`NPEF )3ᆡ*ኡᐋ
ᄴݛෝါ݀TZODၒྜྷདࣅᆐ࢟ຳቲᄴݛă
ઘࣅᄴݛෝါLjTZOD`NPEF > 1 )෦ཱྀ*ǖᏴTZODဍ
ዘ)ଣ൸ᔗೂਜ਼ۣߒဟମ*ᒄઁࡼ4ৈၒྜྷဟᒩ)DML*
ࡼဍዘLj༓ᒜॊຫၒ߲ᄢਭጙࠨᓨზᏘ)ܤᅄ22*ă
ܟዘᄴݛෝါLjTZOD`NPEF > 2ǖᏴTZODဍዘ)ଣ
൸ᔗೂਜ਼ۣߒဟମ*ᒄઁࡼ4ৈၒྜྷဟᒩ)DML*ࡼ
ဍዘLjॊຫၒ߲ۻ༓ᒜᆐᓨზ1ăጙৈTZODࡼᎌ
ဍዘઁLjॊຫဟᒩဍዘ߲ሚᏴDMLࡼ5ৈ)03ෝါ*
6ৈ)05ෝါ*ဍዘ)ᅄ23*ă
______________________________________________________________________________________
25
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
tHO
DIVIDE-BY-2 SLIP SYNCRONIZATION
tSUV
tSUV = SET-UP TIME FOR VALID CLOCK EDGE.
tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
SYNC
1
2
3
4
2x INPUT CLK
SLIP
(0)
(1)
(0)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
1x DIVIDED CLK
(STATE)
tHO
tSUV
DIVIDE-BY-4 SLIP SYNCHRONIZATION
SYNC
1
2
3
4
5
4x INPUT CLK
SLIP
(0)
(1)
(2)
(3)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(1)
(2)
(3)
(0)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(2)
(3)
(0)
(1)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(3)
(0)
(1)
(2)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
1x DIVIDED CLK
(STATE)
ᅄ22/! ઘࣅᄴݛෝါ
26
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
NBY2:626
tHO
DIVIDE-BY-2 EDGE SYNCRONIZATION
tSUV
tSUV = SET-UP TIME FOR VALID CLOCK EDGE.
tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
SYNC
1
2
3
4
2x INPUT CLK
FORCE TO 0
(0)
(1)
(0)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
1x DIVIDED CLK
(STATE)
tHO
tSUV
DIVIDE-BY-4 EDGE SYNCHRONIZATION
SYNC
1
2
3
4
5
4x INPUT CLK
FORCE TO 0
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(1)
(2)
(3)
(0)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(3)
(0)
(1)
(2)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
1x DIVIDED CLK
(STATE)
ᅄ23/! ܟዘᄴݛෝါ
______________________________________________________________________________________
27
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ܭ5/! ၫဟኔ఼ᒜ
DATA TIMING CONTROL
DESCRIPTION
DA_BYPASS
Data aligner bypass. When this control is active (high), data and DCLK delay is reduced by
approximately 3.4ns (relative to DA_BYPASS = 0).
DLY_HALF_T
When this control is active, data output is delayed by half clock period (T/2). This control does not
delay data output if MUX mode is active.
DTIME<2:0>
Allows adjustment of data output delay in T/16 increments, where T is the sample clock period.
Provides adjustment of DCLK delay in T/16 increments, where T is the sample clock period. When
DTIME and DCLKTIME are adjusted to the same setting, the rising edge of DCLK occurs T/8 prior
to data transitions.
DCLKTIME<2:0>
ܭ6/! ၫဟኔ఼ᒜ෦ཱྀᒙ
DATA TIMING
CONTROL
DEFAULT
DA_BYPASS
1
Data aligner disabled
DLY_HALF_T
0
No delay
DTIME<2:0>
000
No delay
DCLKTIME<2:0>
000
No delay
DESCRIPTION
ਜ਼EMZ`IBMG`Uࡼ25ᒬభᓨზࡼ߂ܪၫဟኔLj࠰ሣࡔ
ܭ෦ཱྀᒙሆࡼၫဟኔă༿ᓖፀNBY2:626! 76Ntqt! BED
ࡼ෦ཱྀဟኔࢯᑳ્ޘညৎࣶࡼၫዓߕᒲ໐ă
ܭ7ਜ਼ܭ8߲೫ݙᄴݧዹൈሆࡼᅎୀဟኔᒙă
ᑚቋᅎୀဟኔᒙሆࡼ߂ܪၫဟኔᄂቶᎧݧዹൈࡼਈᇹ
ྙᅄ26ਜ਼ᅄ27Ⴥာă
ࡩEB`CZQBTT > 2ဟLjEDMLUJNFዓߕᒙܘኍࢀ᎖ࢅ
᎖EUJNFࡼዓߕᒙLjྙܭ9Ⴥာă
ၫᔊၒ߲
NBY2:626ᎌጙৈၷDNPTĂభআࡼభภၫᔐሣă
Ᏼ݀ా߈ܠෝါሆLjಽGPSNBUၒྜྷᒙມጤऔᒜĂ
औᒜݗ൩ৃಙ൩ၫၒ߲)E1`–E:`*ăPVUTFMၒ
ྜྷኡᐋআၷᔐሣᔫăਈ᎖ಽTQJాᒙၒ߲ৃ
ါࡼৎࣶቧᇦLj༿ݬఠၒ߲ৃါࡀ)12i*ăTQJాᄋ
ৎࣶഉቶLjᒦE1`–E:`ᆡࡼၿኔۻनሶLjჅጲMTC
߲ሚᏴE:`ᆡᒙLjऎNTC߲ሚᏴE1`ᆡᒙăPWEEᒙၒ
߲࢟ኹLjభᏴ2/9Wᒗ4/4WᒄମᒙPWEEăၫᔊၒ߲࣡ࡼ
ၒ߲࢟ᔜభᏴ61Ωᒗ411ΩᒄମᒙăಽDI`ၫၒ߲࣡
఼ᒜࡀ)15iਜ਼16i*ᒙඛৈᔐሣࡼၒ߲࢟ᔜă
భ߈ܠၫဟኔ
NBY2:626ᄋభ߈ܠၫဟኔ఼ᒜLj࣪ဟኔቲᎁછLj
࠭ऎ൸ᔗᇹᄻဟኔࡼገཇăဟኔࢯᑳถથభᄰਭܜݧ
ዹၾମࡼၫၒ߲ᏘܤᄋဍBEDቶถăਈ᎖ၫဟኔ
఼ᒜቧࡼLj༿ݬఠܭ5ăܭ6߲೫ဟኔࢯᑳ఼ᒜࡼ
෦ཱྀᒙLjࣶ።࣒ݙኊገኀখ෦ཱྀᒙă
࢟Ꮞಯ
TIEOၒྜྷ)୭8*᎖఼ᒜྀፀೝৈ࢟Ꮞಯᓨზᒄମࡼ
༤ધă࢟Ꮞಯࡀ)11i*ࢾፃ೫ඛᒬ࢟Ꮞಯࡼᓨზă
෦ཱྀᓨზሆLjTIEO > 2ဟਈࣥNBY2:626LjTIEO > 1ဟऩ
ૄᅲཝᔫෝါă࢟Ꮞಯถ݀ݙገཇጙࢾဧTIEO
ၒྜྷăᇄ൙TIEOࠀ᎖ੜᒬᓨზLjୈభ유۸ࡼ࢟
ᏎಯഉቶLjᒦ۞౪ᄰਭ࢟Ꮞಯࡀ)11i*ဣሚ
ࣖೂࡼBEDᄰࡸ࢟Ꮞಯ఼ᒜăୈᄋਈࣥਜ਼ࡗ૦ೝ
ᒬࢅෝါăࡗ૦ෝါሆLjᓰਜ਼ᐴహ܈ੰ࢟വۣ
ߒᎌᔫᓨზLjۣᑺႥታୈăࡗ૦ෝါሆLjᅪ
ݝဗଝࡼဟᒩቧܘኍۣߒᎌLjጲۣᑺᐴహ܈ੰ
ۣߒჄࢾă࠭ࡗ૦ෝါታࡼ࢜ቯဟମᆐ26μtăਈࣥෝ
ါሆLj߹೫ૹ߅ᔈଶ࢟ހኹࢯஂჅገཇࡼᓰ࢟വᅪLj
Ⴥᎌ࢟വ࣒ਈܕăࡩୈࠀ᎖ਈࣥᓨზဟLjྙਫᆮኹ
ࠀ᎖ᎌᓨზLj્ሿऄᅪࡼᎧࢯஂ࢟വሤਈࡼ࢟Ꮞ
࢟ഗă࠭ਈࣥෝါታࡼ࢜ቯဟମᆐ 6ntLjᓍገན᎖
SFGJPࡼSDဟମޟၫă
ၫဟኔࢯᑳᒙࡼ፬ሰ༿ݬఠᅄ24ਜ਼ᅄ25ăyᒷᆐݧዹ
ൈLjzᒷᆐጲဟᒩᒲ໐ᆐᆡࡼၫዓߕăဣሣᆐEUJNF
28
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
VOVDD = 1.8V
DA_BYPASS = 1
1.5
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
1.0
0.5
MAX19515 fig15
2.0
DATA DELAY (T FRACTIONAL PERIOD)
DATA DELAY (T FRACTIONAL PERIOD)
RECOMMENDED DATA TIMING
vs. SAMPLE RATE
MAX19515 fig13
2.0
+10/16
+8/16
+6/16
+2/16
0
-2/16
0
VOVDD = 1.8V
DA_BYPASS = 1
1.5
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
1.0
0.5
+10/16
+8/16
+6/16
+2/16
0
-2/16
0
30
40
50
60
30
40
SAMPLING RATE (Msps)
RECOMMENDED DATA TIMING
vs. SAMPLE RATE
MAX19515 fig14
DATA DELAY (T FRACTIONAL PERIOD)
1.5
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
1.0
0.5
+10/16
+8/16
+6/16
+2/16
0
-2/16
0
40
50
MAX19515 fig16
2.0
VOVDD = 3.3V
DA_BYPASS = 1
30
60
ᅄ26/! ᅎୀၫဟኔ)WPWEE >! 2/9W*
FACTORY-DEFAULT NOMINAL DATA
TIMING vs. SAMPLE RATE
2.0
50
SAMPLING RATE (Msps)
ᅄ24/! ෦ཱྀၫဟኔ)WPWEE >! 2/9W*
DATA DELAY (T FRACTIONAL PERIOD)
NBY2:626
FACTORY-DEFAULT NOMINAL DATA
TIMING vs. SAMPLE RATE
VOVDD = 3.3V
DA_BYPASS = 1
1.5
1.0
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
0.5
0
60
30
40
SAMPLING RATE (Msps)
50
+10/16
+8/16
+6/16
+2/16
0
-2/16
60
SAMPLING RATE (Msps)
ᅄ25/! ෦ཱྀၫဟኔ)WPWEE >! 4/4W*
ᅄ27/! ᅎୀၫဟኔ)WPWEE >! 4/4W*
ܭ7/! ᅎୀဟኔࢯᑳ)WPWEE >! 2/9W*
SAMPLING RATE (Msps)
VOVDD = 1.8V
FROM
TO
DA_BYPASS
DLY_HALF_T
DTIME<2:0>
DCLKTIME<2:0>
30
56
1
0
000
000
56
65
1
0
101
101
______________________________________________________________________________________
29
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ܭ8/! ᅎୀဟኔࢯᑳ)WPWEE >! 4/4W*
SAMPLING RATE (Msps)
VOVDD = 3.3V
FROM
TO
DA_BYPASS
DLY_HALF_T
DTIME<2:0>
DCLKTIME<2:0>
30
65
1
0
000
000
ܭ9/! EB`CZQBTT! >! 2ဟLjEDMLUJNFਜ਼EUJNFჅᏤࡼᒙ
DTIME<2:0>
ALLOWED DCLKTIME<2:0> SETTINGS
111 (-3T/16)
111 (-3T/16)
110 (-2T/16)
110 (-2T/16); 111 (-3T/16)
101 (-1T/16)
101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
000 (nominal)
000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
001 (+1T/16)
001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
010 (+2T/16)
010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
011 (+3T/16)
011 (+3T/16); 010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
ܭ:/! আᆡऱज
RESET MODE
DESCRIPTION
Power-On Reset
Upon power-up (AVDD supply voltage and clock signal applied), the POR (power-on-reset) circuit initiates a
register reset.
Software Reset
Write data 5Ah to address 0Ah to initiate register reset.
Hardware Reset A register reset is initiated by the falling edge on the SHDN pin when SPEN is high.
ૹ߅࢟ኹࢯஂ
NBY2:626Ᏼෝผ࢟Ꮞ)BWEE*ૹ߅೫ጙৈᔈଶހሣቶᆮ
ኹLjྙᅄ28ჅာăࡩBWEEࡼ࢟ኹࢅ᎖3WဟLj࢟ኹ
ࢯஂۻവLjऎਖ਼ቦෝผ࢟വᎅᅪ࢟ݝᏎ࢟ăྙਫ
BWEE࢟ኹ᎖3WLjᐌਈஂࢯܕവLjဧถ࢟ኹࢯஂෝ
ါă࢟ኹࢯஂෝါሆLjดݝਖ਼ቦෝผ࢟വᎅࢯஂᄋࡼ
2/9Wᆮࢾ࢟ኹ࢟ăᏴ3/4Wᒗ4/6W BWEEၒྜྷ࢟ኹपᆍดLj
ࢯஂᄋ2/9Wၒ߲࢟ኹăᎅ᎖࢟Ꮞ࢟ഗᏴক࢟ኹपᆍด
ۣߒੱࢾLjჅጲෝผ࢟വࡼᎧჅᔫࡼၒྜྷ࢟ኹ߅
ᑵ܈ă
30
࢟ਜ਼আᆡ
ઓభ߈ܠࡀࡼ෦ཱྀᒙૺ߲ޣᒙࡀᏴऻ
ጵပࡀăୈ࢟ઁLjᑚቋၫᒋۻଝᏲࡵ఼ᒜࡀ
ăকݷᔫखညᏴBWEE࢟ਜ਼ဗଝၒྜྷဟᒩቧᒄઁă
ᒑገBWEEࠀ᎖࢟ᓨზLjۣߒࡀၫᒋăBWEE
࢟ࡼᄴဟLjࡀభጲআᆡLjჅᎌઓభ߈ܠࡀ
࣒ۻ෦ཱྀᒋჅঙăᄰਭࠈాख႙ࡼྟୈෘഎᄰਭ
SPENਜ਼TIEOၒྜྷࡼ፮ୈ఼ᒜLjభࣅআᆡݷᔫăআ
ᆡဟମᎧBEDဟᒩᒲ໐߅ᑵ܈LjᏴ76Ntqtဟኊገ241μtLj
ܭ:࣪আᆡऱजቲ೫ᔐஉă
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
NBY2:626
AVDD
(PINS 1, 12, 13, 48)
REGULATOR
IN
2.3V TO 3.5V
OUT
1.8V
ENABLE
INTERNAL
ANALOG
CIRCUITS
REFERENCE
GND
ᅄ28/! ૹ߅࢟ኹࢯஂ
``````````````````````````````` ።ቧᇦ
0.1μF
1
VIN
6
IN_+
ෝผၒྜྷ
CM_
ܤኹẮތॊෝผၒྜྷ
NBY2:626ݧཝތॊၒྜྷቧဟLjᎌᎁ᎖࣡ၒྜྷད
ࣅࡼTGESਜ਼UIEăތॊၒྜྷෝါሆLjᎅ᎖ೝവၒྜྷဵຳ
ੰࡼLj๔ࠨቕ݆୷ࢅăᅪLjᎧ࣡ၒྜྷෝါሤ܈Ljඛৈ
BEDၒྜྷᒑኊጙࡼۍቧڼ७ă
36.5Ω
0.5%
MAX19515
T1
N.C.
5
2
N.C.
0.1μF
3
SGܤኹ)ᅄ29*ᆐ࣡ቧᓞધᆐཝތॊቧᄋ೫ጙ
ৈੑࡼஊऱښăܤኹᒦቦߥᄿೌᒗDN`Ljᄋ
ৢෝ࢟ኹăᅄᒦܤኹᎌ2;2/5ࡼᔜఝ܈ăጐభጲኡᐋݙ
ᄴࡼဍኹܤኹLjጲଢ଼ࢅདࣅገཇăၒྜྷདࣅቧڼ७ࡼ
ଢ଼ࢅᎌᓐ᎖খ࿖ᑳᄏပᑞăᅄ29Ⴥာᒙ࣪᎖จౠႅᄂຫ
ൈ)gDML03*ጲሆࡼၒྜྷభጲᄋ୷ੑࡼᔫᄂቶă
4
MINI-CIRCUITS 36.5Ω
0.5%
ADT1-1WT
IN_-
ᅄ29/! ၒྜྷຫൈᏴจౠႅᄂຫൈጲሆဟࡼܤኹẮၒྜྷདࣅ
IN_+
0.1μF
1
VIN
N.C.
5
T1
6
2
1
75Ω
0.5%
N.C.
N.C.
5
T2
110Ω
0.5%
6
MAX19515
2
CM_
N.C.
0.1μF
3
4
MINI-CIRCUITS
ADT1-1WT
75Ω
0.5%
3
4
MINI-CIRCUITS
ADT1-1WT
110Ω
0.5%
IN_-
ᅄ2:/! ၒྜྷຫൈިਭจౠႅᄂຫൈဟࡼܤኹẮၒྜྷདࣅ
______________________________________________________________________________________
31
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
VIN
0.1μF
0.01μF
IN_+
MAX4108
CLK+
0.1μF
CLKIN
100Ω
49.9Ω
MAX19515
MAX19515
CM_
100Ω
0.1μF
49.9Ω
0.01μF
CLK-
IN_0.1μF
ᅄ31/! ࣡ĂୣഗẮၒྜྷདࣅ
ᅄ32/! ࣡ᒗތॊဟᒩၒྜྷ
ᅄ2:Ⴥာ࢟വభ࣡ၒྜྷቧᓞધ߅ཝތॊቧăᅄ2:
ࣶ೫ጙৈܤኹLjᎌᓐ᎖খ࿖ৢෝጴᒜᒎܪLjး᎖
᎖จౠႅᄂຫൈࡼຫၒྜྷቧăጙᔝ86Ωਜ਼221Ω࣡࢟
ᔜᆐቧᏎᄋࢀࡼ61Ω࣡ăऔᔝ࣡࢟ᔜೌᒗ
DN`Ljᄋးࡩࡼၒྜྷৢෝ࢟ኹă
ผሣLjኍཀྵۣෝผၒྜྷሣᎧᔈࡼᓞધᄰࡸಭఎLj
ဧᄰࡸମࠈཷଢ଼ᒗᔢࢅăۣᑺჅᎌቧሣభถLj݀
༦ᎌ:1°ᓞ୯ă
``````````````````````````````````` ࢾፃ
࣡ୣഗẮၒྜྷቧ
ᅄ31Ⴥာᆐ࣡ୣഗẮၒྜྷLjNBY5219ᎌႥĂࡒĂ
ࢅᐅဉĂࢅပᑞᄂቶLjۣᑺၒྜྷቧࡼᅲᑳቶăᄰਭดݝ
3lΩ࢟ᔜLjມᒙ࢟ኹᔫࡵၒྜྷ࣡Ljৎࣶቧᇦ༿ݬఠৢෝ
ࡀ19iă
JOMᆐဣࠅހၒၫᎧᔢଛผᒇሣࡼມތLjᔢࡍມࢾތ
ፃᆐJOMă
ᒇഗẮၒྜྷ
NBY2:626୷ࡼৢෝ࢟ኹपᆍ)1/5Wᒗ2/5W*ဧถ৫ݧ
ᒇഗẮቧLjኍཀྵۣৢෝ࢟ኹۣߒᏴ1/5Wᒗ2/5Wᒄମă
EOMဵဣଔࠅၒၫࡼࣞޠݛᎧ2ৈMTCಯሯᒋᒄތLj
ቃ᎖2! MTCࡼEOMᇙۣތᑺޘ્ݙညပ൩Lj݀భཀྵۣࠅၒ
ၫࢯăᏴࠅၒၫࡼඛৈހޠݛEOMມތLjᔢࡍ
ມࢾތፃᆐEOMă
૩ॊऻሣቶ)JOM*
ᆈॊऻሣቶ)EOM*
ဟᒩၒྜྷ
ᅄ32Ⴥာᆐ࣡ᒗތॊࡼဟᒩၒྜྷᓞધ࢟വă
Ăവਜ਼
````````````````````` ࢟വݚۇᓖፀူሲ
NBY2:626ኊገݧႥ࢟വݚۇଆၣăჅᎌവ࢟
ྏణதୈहᒙLjᔢੑᎧBEDࠀ᎖ᄴጙށLjݧܭ
ᄣᏄୈဧည࢟ঢଢ଼ᒗᔢቃăಽ 1/2μG ࡼჿࠣ࢟ྏ
BWEEĂPWEEĂSFGJPĂDNBਜ਼DNCവᒗHOEăࡒᎌ
ށਜ਼࢟Ꮞ࢟ށࣶࡼށവۇถ৫ᔢࡍ߈ۣࣞᑺቧࡼ
ᅲᑳቶăဧඛጙᄰࡸࡼႥၫᔊቧሣᏐಭැঢࡼෝ
32
ပࢯᇙތ
ပࢯᇙܭތာဣଔࠅၒၫᎧಯሯࠅၒၫᏴᒦ࢛ࡼປ
߈ࣞăಯሯ༽ౚሆLjᒦ࢛ᄢ߲ܤሚᏴᒦ࢛ጲ1/6ৈMTC
ࠀLjပࢯᇙဵތဣࡼހᒦ࢛ᄢ࢛ܤᎧಯሯᒦ࢛ᄢ࢛ܤମ
ࡼތᒋă
ᐐፄᇙތ
ᐐፄᇙܭތာᏴਖࢾࡼ൸߈ၒྜྷपᆍดLjဣࠅހၒ
ၫቓൈᎧಯሯࠅၒၫቓൈࡼປࣞăᐐፄᇙࢾތፃᆐ
ဣࠅހၒၫࡼሤ࣪ᇙތLjڻॊܭ܈ာă
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ፒᇄᏭྲࣅზपᆍ)TGES2ਜ਼TGES3*
TTOGᆐቃቧၒྜྷᏴจౠႅᄂຫࡒดࡼಝ૩ᐅဉਜ਼ပᑞ
ൈăଐႯকᐅဉဟ߹ᒇഗပࢯă࣪᎖ᑚᒬᓞધLjቃ
ቧࢾፃᆐ७ᒋቃ᎖.46eCGTࡼፒቧăকݬၫ۞೫
ᓞધࡼེᐅဉਜ਼છᐅဉLj᎖ଐႯ၃ᄰࡸࡼᔐᐅ
ဉᇹၫăਈ᎖ེᐅဉਜ਼છᐅဉࡼሮᇼቧᇦLj༿ݬఠ
dijob/nbyjn.jd/dpnࡼ።܊ă
TGESဵ݆)ᔢࡍቧ߅ॊ*ࡼSNT७ᒋᎧ۞ݙ౪ᒇഗပࢯ
ࡼऔࡍᏭྲ߅ॊࡼSNT७ᒋᒄ܈Ljጲॊ۴ᆐᆡăTGES2
न፯᎖ᔢތ3ࠨ4ࠨቕ݆ပᑞࡼᏭྲቶถăTGES3ࢾፃ
ᆐ۞ݙ౪3ࠨĂ4ࠨቕ݆ૺᒇഗပࢯࡼᔢތᏭྲॊă
ቧᐅ)܈TOS*
࠭ၫᔊݧዹᒦᒮᔢଛ݆ተLjಯ൙TOSᔢࡍᒋဵ൸߈
ෝผၒྜྷ)SNTᒋ*ᎧSNTછᇙ)ތထᇙ*ތᒄ܈Ljಯሯ
༽ౚሆLjෝ0ၫᓞધᐅဉࡼᔢቃಯ൙ᒋஞᎅછᇙޘތညLj
݀༦ᒇᎅBEDࡼॊܦൈ)Oᆡ*ࢾǖ
SNR[max] = 6.02 x N + 1.76
ဣଔLj߹೫છᐅဉᅪથᎌᐅဉᏎ)ಿྙེᐅဉĂ
ᓰᐅဉĂဟᒩ࣌ࣅࢀ*ăTOSݧSNTቧᎧSNTᐅဉᒄ
܈ଐႯăSNTᐅဉ۞౪߹݆Ă༄ങࠨቕ݆)IE3–IE8*
ᎧᒇഗပࢯጲᅪจౠႅᄂຫൈࡼჅᎌຫໍ߅ॊă
⎛ SIGNALRMS ⎞
SNR = 20 × log ⎜
⎟
⎝ NOISERMS ⎠
ᔐቕ݆ပᑞ)UIE*
UIEᄰဵޟၒྜྷቧ༄ങࠨቕ݆ࡼSNTᒄਜ਼Ꭷ݆ᒄ܈Lj
భጲሆါܭာǖ
⎛
V22 + V32 + V4 2 + V52 + V62 + V72
THD = 20 × log ⎜
⎜
V1
⎝
⎞
⎟
⎟
⎠
ᒦW2 ᆐ݆७ᒋLjW3–W8 ᆐ3ࠨᒗ8ࠨቕ݆)IE3–IE8*ࡼ
७ᒋă
ྯୣࢯ)JN4*
JN4ᆐจౠႅᄂຫࡒดྯୣࢯࡼᔐൈᎧೝവፒၒྜྷ
g JO2 ਜ਼g JO3 ᔐൈࡼ܈ᒋăඛവၒྜྷቧ࢟ຳᆐ.8eCGTLj
ྯୣࢯॊᆐǖ3! y! gJO2 .! gJO3Ă3! y! gJO3 .! gJO2Ă3! y! gJO2
,! gJO3Ă3! y! gJO3 ,! gJO2ă
ዓߕ
ቧᎧᐅဉ ,! ပᑞ)܈TJOBE*
TJOBEݧSNTቧᎧSNTᐅဉ , SNTပᑞᒄ܈ଐႯă
SNTᐅဉ۞౪߹݆Ă༄ങࠨቕ݆)IE3–IE8*ਜ਼ᒇഗပࢯ
ጲᅪจౠႅᄂຫൈࡼჅᎌຫໍ߅ॊLjऎSNTပᑞ۞౪༄
ങࠨቕ݆)IE3–IE8*ă
⎛
SIGNALRMS
SINAD = 20 × log ⎜
⎜
2
2
⎝ NOISERMS + DISTORTIONRMS
⎞
⎟
⎟
⎠
ၒྜྷቧᏴݧዹဟᒩࡼဍዘቲݧዹăዓဟ)uBE*ဵ
ᒎݧዹဟᒩဍዘᎧဣଔݧዹၾମࡼᆈቃዓဟă
࣌ࣅ
࣌ࣅ)uBK*ࢾፃᆐݧዹᎧݧዹᒄମዓဟࡼܤછă
ਭདࣅૂআဟମ
ਭདࣅૂআဟମဵBED࠭ިਭ൸߈ሢᒜࡼၒྜྷၾზቲ
ૂআჅኊገࡼဟମăਖࢾਭདࣅૂআဟମᏴၒྜྷި߲൸
߈±21&ࡼ༽ౚሆቲހă
``````````````````````````````` በຢቧᇦ
PROCESS: CMOS
______________________________________________________________________________________
33
NBY2:626
ቃቧᐅ)TTOG*
OVDD
D4B
D5B
D6B
D7B
D8B
D9B
D0A
D1A
D3A
OVDD
TOP VIEW
D2A
```````````````````````````````````````````````````````````````````````````` ୭ᒙ
36 35 34 33 32 31 30 29 28 27 26 25
D4A
37
24
D3B
D5A
38
23
D2B
D6A
39
22
D1B
D7A
40
21
D0B
D8A
41
20
DCLKB
19
DORB
18
GND
D9A
42
DORA
43
DCLKA
44
17
GND
SDIN/FORMAT
45
16
CLK-
SCLK/DIV
46
15
CLK+
CS/OUTSEL
47
14
SYNC
AVDD
48
13
AVDD
MAX19515
*EP
10 11 12
INB-
CMB
9
AVDD
8
I.C.
7
INB+
6
SHDN
INA-
5
SPEN
4
REFIO
3
INA+
1
2
CMA
+
AVDD
NBY2:626
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
*EXPOSED PAD
```````````````````````````````````````````````````````````````````````````` ॖᓤቧᇦ
ྙኊᔢதࡼॖᓤᅪተቧᇦਜ਼ݚLj༿އኯ china.maxim-ic.com/packagesă༿ᓖፀLjॖᓤܠ൩ᒦࡼĐ,đĂ
Đ$đĐ.đஞܭာSpITᓨზă
ॖᓤᅄᒦభถ۞ݙᄴࡼᆘᓮᔊ९LjࡣॖᓤᅄᒑᎧॖᓤᎌਈLjᎧSpITᓨზᇄਈă
34
ॖᓤಢቯ
ॖᓤܠ൩
ᅪተܠ
ݚܠ
48 TQFN-EP
T4877+4
21-0144
90-0130
______________________________________________________________________________________
ၷᄰࡸĂ21ᆡĂ76Ntqt! BED
ኀࢿ
ኀࢿ྇໐
ႁී
0
7/08
ᔢ߱۾ۈă
1
10/08
ኀᑵ೫࢜ቯᔫᄂቶᒦᅄ43ࡼᔑᔬܪă
2
9/10
োDNPTၒ߲དࣅࡼܤછLjৎቤ೫ဟମᄂቶݬၫă
ኀখ
—
11
5, 6, 28, 29, 30
Nbyjn ۱யࠀူێ
۱ய 9439ቧረ ᎆᑶܠ൩ 211194
ॅ࢟જǖ911!921!1421
࢟જǖ121.7322 62::
ࠅᑞǖ121.7322 63::
Nbyjn࣪ݙNbyjnޘອጲᅪࡼྀੜ࢟വဧঌᐊLjጐݙᄋᓜಽభăNbyjnۣഔᏴྀੜဟମĂᎌྀੜᄰۨࡼ༄ᄋሆኀখޘອᓾ೯ਜ਼ਖৃࡼཚಽă
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______________________ 35
© 2010 Maxim Integrated Products
Nbyjn ဵ Nbyjn!Joufhsbufe!Qspevdut-!Jod/ ࡼᓖݿܪă
NBY2:626
```````````````````````````````````````````````````````````````````````````` ኀࢿ಼ဥ
MAX19515 双通道、10位、65Msps ADC - 概述
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Maxim > 产品 > 汽车电子 > MAX19515
Maxim > 产品 > 高速数据转换器 > MAX19515
MAX19515
双通道、10位、65Msps ADC
10位、65Msps、双通道ADC，提供60dBFS SNR和85dBFS SFDR，每通道功耗仅为43mW
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状况：生产中。
概述
数据资料
MAX19515双通道模数转换器(ADC)可提供10位的分辨率并具有65Msps的最大采样速率。
完整的数据资料
提供更新的英文版数据资料
MAX19515的模拟输入可接受0.4V至1.4V的宽输入共模电压范围，可以与宽范围的RF、IF以及基带前端元
件直流耦合输入。在基带至超过400MHz的输入频率范围内，MAX19515具有优异的动态性能，非常适合
零中频(ZIF)和高中频(IF)采样应用。fIN = 70MHz、fCLK = 65MHz时，典型的信噪比(SNR)性能
为60.1dBFS，而典型的无杂散动态范围(SFDR)为82dBc。
英文
下载 Rev. 3 (PDF, 552kB)
中文
下载 Rev. 2 (PDF, 844kB)
MAX19515工作在1.8V电源下。此外，内置的自检测电压调节器可工作在2.5V至3.3V电压(AVDD)下。数
字输出驱动器可工作在1.8V至3.5V的独立电源电压(OVDD)下。VAVDD = 1.8V时，每通道的模拟功耗仅
为43mW。除了具有较低的工作功耗外，MAX19515在断电模式下的功耗仅为1mW，待机模式下的功耗仅
为15mW。
各种调节和功能的选择可以通过3线串行接口访问可编程寄存器实现。此外，串口还可以被禁用，同时提
供三个输入引脚，可选择输出模式、数据格式和时钟分频比。数据输出采用双并行CMOS兼容输出数据总
线，可配置为单复用并行CMOS总线。
MAX19515采用小尺寸、7mm x 7mm、48引脚薄型QFN封装，规定工作在-40°C至+85°C扩展级温度范
围。
引脚及特性兼容的8位65Msps、100Msps以及130Msps版本请分别参考MAX19505、MAX19506以
及MAX19507数据资料。引脚及特性兼容的10位100Msps和130Msps版本请分别参
考MAX19516和MAX19517数据资料。
现备有评估板：MAX19505EVKIT, MAX19506EVKIT, MAX19507EVKIT, MAX19515EVKIT, MAX19516EVKIT, MAX19517EVKIT
注：使用该产品需要以下文件：
MAX19505、MAX19506、MAX19507、MAX19515、MAX19516和MAX19517评估板软件
关键特性
极低的工作功耗(65Msps时为43mW/通道)
1.8V或2.5V至3.3V模拟电源电压
优异的动态性能
70MHz时，SNR为60.1dBFS
70MHz时，SFDR为82dBc
通过SPI™接口实现用户可编程调节和特性选择
可选的数据总线(双CMOS或单复用CMOS)
DCLK输出和可编程数据输出定时，简化了高速数字接口
非常宽的输入共模电压范围(0.4V至1.4V)
非常高的模拟输入带宽(> 850MHz)
单端或差分模拟输入
单端或差分时钟输入
1分频(DIV1)、2分频(DIV2)以及四分频(DIV4)时钟模式
二进制补码、格雷码以及偏移二进制输出数据格式
超限指示器(DOR)
CMOS输出内部端接选项(可编程)
比特顺序可逆(可编程)
数据输出测试模板
小尺寸、7mm x 7mm、48引脚薄型QFN封装，带有裸焊盘
Key Specifications: High-Speed ADCs (> 5Msps)
http://china.maxim-ic.com/datasheet/index.mvp/id/5924[2011-02-23 10:21:04]
应用/使用
数字机顶盒
中频和基带通信，包括：蜂窝基站及点对点微
波接收机
便携式仪表和低功耗数据采集
超声和医学成像
MAX19515 双通道、10位、65Msps ADC - 概述
Part
Number
MAX19515 Smallest
Full
Sample AC
Available
SFDR
Pwr. I CC
Price
Rate Specs
BW (mA) Data Bus Pckg.
Input
Resolution (Msps) (MHz) (dBc) SINAD SNR THD INL
DNL
Features
2
(MHz)
Chan.
Interface (mm )
(bits)
(dB) (dB) (dB) (±LSB) (±LSB)
2
DCLK Output
Programmable
Data Output
Timing
Selectable
Data Bus
10
max ≥
@ f IN
min
65
70
77
59.6
60.1
-79
0.25
0.2
min
typ
850
47
Selectable
Dual/Mux'd
CMOS
查看所有High-Speed ADCs (> 5Msps) (77)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may
differ due to local duties, taxes, fees, and exchange rates. For volume-specific prices and delivery, please see the price and availability page or contact an authorized
distributor.
图表
引脚配置
更多信息
新品发布
[ 2008-10-27 ]
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参考文献： 19- 4195 Rev. 3; 2011- 02- 22
本页最后一次更新: 2011- 02- 22
联络我们：信息反馈、提出问题 • 对该网页的评价 • 发送本网页 • 隐私权政策 • 法律声明
http://china.maxim-ic.com/datasheet/index.mvp/id/5924[2011-02-23 10:21:04]
max
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See
Notes
50.4
$7.50
@1k
MAX19515 双通道、10位、65Msps ADC - 概述
© 2011 Maxim Integrated Products版权所有
http://china.maxim-ic.com/datasheet/index.mvp/id/5924[2011-02-23 10:21:04]
19-4195; Rev 3; 1/11
KIT
ATION
EVALU
E
L
B
A
AVAIL
Dual-Channel, 10-Bit, 65Msps ADC
The MAX19515 dual-channel, analog-to-digital converter (ADC) provides 10-bit resolution and a maximum
sample rate of 65Msps.
The MAX19515 analog input accepts a wide 0.4V to
1.4V input common-mode voltage range, allowing DCcoupled inputs for a wide range of RF, IF, and baseband front-end components. The MAX19515 provides
excellent dynamic performance from baseband to high
input frequencies beyond 400MHz, making the device
ideal for zero-intermediate frequency (ZIF) and highintermediate frequency (IF) sampling applications. The
typical signal-to-noise ratio (SNR) performance is
60.1dBFS and typical spurious-free dynamic range
(SFDR) is 82dBc at fIN = 70MHz and fCLK = 65MHz.
The MAX19515 operates from a 1.8V supply.
Additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5V to 3.3V supply (AVDD).
The digital output drivers operate on an independent
supply voltage (OVDD) over the 1.8V to 3.5V range.
The analog power consumption is only 43mW per channel at V AVDD = 1.8V. In addition to low operating
power, the MAX19515 consumes only 1mW in powerdown mode and 15mW in standby mode.
Various adjustments and feature selections are available through programmable registers that are
accessed through the 3-wire serial-port interface.
Alternatively, the serial-port interface can be disabled,
with the three pins available to select output mode,
data format, and clock-divider mode. Data outputs are
available through a dual parallel CMOS-compatible output data bus that can also be configured as a single
multiplexed parallel CMOS bus.
The MAX19515 is available in a small 7mm x 7mm 48pin thin QFN package and is specified over the -40°C
to +85°C extended temperature range.
Refer to the MAX19505, MAX19506, and MAX19507
data sheets for pin- and feature-compatible 8-bit,
65Msps, 100Msps, and 130Msps versions, respectively.
Refer to the MAX19516 and MAX19517 data sheets for
pin- and feature-compatible 10-bit, 100Msps and
130Msps versions, respectively.
Applications
IF and Baseband Communications, Including
Cellular Base Stations and Point-to-Point
Microwave Receivers
Ultrasound and Medical Imaging
Portable Instrumentation and Low-Power Data
Acquisition
Digital Set-Top Boxes
Features
o Very-Low-Power Operation (43mW/Channel at
65Msps)
o 1.8V or 2.5V to 3.3V Analog Supply
o Excellent Dynamic Performance
60.1dBFS SNR at 70MHz
82dBc SFDR at 70MHz
o User-Programmable Adjustments and Feature
Selection through an SPI™ Interface
o Selectable Data Bus (Dual CMOS or Single
Multiplexed CMOS)
o DCLK Output and Programmable Data Output
Timing Simplifies High-Speed Digital Interface
o Very Wide Input Common-Mode Voltage Range
(0.4V to 1.4V)
o Very High Analog Input Bandwidth (> 850MHz)
o Single-Ended or Differential Analog Inputs
o Single-Ended or Differential Clock Input
o Divide-by-One (DIV1), Divide-by-Two (DIV2), and
Divide-by-Four (DIV4) Clock Modes
o Two’s Complement, Gray Code, and Offset Binary
Output Data Format
o Out-of-Range Indicator (DOR)
o CMOS Output Internal Termination Options
(Programmable)
o Reversible Bit Order (Programmable)
o Data Output Test Patterns
o Small 7mm x 7mm 48-Pin Thin QFN Package with
Exposed Pad
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX19515ETM+
-40°C to +85°C
48 TQFN-EP*
MAX19515ETM/V+
-40°C to +85°C
48 TQFN-EP*
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
SPI is a trademark of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX19515
General Description
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
ABSOLUTE MAXIMUM RATINGS
OVDD, AVDD to GND............................................-0.3V to +3.6V
CMA, CMB, REFIO, INA+, INA-, INB+,
INB- to GND ......................................................-0.3V to +2.1V
CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN
to GND ..........-0.3V to the lower of (VAVDD + 0.3V) and +3.6V
DCLKA, DCLKB, D9A–D0A, D9B–D0B, DORA, DORB
to GND..........-0.3V to the lower of (VOVDD + 0.3V) and +3.6V
Continuous Power Dissipation (TA = +70°C)
48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/°C
above +70°C).............................................................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
INL
fIN = 3MHz
-0.8
±0.25
+0.8
LSB
Differential Nonlinearity
DNL
fIN = 3MHz
-0.7
±0.2
+0.7
LSB
Offset Error
OE
Internal reference
-0.4
±0.1
+0.4
%FS
Gain Error
GE
External reference = 1.25V
-1.5
±0.3
+1.5
%FS
ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)
Differential Input-Voltage Range
VDIFF
Differential or single-ended inputs
Common-Mode Input-Voltage
Range
VCM
(Note 2)
Input Resistance
RIN
Input Current
1.5
0.4
Fixed resistance
Input Capacitance
1.4
V
> 100
Differential input resistance, common mode
connected to inputs
4
IIN
Switched capacitance input current, each
input
35
CPAR
Fixed capacitance to ground, each input
0.7
Switched capacitance, each input
1.2
CSAMPLE
VP-P
kΩ
µA
pF
CONVERSION RATE
Maximum Clock Frequency
fCLK
Minimum Clock Frequency
fCLK
Data Latency
2
65
MHz
30
Figures 9, 10
9
_______________________________________________________________________________________
MHz
Cycles
Dual-Channel, 10-Bit, 65Msps ADC
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Small-Signal Noise Floor
SSNF
Signal-to-Noise Ratio
SNR
fIN = 70MHz, < -35dBFS
-60.4
fIN = 3MHz
fIN = 70MHz
60.2
59.3
fIN = 175MHz
Signal-to-Noise Plus Distortion
Ratio
fIN = 70MHz
59.7
58.8
fIN = 175MHz
Spurious-Free Dynamic Range
(2nd and 3rd Harmonic)
fIN = 70MHz
85
73
fIN = 175MHz
Spurious-Free Dynamic Range
(4th and Higher Harmonics)
Second Harmonic
HD2
Third Harmonic
HD3
Total Harmonic Distortion
Third-Order Intermodulation
Full-Power Bandwidth
THD
IM3
fIN = 70MHz
dBc
84
81
fIN = 3MHz
SFDR2
dB
59.6
59.3
fIN = 3MHz
SFDR1
dBFS
60.1
59.8
fIN = 3MHz
SINAD
dBFS
82
74.4
dBc
82
fIN = 175MHz
82
fIN = 3MHz
-86
fIN = 70MHz
-86
fIN = 175MHz
-82
fIN = 3MHz
-86
fIN = 70MHz
-86
fIN = 175MHz
-82
fIN = 3MHz
-80
fIN = 70MHz
-79
fIN = 175MHz
-77
fIN = 70MHz ±1.5MHz, -7dBFS
-90
fIN = 175MHz ±2.5MHz, -7dBFS
-80
-73
dBc
-74
dBc
-71.8
dBc
dBc
FPBW
850
Aperture Delay
tAD
850
ps
Aperture Jitter
tAJ
0.3
psRMS
1
Cycles
Overdrive Recovery Time
±10% beyond full scale
MHz
_______________________________________________________________________________________
3
MAX19515
ELECTRICAL CHARACTERISTICS (continued)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INTERCHANNEL CHARACTERISTICS
Crosstalk
fINA or fINB = 70MHz at -1dBFS
95
fINA or fINB = 175MHz at -1dBFS
85
dBc
Gain Match
fIN = 70MHz
±0.05
dB
Offset Match
fIN = 70MHz
±0.1
%FSR
Phase Match
fIN = 70MHz
±0.5
Degrees
ANALOG OUTPUTS (CMA, CMB)
CMA, CMB Output Voltage
VCOM
Default programmable setting
0.85
0.9
0.95
1.25
1.27
V
INTERNAL REFERENCE
REFIO Output Voltage
REFIO Temperature Coefficient
VREFOUT
1.23
V
TCREF
< ±60
ppm/°C
REFIO Input-Voltage Range
VREFIN
1.25 +5/
-10%
V
REFIO Input Resistance
RREFIN
10
±20%
kΩ
0.4 to 2.0
VP-P
EXTERNAL REFERENCE
CLOCK INPUTS (CLK+, CLK-)—DIFFERENTIAL MODE
Differential Clock Input Voltage
Self-biased
Differential Input Common-Mode
Voltage
Input Resistance
Input Capacitance
1.2
DC-coupled clock signal
RCLK
CCLK
V
1.0 to 1.4
Differential, default
10
Differential, internal termination selected
kΩ
100
Ω
Common mode
9
kΩ
To ground, each input
3
pF
CLOCK INPUTS (CLK+, CLK-)—SINGLE-ENDED MODE (VCLK- < 0.1V)
Single-Ended Mode Selection
Threshold (VCLK-)
0.1
Allowable Logic Swing (VCLK+)
0 - VAVDD
Single-Ended Clock Input High
Threshold (VCLK+)
Input Leakage (CLK-)
Input Capacitance (CLK+)
4
V
1.5
V
Single-Ended Clock Input Low
Threshold (VCLK+)
Input Leakage (CLK+)
0.3
VCLK+ = VAVDD = 1.8V or 3.3V
+0.5
VCLK+ = 0V
-0.5
VCLK- = 0V
-150
V
-50
3
_______________________________________________________________________________________
V
µA
µA
pF
Dual-Channel, 10-Bit, 65Msps ADC
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUT (SYNC)
Allowable Logic Swing
0 - VAVDD
Sync Clock Input High Threshold
V
1.5
V
Sync Clock Input Low Threshold
0.3
VSYNC = VAVDD = 1.8V or 3.3V
Input Leakage
VSYNC = 0V
+0.5
-0.5
Input Capacitance
V
µA
4.5
pF
0 - VAVDD
V
DIGITAL INPUTS (SHDN, CS)
Allowable Logic Swing
Input High Threshold
1.5
V
Input Low Threshold
0.3
VSHDN/VSPEN = VAVDD = 1.8V or 3.3V
Input Leakage
VSHDN/VSPEN = 0V
Input Capacitance
+0.5
-0.5
CDIN
V
µA
3
pF
0 - VAVDD
V
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)—SERIAL-PORT CONTROL MODE
Allowable Logic Swing
Input High Threshold
1.5
V
Input Low Threshold
0.3
VSCLK/VSDIN/VCS = VAVDD = 1.8V or 3.3V
Input Leakage
VSCLK/VSDIN/VCS = 0V
Input Capacitance
+0.5
-0.5
CDIN
3
V
µA
pF
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = VAVDD)—PARALLEL CONTROL MODE (Figure 5)
Input Pullup Current
Input Pulldown Current
Open-Circuit Voltage
VOC
VSCLK/VSDIN/VCS = VAVDD = 1.8V
7
12
17
VSCLK/VSDIN/VCS = VAVDD = 3.3V
16
21
26
VSCLK/VSDIN/VCS = 0V, VAVDD = 1.8V
-65
-50
-35
VSCLK/VSDIN/VCS = 0V, VAVDD = 3.3V
-105
-90
-75
VAVDD = 1.8V
1.35
1.45
1.55
VAVDD = 3.3V
2.58
2.68
2.78
µA
µA
V
DIGITAL OUTPUTS (75Ω, D0–D9 (A and B Channel), DCLKA, DCLKB, DORA, DORB)
Output-Voltage Low
VOL
ISINK = 200µA
Output-Voltage High
VOH
ISOURCE = 200µA
Three-State Leakage Current
ILEAK
0.2
VOVDD
- 0.2
VOVDD applied
GND applied
V
+0.5
-0.5
V
µA
_______________________________________________________________________________________
5
MAX19515
ELECTRICAL CHARACTERISTICS (continued)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-MANAGEMENT CHARACTERISTICS
Wake-Up Time from Shutdown
tWAKE
Internal reference, CREFIO = 0.1µF (10τ)
5
ms
Wake-Up Time from Standby
tWAKE
Internal reference
15
µs
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)
SCLK Period
tSCLK
50
ns
SCLK to CS Setup Time
tCSS
10
ns
SCLK to CS Hold Time
tCSH
10
ns
SDIN to SCLK Setup Time
tSDS
Serial-data write
10
ns
SDIN to SCLK Hold Time
tSDH
Serial-data write
0
SCLK to SDIN Output Data Delay
tSDD
Serial-data read
ns
10
ns
TIMING CHARACTERISTICS—DUAL BUS PARALLEL MODE (Figure 9) (Default Timing, see Table 5)
Clock Pulse-Width High
tCH
7.69
ns
Clock Pulse-Width Low
tCL
7.69
ns
tCH/tCLK
30 to 70
%
Clock Duty Cycle
Data Delay After Rising Edge of
CLK+
tDD
CL = 10pF, VOVDD = 1.8V (Note 2)
3.4
CL = 10pF, VOVDD = 3.3V
5.3
7.1
4.1
ns
Data to DCLK Setup Time
tSETUP
CL = 10pF, VOVDD = 1.8V (Note 2)
12.8
13.4
ns
Data to DCLK Hold Time
tHOLD
CL = 10pF, VOVDD = 1.8V (Note 2)
1.4
2.0
ns
TIMING CHARACTERISTICS—MULTIPLEXED BUS PARALLEL MODE (Figure 10) (Default Timing, see Table 5)
Clock Pulse-Width High
tCH
7.69
ns
Clock Pulse-Width Low
tCL
7.69
ns
tCH/tCLK
30 to 70
%
Clock Duty Cycle
Data Delay After Rising Edge of
CLK+
Data to DCLK Setup Time
Data to DCLK Hold Time
tDD
CL = 10pF, VOVDD = 1.8V (Note 2)
3.3
CL = 10pF, VOVDD = 3.3V
5.2
7.0
4.0
tSETUP
CL = 10pF, VOVDD = 1.8V (Note 2)
5.0
5.9
ns
ns
tHOLD
CL = 10pF, VOVDD = 1.8V (Note 2)
1.2
1.8
DCLK Duty Cycle
tDCH/tCLK
CL = 10pF, VOVDD = 1.8V (Note 2)
44
50
56
ns
%
MUX Data Duty Cycle
tCHA/tCLK
CL = 10pF, VOVDD = 1.8V (Note 2)
44
50
56
%
TIMING CHARACTERISTICS—SYNCHRONIZATION (Figure 12)
Setup Time for Valid Clock Edge
tSUV
Edge mode (Note 2)
0.7
ns
Hold-Off Time for Invalid Clock
Edge
tSDH
Edge mode (Note 2)
0.5
ns
Minimum Synchronization Pulse
Width
6
Relative to input clock period
2
_______________________________________________________________________________________
Cycles
Dual-Channel, 10-Bit, 65Msps ADC
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
VAVDD
Digital Output Supply Voltage
VOVDD
Analog Supply Current
Analog Power Dissipation
Digital Output Supply Current
IAVDD
PDA
IOVDD
Low-level VAVDD
1.7
1.9
High-level VAVDD (regulator mode, invoked
automatically)
2.3
3.5
1.7
3.5
Dual channel
47
Single channel active
28
8.5
12
Power-down mode
0.65
0.9
Power-down mode, VAVDD = 3.3V
1.6
Dual channel
85
Dual channel, VAVDD = 3.3V
155
Single channel active
50
Standby mode
15
22
Power-down mode
1.2
1.6
Power-down mode, VAVDD = 3.3V
2.9
Dual-channel mode, CL = 10pF
13
< 0.1
V
55
Standby mode
Power-down mode
V
mA
99
mW
mA
Note 1: Specifications ≥ +25°C guaranteed by production test, specifications < +25°C guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
_______________________________________________________________________________________
7
MAX19515
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
3MHz SINGLE-ENDED INPUT FFT PLOT
-100
-60
-100
-120
10
15
20
25
FREQUENCY (MHz)
30
175MHz INPUT FFT PLOT
10
15
20
25
FREQUENCY (MHz)
30
0
-100
0
-40
-60
-80
-100
-120
10
15
20
25
30
5
10
15
20
25
FREQUENCY (MHz)
0.8
0
0.2
DNL (LSB)
0.4
0.2
0
-0.2
90
0
-0.2
SFDR2
SFDR1
80
75
-THD
70
65
-0.6
-0.6
60
-0.8
-0.8
55
-1.0
-1.0
50
1024
SNR
0
256
512
768
DIGITAL OUTPUT CODE
30
85
-0.4
256
512
768
DIGITAL OUTPUT CODE
10
15
20
25
FREQUENCY (MHz)
PERFORMANCE vs. INPUT FREQUENCY
-0.4
0
5
95
PERFORMANCE (dBFS)
0.6
0.4
MAX19515 toc03
-80
30
MAX19515 toc08
1.0
MAX19515 toc07
0.6
-60
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.8
-40
-120
0
FREQUENCY (MHz)
1.0
30
-100
-120
5
10
15
20
25
FREQUENCY (MHz)
fIN1 = 172.49286MHz
fIN2 = 177.50202MHz
-20
AMPLITUDE (dBFS)
-80
0
5
175MHz TWO-TONE IMD
fIN1 = 71.496925MHz
fIN2 = 68.504600MHz
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-60
5
0
MAX19515 toc04
fIN = 175.096626MHz
AIN = -0.512dBFS
SNR = 59.073dB
SINAD = 59.022dB
THD = -78.338dBc
SFDR1 = 81.806dBc
SFDR2 = 84.255dBc
-40
-80
70MHz TWO-TONE IMD PLOT
0
-20
-60
-120
0
MAX19515 toc05
5
-40
-100
-120
0
8
MAX19515 toc02
-80
fIN = 70.1014328MHz
AIN = -0.532dBFS
SNR = 59.432dB
SINAD = 58.388dB
THD = -79.349dBc
SFDR1 = 84.227dBc
SFDR2 = 81.877dBc
-20
MAX19515 toc06
-80
-40
70MHz INPUT FFT PLOT
0
AMPLITUDE (dBFS)
-60
fIN = 2.99877166748047MHz
AIN = -0.546dBFS
SNR = 59.675dB
SINAD = 59.632dB
THD = -79.673dBc
SFDR1 = 88.737dBc
SFDR2 = 82.290dBc
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
MAX19515 toc01
fIN = 2.99877166MHz
AIN = -0.532dBFS
SNR = 59.682dB
SINAD = 59.641dB
THD = -79.826dBc
SFDR1 = 83.946dBc
SFDR2 = 82.852dBc
-20
0
1024
MAX19515 toc09
3MHz INPUT FFT PLOT
0
INL (LSB)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
0
50
SINAD
100 150 200 250 300 350 400
INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
80
SFDR1
70
65
SNR
-THD
SFDR2
90
80
-THD
70
SFDR1
85
80
75
-THD
70
SNR
65
60
60
55
SINAD
-80
70
PERFORMANCE
vs. COMMON-MODE VOLTAGE
SFDR2
85
80
75
-THD
70
SNR
65
90
60
SFDR1
80
75
-THD
70
65
SNR
60
55
55
0.55
0.75
0.95
1.15
1.35
COMMON-MODE VOLTAGE (V)
1.65
75
-THD
70
65
SNR
60
55
SINAD
1.70 1.75 1.80 1.85 1.90
ANALOG SUPPLY VOLTAGE (V)
1.95
2.3
40
38
36
34
48
47
46
45
44
43
42
32
41
30
40
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (MHz)
MAX19515 toc17
49
50
49
ANALOG SUPPLY CURRENT (mA)
42
50
ANALOG SUPPLY CURRENT (mA)
44
2.5
2.7
2.9
3.1
3.3
ANALOG SUPPLY VOLTAGE (V)
3.5
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
MAX19515 toc16
46
SFDR1
80
50
ANALOG SUPPLY CURRENT
vs. SAMPLING FREQUENCY
48
SFDR2
85
50
0.35
50
90
SINAD
SINAD
50
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGE
SFDR2
85
PERFORMANCE (dBFS)
SFDR1
90
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (Msps)
0
PERFORMANCE
vs. ANALOG SUPPLY VOLTAGE
MAX19515 toc13
95
-70 -60 -50 -40 -30 -20 -10
ANALOG INPUT AMPLITUDE (dBFS)
MAX19515 toc15
60
PERFORMANCE (dBFS)
20
30
40
50
INPUT FREQUENCY (MHz)
MAX19515 toc14
10
SINAD
50
50
MAX19515 toc18
55
0
PERFORMANCE (dBFS)
SFDR2
90
60
50
ANALOG SUPPLY CURRENT (mA)
SINAD
SNR
95
MAX19515 toc12
100
PERFORMANCE (dBFS)
85
SFDR1
PERFORMANCE (dBFS)
SFDR2
75
110
MAX19515 toc11
90
MAX19515 toc10
SINGLE-ENDED PERFORMANCE (dBFS)
95
PERFORMANCE
vs. SAMPLING FREQUENCY
PERFORMANCE
vs. ANALOG INPUT AMPLITUDE
SINGLE-ENDED PERFORMANCE
vs. INPUT FREQUENCY
48
47
46
45
44
43
42
41
40
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
1.65
1.70
1.75 1.80 1.85
SUPPLY VOLTAGE (V)
1.90
_______________________________________________________________________________________
1.95
9
MAX19515
Typical Operating Characteristics (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
47
46
45
44
43
42
VOVDD = 1.8V
10
8
6
4
2
25
MAX19515 toc21
48
12
MAX19515 toc20
49
DIGITAL SUPPLY CURRENT (mA)
MAX19515 toc19
50
ANALOG SUPPLY CURRENT (mA)
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
DIGITAL SUPPLY CURRENT
vs. SAMPLING FREQUENCY
VOVDD = 3.6V
DIGITAL SUPPLY CURRENT (mA)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
20
15
10
5
41
0
2.7
2.9
3.1
SUPPLY VOLTAGE (V)
3.3
3.5
0
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (Msps)
20 25 30 35 40 45 50 55 60 65 70
SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
23
SUPPLY CURRENT (mA)
21
19
VOVDD = 3.6V
17
15
VOVDD = 1.8V
13
11
9
25
DUAL BUS
DIGITAL SUPPLY CURRENT (mA)
MAX19515 toc22
25
20
15
10
5
30
MULTIPLEXED BUS
DIGITAL SUPPLY CURRENT (mA)
2.5
MAX19515 toc23
2.3
MAX19515 toc24
40
25
20
15
10
5
7
0
0
5
60
PERFORMANCE
vs. CLOCK DUTY CYCLE
SFDR2
-THD
70
SNR
SFDR1
90
85
PERFORMANCE (dBFS)
80
65
95
MAX19515 toc25
SFDR1
75
80
SFDR2
-THD
75
70
SNR
65
60
SINAD
10
40
45
50
55
CLOCK DUTY CYCLE (%)
60
65
0.03
0.02
0.01
0
-0.01
-0.04
SINAD
-0.05
50
35
0.04
-0.03
55
55
0.05
-0.02
60
30
GAIN ERROR vs. TEMPERATURE
PERFORMANCE vs. TEMPERATURE
90
85
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
SUPPLY VOLTAGE (V)
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
SUPPLY VOLTAGE (V)
80
MAX19515 toc27
0
20
40
TEMPERATURE (°C)
GAIN ERROR (%)
-20
MAX19515 toc26
-40
PERFORMANCE (dBFS)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
-40
-20
0
20
40
TEMPERATURE (°C)
______________________________________________________________________________________
60
80
Dual-Channel, 10-Bit, 65Msps ADC
REFERENCE VOLTAGE (V)
-0.1
-0.2
-0.3
-0.4
-0.5
1.2495
1.2474
1.2453
-0.6
-0.7
60
80
VCM = 1.2V
1.2
VCM = 1.05V
1.0
VCM = 0.9V
0.8
VCM = 0.75V
VCM = 0.6V
0.6
VCM = 0.45V
0.4
0.2
-40
-20
0
20
40
TEMPERATURE (°C)
60
MAX19515 toc31
0.06
80
-40
-20
0
20
40
TEMPERATURE (°C)
60
80
INPUT CURRENT
vs. COMMON-MODE VOLTAGE
GAIN ERROR vs. SUPPLY VOLTAGE
0.08
60
55
0.02
0
-0.02
REGULATOR MODE
INPUT CURRENT (µA)
0.04
50
45
40
35
-0.04
30
-0.06
25
-0.08
MAX19515 toc32
0
20
40
TEMPERATURE (°C)
GAIN ERROR (%)
-20
VCM = 1.35V
1.4
0
1.2432
-40
MAX19515 toc30
0
1.6
COMMON-MODE REFERENCE VOLTAGE (V)
0.1
MAX19515 toc29
1.2516
MAX19515 toc28
0.2
OFFSET ERROR (mV)
COMMON-MODE REFERENCE VOLTAGE
vs. TEMPERATURE
REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR vs. TEMPERATURE
20
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4
COMMON-MODE VOLTAGE (V)
______________________________________________________________________________________
11
MAX19515
Typical Operating Characteristics (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 65MHz, AIN = -0.5dBFS, data output termination
= 50Ω, TA = +25°C, unless otherwise noted.)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
Pin Description
PIN
NAME
1, 12, 13, 48
AVDD
12
FUNCTION
Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1µF.
2
CMA
Channel A Common-Mode Input-Voltage Reference
3
INA+
Channel A Positive Analog Input
4
INA-
Channel A Negative Analog Input
5
SPEN
Active-Low SPI Enable. Drive high to enable parallel programming mode.
6
REFIO
Reference Input/Output. To use internal reference, bypass to GND with a > 0.1µF capacitor. See
the Reference Input/Output (REFIO) section for external reference adjustment.
7
SHDN
Active-High Power-Down. If SPEN is high (parallel programming mode), a register reset is initiated
on the falling edge of SHDN.
8
I.C.
9
INB+
Internally Connected. Leave unconnected.
Channel B Positive Analog Input
10
INB-
Channel B Negative Analog Input
11
CMB
Channel B Common-Mode Input-Voltage Reference
14
SYNC
Clock-Divider Mode Synchronization Input
15
CLK+
Clock Positive Input
16
CLK-
Clock Negative Input. If CLK- is connected to ground, CLK+ is a single-ended logic-level clock
input. Otherwise, CLK+/CLK- are self-biased differential clock inputs.
17, 18
GND
19
DORB
Channel B Data Over Range
Ground. Connect all ground inputs and EP (exposed pad) together.
20
DCLKB
Channel B Data Clock
21
D0B
Channel B Three-State Digital Output, Bit 0 (LSB)
22
D1B
Channel B Three-State Digital Output, Bit 1
23
D2B
Channel B Three-State Digital Output, Bit 2
Channel B Three-State Digital Output, Bit 3
24
D3B
25, 36
OVDD
26
D4B
Channel B Three-State Digital Output, Bit 4
27
D5B
Channel B Three-State Digital Output, Bit 5
28
D6B
Channel B Three-State Digital Output, Bit 6
29
D7B
Channel B Three-State Digital Output, Bit 7
30
D8B
Channel B Three-State Digital Output, Bit 8
31
D9B
Channel B Three-State Digital Output, Bit 9 (MSB)
32
D0A
Channel A Three-State Digital Output, Bit 0 (LSB)
33
D1A
Channel A Three-State Digital Output, Bit 1
34
D2A
Channel A Three-State Digital Output, Bit 2
35
D3A
Channel A Three-State Digital Output, Bit 3
37
D4A
Channel A Three-State Digital Output, Bit 4
38
D5A
Channel A Three-State Digital Output, Bit 5
39
D6A
Channel A Three-State Digital Output, Bit 6
Digital Supply Voltage. Bypass each OVDD input to GND with 0.1µF capacitor.
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
PIN
NAME
40
D7A
Channel A Three-State Digital Output, Bit 7
FUNCTION
41
D8A
Channel A Three-State Digital Output, Bit 8
42
D9A
43
DORA
Channel A Data Over Range
44
DCLKA
Channel A Data Clock
45
SDIN/FORMAT
46
SCLK/DIV
Serial Clock/Clock Divider. Serial clock when SPEN is low. Clock divider when SPEN is high.
47
CS/OUTSEL
Serial-Port Select/Data Output Mode. Serial-port select when SPEN is low. Data output mode
selection when SPEN is high.
—
EP
Channel A Three-State Digital Output, Bit 9 (MSB)
SPI Data Input/Format. Serial-data input when SPEN is low. Output data format when SPEN is high.
Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal
performance.
Detailed Description
The MAX19515 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 9 clock cycles.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital output code is multiplied and passed on to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX19515 functional diagram.
Analog Inputs and Common-Mode
Reference
Apply the analog input signal to the analog inputs
(INA+/INA- or INB+/INB-), which are connected to the
input sampling switch (Figure 3). When the input sampling switch is closed, the input signal is applied to the
sampling capacitors through the input switch resistance.
The input signal is sampled at the instant the input
switch opens. The pipeline ADC processes the sampled
voltage and the digital output result is available 9 clock
cycles later. Before the input switch is closed to begin
the next sampling cycle, the sampling capacitors are
reset to the input common-mode potential.
Common-mode bias can be provided externally or
internally through 2kΩ resistors. In DC-coupled applications, the signal source provides the external bias and
the bias current. In AC-coupled applications, the input
+
MAX19515
Σ
x2
−
FLASH
ADC
DAC
IN_+
STAGE 1
STAGE 2
STAGE 9
IN_-
STAGE 10
END OF PIPELINE
DIGITAL ERROR CORRECTION
D0_ THROUGH D9_
Figure 1. Pipeline Architecture—Stage Blocks
current is supplied by the common-mode input voltage.
For example, the input current can be supplied through
the center tap of a transformer secondary winding.
Alternatively, program the appropriate internal register
through the serial-port interface to supply the input DC
current through internal 2kΩ resistors (Figure 3). When
the input current is supplied through the internal resistors, the input common-mode potential is reduced by
the voltage drop across the resistors. The commonmode input reference voltage can be adjusted through
programmable register settings from 0.45V to 1.35V in
0.15V increments. The default setting is 0.90V. Use this
feature to provide a common-mode output reference to
a DC-coupled driving circuit.
______________________________________________________________________________________
13
MAX19515
Pin Description (continued)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
CLOCK
MAX19515
INA+
T/H
INA-
PIPELINE
ADC
DIGITAL
ERROR
CORRECTION
D0A–D9A
DORA
DCLKA
CMA
REFIO
CMB
REFERENCE
AND BIAS
SYSTEM
INTERNAL
REFERENCE
GENERATOR
PIPELINE
ADC
DIGITAL
ERROR
CORRECTION
DATA
AND
OUTPUT
FORMAT
OUTPUT
DRIVERS
OVDD
(1.8V TO 3.3V)
D0B–D9B
INB+
T/H
INB-
DORB
DCLKB
CLOCK
CLK+
CLOCK
DIVIDER
CLK-
DUTYCYCLE
EQUALIZER
SYNC
AVDD
(1.8V OR
2.5V TO 3.3V)
REGULATOR
AND
POWER CONTROL
1.8V INTERNAL
CS
SERIAL PORT
AND
CONTROL REGISTERS
SCLK
SDIN
SHDN
INTERNAL CONTROL
GND
SPEN
Figure 2. Functional Diagram
AVDD
CMA
RSWITCH
120Ω
INA+
CSAMPLE
1.2pF
CPAR
0.7pF
2kΩ
*VCOM
AVDD
2kΩ
RSWITCH
120Ω
INACPAR
0.7pF
CSAMPLE
1.2pF
SAMPLING CLOCK
MAX19515
*VCOM PROGRAMMABLE FROM 0.45V TO 1.35V. SEE COMMON-MODE REGISTER (08h)
Figure 3. Internal Track-and-Hold (T/H) Circuit
14
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
INTERNAL GAIN—BYPASS REFIO
EXTERNAL GAIN CONTROL—DRIVE REFIO
36kΩ
0.1µF
EXTERNAL BYPASS
REFIO
1.250V
BANDGAP
REFERENCE
10kΩ
BUFFER
DECODER
CS
SCLK
SDIN
23/32 AVDD
TO
CONTROL
LOGIC
156kΩ
SCALE AND
INTERNAL REFERENCE
LEVEL SHIFT
(CONTROLS ADC GAIN)
3/32 AVDD
Figure 4. Simplified Reference Schematic
Figure 5. Simplified Parallel-Interface Input Schematic
Table 1. Parallel-Interface Pin Functionality
SPEN
SDIN/FORMAT
SCLK/DIV
CS/OUTSEL
DESCRIPTION
SPI interface active. Features are programmed through the
serial port (see the Serial Programming Interface section).
SDIN
SCLK
CS
1
0
X
X
1
AVDD
X
X
Offset binary
1
Unconnected
X
X
Gray code
1
X
0
X
Clock divide-by-1
1
X
AVDD
X
Clock divide-by-2
1
X
Unconnected
X
Clock divide-by-4
1
X
X
0
CMOS (dual bus)
1
X
X
AVDD
MUX CMOS (channel A data bus)
X
X
Unconnected
MUX CMOS (channel B data bus)
0
1
X = Don’t care.
Two’s complement
Reference Input/Output (REFIO)
Programming and Interface
REFIO adjusts the reference potential, which, in turn,
adjusts the full-scale range of the ADC. Figure 4 shows
a simplified schematic of the reference system. An
internal bandgap voltage generator provides an internal
reference voltage. The bandgap potential is buffered
and applied to REFIO through a 10kΩ resistor. Bypass
REFIO with a 0.1µF capacitor to GND. The bandgap
voltage is applied to a scaling and level-shift circuit,
which creates internal reference potentials that establish the full-scale range of the ADC. Apply an external
voltage on REFIO to trim the ADC full scale. The allowable adjustment range is +5/-15%. The REFIO-to-ADC
gain transfer function is:
VFS = 1.5 x [VREFIO/1.25] Volts
There are two ways to control the MAX19515 operating
modes. Full feature selection is available using the SPI
interface, while the parallel interface offers a limited set
of commonly used features. The programming mode is
selected using the SPEN input. Drive SPEN low for SPI
interface; drive SPEN high for parallel interface.
Parallel Interface
The parallel interface offers a pin-programmable interface with a limited feature set. Connect SPEN to AVDD
to enable the parallel interface. See Table 1 for pin
functionality; see Figure 5 for a simplified parallel-interface input schematic.
______________________________________________________________________________________
15
MAX19515
29/32 AVDD
AVDD
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
CS
SCLK
SDIN
R/W
A6
A5
A4
A3
R/W
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
DATA
WRITE OR READ
ADDRESS
0 = WRITE
1 = READ
Figure 6. Serial-Interface Communication Cycle
tCSH
tCSS
CS
tSCLK
SCLK
tSDS
tSDH
tSDD
SDIN
WRITE
READ
Figure 7. Serial-Interface Timing Diagram
Serial Programming Interface
A serial interface programs the MAX19515 control registers through the CS, SDIN, and SCLK inputs. Serial
data is shifted into SDIN on the rising edge of SCLK
when CS is low. The MAX19515 ignores the data presented at SDIN and SCLK when CS is high. CS must
transition high after each read/write operation. SDIN
also serves as the serial-data output for reading control
registers. The serial interface supports two-byte transfer
in a communication cycle. The first byte is a control
byte, containing the address and read/write instruction,
written to the MAX19515. The second byte is a data
byte and can be written to or read from the MAX19515.
Figure 6 shows a serial-interface communication cycle.
The first SDIN bit clocked in establishes the communi-
16
cation cycle as either a write or read transaction (0 for
write operation and 1 for read operation). The following
7 bits specify the address of the register to be written or
read. The final 8 SDIN bits are the register data. All
address and data bits are clocked in or out MSB first.
During a read operation, the MAX19515 serial port drives read data (D7) into SDIN after the falling edge of
SCLK following the 8th rising edge of SCLK. Since the
minimum hold time on SDIN input is zero, the master
can stop driving SDIN any time after the 8th rising edge
of SCLK. Subsequent data bits are driven into SDIN on
the falling edge of SCLK. Output data in a read operation is latched on the rising edge of SCLK. Figure 7
shows the detailed serial-interface timing diagram.
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
ters are reset to default values. A read operation of register 0Ah returns a status byte with information
described in Table 2.
Table 2. Register 0Ah Status Byte
BIT NO.
VALUE
7
0
DESCRIPTION
Reserved
6
0
5
0 or 1
1 = ROM read in progress
Reserved
4
0 or 1
1 = ROM read completed and register data is valid (checksum is OK)
3
0
2
1
Reserved
1
0 or 1
Reserved
0
0 or 1
1 = Duty-cycle equalizer DLL is locked
Reserved
User-Programmable Registers
Table 3. User-Programmable Registers
ADDRESS
POR DEFAULT
FUNCTION
00h
00000011
01h
00000000
Output format
02h
00000000
Digital output power management
03h
10000000
Data/DCLK timing
04h
00000000
CHA data output termination control
05h
00000000
CHB data output termination control
06h
00000000
Clock divide/data format/test pattern
07h
Reserved
Reserved—do not use
08h
00000000
Common mode
0Ah
—
Software reset
Power management
Power Management (00h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
HPS_SHDN1 STBY_SHDN1 CHB_ON_SHDN1 CHA_ON_SHDN1 HPS_SHDN0 STBY_SHDN0 CHB_ON_SHDN0 CHA_ON_SHDN0
The SHDN input (pin 7) toggles between any two
power-management states. The Power Management
register defines each power-management state. In the
default state, SHDN = 1 shuts down the MAX19515 and
SHDN = 0 returns to full power.
______________________________________________________________________________________
17
MAX19515
Register address 0Ah is a special-function register.
Writing data 5Ah to register 0Ah initiates a register
reset. When this operation is executed, all control regis-
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
In addition to power management, the HPS_SHDN1
and HPS_SHDN0 activate an A+B adder mode. In this
mode, the results from both channels are averaged.
The MUX_CH bit selects which bus the (A+B)/2 data is
presented.
Control Bits:
HPS_SHDN0
STBY_SHDN0
CHA_ON_SHDN0
CHB_ON_SHDN0
SHDN INPUT = 0*
HPS_SHDN1
STBY_SHDN1
CHA_ON_SHDN1
CHB_ON_SHDN1
SHDN INPUT = 1**
X
0
0
0
Complete power-down
0
0
0
1
Channel B active, channel A full power-down
0
0
1
0
Channel A active, channel B full power-down
0
X
1
1
Channels A and B active
0
1
0
0
Channels A and B in standby mode
0
1
0
1
Channel B active, channel A standby
0
1
1
0
Channel A active, channel B standby
1
1
0
0
Channels A and B in standby mode
1
X
X
1
Channels A and B active, output is averaged
1
X
1
X
Channels A and B active, output is averaged
*HPS_SHDN0, STBY_SHDN0, CHA_ON_SHDN0, and CHB_ON_SHDN0 are active when SHDN = 0.
**HPS_SHDN1, STBY_SHDN1, CHA_ON_SHDN1, and CHB_ON_SHDN1 are active when SHDN = 1.
X = Don’t care.
Note: When HPS_SHDN_ = 1 (A+B adder mode), CHA_ON_SHDN_ and CHB_ON_SHDN_ must BOTH equal 0 for power-down or
standby.
Output Format (01h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
0
BIT_ORDER_B
BIT_ORDER_A
MUX_CH
MUX
0
Bit 7, 6, 5
Set to 0 for proper operation
Bit 4
BIT_ORDER_B: Reverse CHB output bit order
0 = Defined data bus pin order (default)
1 = Reverse data bus pin order
Bit 3
BIT_ORDER_A: Reverse CHA output bit order
0 = Defined data bus pin order (default)
1 = Reverse data bus pin order
Bit 2
MUX_CH: Multiplexed data bus selection
0 = Multiplexed data output on CHA (CHA data presented first, followed by CHB data) (default)
1 = Multiplexed data output on CHB (CHB data presented first, followed by CHA data)
Bit 1
MUX: Digital output mode
0 = Dual data bus output mode (default)
1 = Single multiplexed data bus output mode
MUX_CH selects the output bus
Bit 0
Set to 0 for proper operation
18
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
X
X
PD_DOUT_1
PD_DOUT_0
DIS_DOR
DIS_DCLK
Bit 7–4
Don’t care
Bit 3, 2
PD_DOUT_1, PD_DOUT_0: Power-down digital output state control
00 = Digital output three state (default)
01 = Digital output low
10 = Digital output three state
11 = Digital output high
Bit 1
DIS_DOR: DOR driver disable
0 = DOR active (default)
1 = DOR disabled (three state)
Bit 0
DIS_DCLK: DCLK driver disable
0 = DCLK active (default)
1 = DCLK disabled (three state)
______________________________________________________________________________________
19
MAX19515
Digital Output Power Management (02h)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
Data/DCLK Timing (03h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DA_BYPASS
DLY_HALF_T
DCLKTIME_2
DCLKTIME_1
DCLKTIME_0
DTIME_2
DTIME_1
DTIME_0
Bit 7
DA_BYPASS: Data aligner bypass
0 = Nominal
1 = Bypasses data aligner delay line to minimize output data latency with respect to the input clock.
Rising clock to data transition is approximately 6ns with DTIME = 000b settings (default)
Bit 6
DLY_HALF_T: Data and DCLK delayed by T/2
0 = Normal, no delay (default)
1 = Delays data and DCLK outputs by T/2
Disabled in MUX data bus mode
Bit 5, 4, 3
DCLKTIME_2, DCLKTIME_1, DCLKTIME_0: DCLK timing adjust (controls both channels)
000 = Nominal (default)
001 = +T/16
010 = +2T/16
011 = +3T/16
100 = Reserved, do not use
101 = -1T/16
110 = -2T/16
111 = -3T/16
Bit 2, 1, 0
DTIME_2, DTIME_1, DTIME_0: Data timing adjust (controls both channels)
000 = Nominal (default)
001 = +T/16
010 = +2T/16
011 = +3T/16
100 = Reserved, do not use
101 = -1T/16
110 = -2T/16
111 = -3T/16
20
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
CT_DCLK_2_A
CT_DCLK_1_A
CT_DCLK_0_A
CT_DATA_2_A
CT_DATA_1_A
CT_DATA_0_A
Bit 7, 6
Don’t care
Bit 5, 4, 3
CT_DCLK_2_A, CT_DCLK_1_A, CT_DCLK_0_A: CHA DCLK termination control
000 = 50Ω (default)
001 = 75Ω
010 = 100Ω
011 = 150Ω
1xx = 300Ω
Bit 2, 1, 0
CT_DATA_2_A, CT_DATA_1_A, CT_DATA_0_A: CHA data output termination control
000 = 50Ω (default)
001 = 75Ω
010 = 100Ω
011 = 150Ω
1xx = 300Ω
CHB Data Output Termination Control (05h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
X
X
CT_DCLK_2_B
CT_DCLK_1_B
CT_DCLK_0_B
CT_DATA_2_B
CT_DATA_1_B
CT_DATA_0_B
Bit 7, 6
Don’t care
Bit 5, 4, 3
CT_DCLK_2_B, CT_DCLK_1_B, CT_DCLK_0_B: CHB DCLK termination control
000 = 50Ω (default)
001 = 75Ω
010 = 100Ω
011 = 150Ω
1xx = 300Ω
Bit 2, 1, 0
CT_DATA_2_B, CT_DATA_1_B, CT_DATA_0_B: CHB data output termination control
000 = 50Ω (default)
001 = 75Ω
010 = 100Ω
011 = 150Ω
1xx = 300Ω
______________________________________________________________________________________
21
MAX19515
CHA Data Output Termination Control (04h)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
Clock Divide/Data Format/Test Pattern (06h)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TEST_PATTERN
TEST_DATA
FORMAT_1
FORMAT_0
TERM_100
SYNC_MODE
DIV1
DIV0
Bit 7
TEST_PATTERN: Test pattern selection
0 = Ramps from 0 to 1023 (offset binary) and repeats (subsequent formatting applied) (default)
1 = Data alternates between D[9:0] = 0101010101, DOR = 1, and D[9:0] = 1010101010,
DOR = 0 on both channels
Bit 6
TEST_DATA: Data test mode
0 = Normal data output (default)
1 = Outputs test data pattern
Bit 5, 4
FORMAT_1, FORMAT_0: Data numerical format
00 = Two’s complement (default)
01 = Offset binary
10 = Gray code
11 = Two’s complement
Bit 3
TERM_100: Select 100Ω clock input termination
0 = No termination (default)
1 = 100Ω termination across differential clock inputs
Bit 2
SYNC_MODE: Divider synchronization mode select
0 = Slip mode (Figure 11) (default)
1 = Edge mode (Figure 12)
Bit 1, 0
DIV1, DIV0: Input clock-divider select
00 = No divider (default)
01 = Divide-by-2
10 = Divide-by-4
11 = No divider
Reserved (07h)—Do not write to this register
22
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CMI_SELF_B
CMI_ADJ_2_B
CMI_ADJ_1_B
CMI_ADJ_0_B
CMI_SELF_A
CMI_ADJ_2_A
CMI_ADJ_1_A
CMI_ADJ_0_A
Bit 7
CMI_SELF_B: CHB connect input common-mode to analog inputs
0 = Internal common-mode voltage is NOT applied to inputs (default)
1 = Internal common-mode voltage applied to analog inputs through 2kΩ resistors
Bit 6, 5, 4
CMI_ADJ_2_B, CMI_ADJ_1_B, CMI_ADJ_0_B: CHB input common-mode voltage adjustment
000 = 0.900V (default)
001 = 1.050V
010 = 1.200V
011 = 1.350V
100 = 0.900V
101 = 0.750V
110 = 0.600V
111 = 0.450V
Bit 3
Bit 2, 1, 0
CMI_SELF_A: CHA connect input common-mode to analog inputs
0 = Internal common-mode voltage is NOT applied to inputs (default)
1 = Internal common-mode voltage applied to analog inputs through 2kΩ resistors
CMI_ADJ_2_A, CMI_ADJ_1_A, CMI_ADJ_0_A: CHA input common-mode adjustment
000 = 0.900V (default)
001 = 1.050V
010 = 1.200V
011 = 1.350V
100 = 0.900V
101 = 0.750V
110 = 0.600V
111 = 0.450V
Software Reset (0Ah)
Bit 7–0
SWRESET: Write 5Ah to initiate software reset
______________________________________________________________________________________
23
MAX19515
Common Mode (08h)
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
Clock Inputs
100Ω
TERMINATION
(PROGRAMMABLE)
CLK+
The input clock interface provides for flexibility in the
requirements of the clock driver. The MAX19515
accepts a fully differential clock or single-ended logiclevel clock. For differential clock operation, connect a
differential clock to the CLK+ and CLK- inputs. In this
mode, the input common mode is established internally
to allow for AC-coupling. The differential clock signal
can also be DC-coupled if the common mode is constrained to the specified 1V to 1.4V clock input common-mode range. For single-ended operation, connect
CLK- to GND and drive the CLK+ input with a logiclevel signal. When the CLK- input is grounded (or
pulled below the threshold of the clock mode detection
comparator) the differential-to-single-ended conversion
stage is disabled and the logic-level inverter path is
activated.
2:1 MUX
AVDD
5kΩ
50Ω
10kΩ
20kΩ
50Ω
SELECT
THRESHOLD
5kΩ
GND
CLK-
SELF-BIAS TURNED OFF FOR
SINGLE-ENDED CLOCK
OR POWER-DOWN.
Clock Divider
The MAX19515 offers a clock-divider option. Enable
clock division either by setting DIV0 and DIV1 through
the serial interface; see the Clock Divide/Data
Figure 8. Simplified Clock Input Schematic
DUAL-BUS OUTPUT MODE
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
tAD
SAMPLING
INSTANT
SAMPLING
INSTANT
IN_
SAMPLING
INSTANT
tCLK
SAMPLE ON RISING EDGE
n
tCL
tCH
n+1
n+2
n+4
n+3
n+5
SAMPLE CLOCK
tDD
DATA, DOR
n-10
n-9
tDC
n-8
n-7
n-6
n-5
tHOLD
tSETUP
DCLK
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
Figure 9. Dual-Bus Output Mode Timing
24
______________________________________________________________________________________
n-4
Dual-Channel, 10-Bit, 65Msps ADC
MAX19515
MUX OUTPUT MODE
SAMPLING
INSTANT
tAD
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
SAMPLING
INSTANT
IN_
tCLK
SAMPLE ON RISING EDGE
n
tCL
tCH
n+1
n+2
n+3
n+4
n+5
SAMPLE CLOCK
tCHA
tDD
DATA, DOR
tCHB
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
CHA
CHB
n-10
n-9
n-9
n-8
n-8
n-7
n-7
n-6
n-6
n-5
n-5
n-4
n-4
tDC
tHOLD
tDCH
tDCL
tSETUP
tHOLD
tSETUP
DCLK
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
MUX_CH (BIT 2, OUTPUT FORMAT 01h) DETERMINES THE OUTPUT BUS AND WHICH CHANNEL DATA IS PRESENTED.
Figure 10. Multiplexed Output Mode Timing
Format/Test Pattern register (06h) for clock-divider
options, or in parallel programming configuration (SPEN
= 1) by using the DIV input.
System Timing Requirements
Figures 9 and 10 depict the relationship between the
clock input and output, analog input, sampling event,
and data output. The MAX19515 samples on the rising
edge of the sampling clock. Output data is valid on the
next rising edge of DCLK after a nine-clock internal
latency. For applications where the clock is divided, the
sample clock is the divided internal clock derived from:
[(CLK+ - CLK-)/DIVIDER]
Synchronization
When using the clock divider, the phase of the internal
clock can be different than that of the FPGA, microcontroller, or other MAX19515s in the system. There are
two mechanisms to synchronize the internal clock: slip
synchronization and edge synchronization. Select the
synchronization mode using SYNC_MODE (bit 2) in the
Clock Divide/Data Format/Test Pattern register (06h)
and drive the SYNC input high to synchronize.
Slip Synchronization Mode, SYNC_MODE = 0
(default): On the third rising edge of the input clock
(CLK) after the rising edge of SYNC (provided set-up
and hold times are met), the divided output is forced to
skip a state transition (Figure 11).
Edge Synchronization Mode, SYNC_MODE = 1: On
the third rising edge of the input clock (CLK) after the
rising edge of SYNC (provided set-up and hold times
are met), the divided output is forced to state 0. A divided clock rising edge occurs on the fourth (/2 mode) or
fifth (/4 mode) rising edge of CLK, after a valid rising
edge of SYNC (Figure 12).
______________________________________________________________________________________
25
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
tHO
DIVIDE-BY-2 SLIP SYNCRONIZATION
tSUV
tSUV = SET-UP TIME FOR VALID CLOCK EDGE.
tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
SYNC
1
2
3
4
2x INPUT CLK
SLIP
(0)
(1)
(0)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
1x DIVIDED CLK
(STATE)
tHO
tSUV
DIVIDE-BY-4 SLIP SYNCHRONIZATION
SYNC
1
2
3
5
4
4x INPUT CLK
SLIP
(0)
(1)
(2)
(3)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(1)
(2)
(3)
(0)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(2)
(3)
(0)
(1)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(3)
(0)
(1)
(2)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
1x DIVIDED CLK
(STATE)
Figure 11. Slip Synchronization Mode
26
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
MAX19515
tHO
DIVIDE-BY-2 EDGE SYNCRONIZATION
tSUV
tSUV = SET-UP TIME FOR VALID CLOCK EDGE.
tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
SYNC
1
2
3
4
2x INPUT CLK
FORCE TO 0
(0)
(1)
(0)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
(0)
(1)
1x DIVIDED CLK
(STATE)
tHO
tSUV
DIVIDE-BY-4 EDGE SYNCHRONIZATION
SYNC
1
2
3
4
5
4x INPUT CLK
FORCE TO 0
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(1)
(2)
(3)
(0)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(3)
(0)
(1)
(2)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
1x DIVIDED CLK
(STATE)
Figure 12. Edge Synchronization Mode
______________________________________________________________________________________
27
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
Table 4. Data Timing Controls
DATA TIMING CONTROL
DESCRIPTION
DA_BYPASS
Data aligner bypass. When this control is active (high), data and DCLK delay is reduced by
approximately 3.4ns (relative to DA_BYPASS = 0).
DLY_HALF_T
When this control is active, data output is delayed by half clock period (T/2). This control does not
delay data output if MUX mode is active.
DTIME<2:0>
Allows adjustment of data output delay in T/16 increments, where T is the sample clock period.
Provides adjustment of DCLK delay in T/16 increments, where T is the sample clock period. When
DTIME and DCLKTIME are adjusted to the same setting, the rising edge of DCLK occurs T/8 prior
to data transitions.
DCLKTIME<2:0>
Table 5. Data Timing Control Default
Settings
DATA TIMING
CONTROL
DEFAULT
DA_BYPASS
1
Data aligner disabled
DLY_HALF_T
0
No delay
DTIME<2:0>
000
No delay
DCLKTIME<2:0>
000
No delay
DESCRIPTION
Digital Outputs
The MAX19515 features a dual CMOS, multiplexable,
reversible data bus. In parallel programming mode,
configure the data outputs (D0_–D9_) for offset binary,
two’s complement, or gray code using the FORMAT
input. Select multiplexed or dual-bus operation using the
OUTSEL input. See the Output Format register (01h) for
details on output formatting using the SPI interface. The
SPI interface offers additional flexibility where D0_–D9_
are reversed, so the LSB appears at D9_ and the MSB
at D0_. OVDD sets the output voltage; set OVDD
between 1.8V and 3.3V. The digital outputs feature programmable output impedance from 50Ω to 300Ω. Set
the output impedance for each bus using the CH_ Data
Output Termination Control registers (04h and 05h).
Programmable Data Timing
The MAX19515 provides programmable data timing control to allow for optimization of timing characteristics to
meet the system timing requirements. The timing adjustment feature also allows for ADC performance improvements by shifting the data output transition away from
the sampling instant. The data timing control signals are
summarized in Table 4. The default settings for timing
adjustment controls are given in Table 5. Many applications will not require adjustment from the default settings.
The effects of the data timing adjustment settings are
illustrated in Figures 13 and 14. The x axis is sampling
rate and the y axis is data delay in units of clock period.
28
The solid lines are the nominal data timing characteristics for the 14 available states of DTIME and
DLY_HALF_T. The heavy line represents the nominal
data timing characteristics for the default settings. Note
that the default timing adjustment setting for the
MAX19515 65Msps ADC results in an additional period
of data latency.
Tables 6 and 7 show the recommended timing control
settings versus sampling rate.
The nominal data timing characteristics versus sampling rate for these recommended timing adjustment
settings are shown in Figures 15 and 16.
When DA_BYPASS = 1, the DCLKTIME delay setting
must be equal to or less than the DTIME delay setting,
as shown in Table 8.
Power Management
The SHDN input (pin 7) toggles between any two powermanagement states. The Power Management register
(00h) defines each power-management state. In default
state, SHDN = 1 shuts down the MAX19515 and SHDN
= 0 returns to full power. Use of the SHDN input is not
required for power management. For either state of
SHDN, complete power-management flexibility is provided, including individual ADC channel power-management control, through the Power Management register
(00h). The available reduced-power modes are shutdown and standby. In standby mode, the reference and
duty-cycle equalizer circuits remain active for rapid
wake-up time. In standby mode, the externally applied
clock signal must remain active for the duty-cycle equalizer to remain locked. Typical wake-up time from standby mode is 15µs. In shutdown mode, all circuits are
turned off except for the reference circuit required for the
integrated self-sensing voltage regulator. If the regulator
is active, there is additional supply current associated
with the regulator circuit when the device is in shutdown.
Typical wake-up time from shutdown mode is 5ms,
which is dominated by the RC time constant on REFIO.
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
1.5
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
1.0
0.5
MAX19515 fig15
2.0
VOVDD = 1.8V
DA_BYPASS = 1
DATA DELAY (T FRACTIONAL PERIOD)
DATA DELAY (T FRACTIONAL PERIOD)
RECOMMENDED DATA TIMING
vs. SAMPLE RATE
MAX19515 fig13
2.0
+10/16
+8/16
+6/16
+2/16
0
-2/16
0
VOVDD = 1.8V
DA_BYPASS = 1
1.5
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
1.0
0.5
+10/16
+8/16
+6/16
+2/16
0
-2/16
0
30
40
50
60
30
40
SAMPLING RATE (Msps)
RECOMMENDED DATA TIMING
vs. SAMPLE RATE
MAX19515 fig14
DATA DELAY (T FRACTIONAL PERIOD)
1.5
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
1.0
0.5
+10/16
+8/16
+6/16
+2/16
0
-2/16
0
40
50
MAX19515 fig16
2.0
VOVDD = 3.3V
DA_BYPASS = 1
30
60
Figure 15. Recommended Data Timing (VOVDD = 1.8V)
FACTORY-DEFAULT NOMINAL DATA
TIMING vs. SAMPLE RATE
2.0
50
SAMPLING RATE (Msps)
Figure 13. Default Data Timing (VOVDD = 1.8V)
DATA DELAY (T FRACTIONAL PERIOD)
MAX19515
FACTORY-DEFAULT NOMINAL DATA
TIMING vs. SAMPLE RATE
VOVDD = 3.3V
DA_BYPASS = 1
1.5
1.0
+11/16
+9/16
+7/16
+5/16
+3/16
+1/16
-1/16
-3/16
0.5
0
60
30
40
SAMPLING RATE (Msps)
50
+10/16
+8/16
+6/16
+2/16
0
-2/16
60
SAMPLING RATE (Msps)
Figure 14. Default Data Timing (VOVDD = 3.3V)
Figure 16. Recommended Data Timing (VOVDD = 3.3V)
Table 6. Recommended Timing Adjustments (VOVDD = 1.8V)
SAMPLING RATE (Msps)
VOVDD = 1.8V
FROM
TO
DA_BYPASS
DLY_HALF_T
DTIME<2:0>
DCLKTIME<2:0>
30
56
1
0
000
000
56
65
1
0
101
101
______________________________________________________________________________________
29
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
Table 7. Recommended Timing Adjustments (VOVDD = 3.3V)
SAMPLING RATE (Msps)
VOVDD = 3.3V
FROM
TO
DA_BYPASS
DLY_HALF_T
DTIME<2:0>
DCLKTIME<2:0>
30
65
1
0
000
000
Table 8. Allowed Settings of DCLKTIME and DTIME for DA_BYPASS = 1
DTIME<2:0>
ALLOWED DCLKTIME<2:0> SETTINGS
111 (-3T/16)
111 (-3T/16)
110 (-2T/16)
110 (-2T/16); 111 (-3T/16)
101 (-1T/16)
101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
000 (nominal)
000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
001 (+1T/16)
001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
010 (+2T/16)
010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
011 (+3T/16)
011 (+3T/16); 010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16)
Table 9. Reset Methods
RESET MODE
DESCRIPTION
Upon power-up (AVDD supply voltage and clock signal applied), the POR (power-on-reset) circuit initiates a
Power-On Reset
register reset.
Software Reset
Write data 5Ah to address 0Ah to initiate register reset.
Hardware Reset A register reset is initiated by the falling edge on the SHDN pin when SPEN is high.
Integrated Voltage Regulator
Power-On and Reset
The MAX19515 includes an integrated self-sensing linear voltage regulator on the analog supply (AVDD). See
Figure 17. When the applied voltage on AVDD is below
2V, the voltage regulator is bypassed, and the core
analog circuitry operates from the externally applied
voltage. If the applied voltage on AVDD is higher than
2V, the regulator bypass switches off, and voltage regulator mode is enabled. When in voltage regulation
mode, the internal-core analog circuitry operates from a
stable 1.8V supply voltage provided by the regulator.
The regulator provides an output voltage of 1.8V over a
2.3V to 3.5V AVDD input-voltage range. Since the
power-supply current is constant over this voltage
range, analog power dissipation is proportional to the
applied voltage.
The user-programmable register default settings and
other factory-programmed settings are stored in nonvolatile memory. Upon device power-up, these values are
loaded into the control registers. This operation occurs
after application of supply voltage to AVDD and application of an input clock signal. The register values are
retained as long as AVDD is applied. While AVDD is
applied, the registers can be reset, which will overwrite all
user-programmed registers with the default values. This
reset operation can be initiated by software command
through the serial-port interface or by hardware control
using the SPEN and SHDN inputs. The reset time is proportional to the ADC clock period and requires 130µs at
65Msps. Table 9 summarizes the reset methods.
30
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
MAX19515
AVDD
(PINS 1, 12, 13, 48)
REGULATOR
IN
2.3V TO 3.5V
OUT
1.8V
ENABLE
INTERNAL
ANALOG
CIRCUITS
REFERENCE
GND
Figure 17. Integrated Voltage Regulator
Applications Information
Analog Inputs
IN_+
0.1µF
1
VIN
6
36.5Ω
0.5%
MAX19515
T1
N.C.
5
2
Transformer-Coupled Differential Analog Input
The MAX19515 provides better SFDR and THD with
fully differential input signals than a single-ended input
drive. In differential input mode, even-order harmonics
are lower as both inputs are balanced, and each of the
ADC inputs only require half the signal swing compared
to single-ended input mode.
An RF transformer (Figure 18) provides an excellent
solution for converting a single-ended signal to a fully
differential signal. Connecting the center tap of the
transformer to CM_ provides a common-mode voltage.
The transformer shown has an impedance ratio of 1:1.4.
Alternatively, a different step-up transformer can be
selected to reduce the drive requirements. A reduced
signal swing from the input driver can also improve the
overall distortion. The configuration of Figure 18 is good
for frequencies up to Nyquist (fCLK/2).
CM_
N.C.
0.1µF
3
4
MINI-CIRCUITS 36.5Ω
0.5%
ADT1-1WT
IN_-
Figure 18. Transformer-Coupled Input Drive for Input
Frequencies Up to Nyquist
IN_+
0.1µF
1
VIN
N.C.
5
T1
6
2
1
75Ω
0.5%
N.C.
N.C.
5
T2
110Ω
0.5%
6
MAX19515
2
CM_
N.C.
0.1µF
3
4
MINI-CIRCUITS
ADT1-1WT
75Ω
0.5%
3
4
MINI-CIRCUITS
ADT1-1WT
110Ω
0.5%
IN_-
Figure 19. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
______________________________________________________________________________________
31
MAX19515
Dual-Channel, 10-Bit, 65Msps ADC
VIN
0.1µF
0.01µF
IN_+
MAX4108
CLK+
0.1µF
CLKIN
100Ω
49.9Ω
MAX19515
MAX19515
CM_
100Ω
0.1µF
49.9Ω
0.01µF
CLK-
IN_0.1µF
Figure 20. Single-Ended, AC-Coupled Input Drive
Figure 21. Single-Ended-to-Differential Clock Input
The circuit of Figure 19 also converts a single-ended
input signal to a fully differential signal. Figure 19 utilizes an additional transformer to improve the commonmode rejection allowing high-frequency signals beyond
the Nyquist frequency. A set of 75Ω and 110Ω termination resistors provide an equivalent 50Ω termination to
the signal source. The second set of termination resistors connect to CM_ providing the correct input common-mode voltage.
duce the highest level of signal integrity. Route highspeed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the
analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines
short and free of 90° turns.
Single-Ended AC-Coupled Input Signal
Figure 20 shows a single-ended, AC-coupled input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity. Bias voltage is applied to the
inputs through internal 2kΩ resistors. See Common
Mode register 08h for further details.
INL is the deviation of the measured transfer function
from a best-fit straight line. Worst-case deviation is
defined as INL.
DC-Coupled Input
The MAX19515’s wide common-mode voltage range
(0.4V to 1.4V) allows DC-coupled signals. Ensure that the
common-mode voltage remains between 0.4V and 1.4V.
Definitions
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
DNL is the difference between the measured transfer
function step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. DNL
deviations are measured at each step of the transfer
function and the worst-case deviation is defined as DNL.
Offset Error
Grounding, Bypassing, and
Board-Layout Considerations
Offset error is a parameter that indicates how well the
actual transfer function matches the ideal transfer function at midscale. Ideally, the midscale transition occurs
at 0.5 LSB above midscale. The offset error is the
amount of deviation between the measured midscale
transition point and the ideal midscale transition point.
The MAX19515 requires high-speed board-layout
design techniques. Locate all bypass capacitors as
close as possible to the device, preferably on the same
side as the ADC, using surface-mount devices for minimum inductance. Bypass AVDD, OVDD, REFIO, CMA,
and CMB with 0.1µF ceramic capacitors to GND.
Multilayer boards with ground and power planes pro-
Gain error is a figure of merit that indicates how well the
slope of the measured transfer function matches the
slope of the ideal transfer function based on the specified full-scale input-voltage range. The gain error is
defined as the relative error of the measured transfer
function and is expressed as a percentage.
Clock Input
Figure 21 shows a single-ended-to-differential clock
input converting circuit.
32
Gain Error
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
Single-Tone Spurious-Free Dynamic Range
(SFDR1 and SFDR2)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next largest spurious
component, excluding DC offset. SFDR1 reflects the
spurious performance based on worst 2nd-order or
3rd-order harmonic distortion. SFDR2 is defined by the
worst spurious component excluding 2nd- and 3rdorder harmonics and DC offset.
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits):
SNR[max] = 6.02 x N + 1.76
THD is the ratio of the RMS of the first six harmonics of
the input signal to the fundamental itself. This is
expressed as:
In reality, there are other noise sources besides quantization noise (e.g., thermal noise, reference noise, clock
jitter, etc.). SNR is computed by taking the ratio of the
RMS signal to the RMS noise. RMS noise includes all
spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2–HD7),
and the DC offset.
⎛ SIGNALRMS ⎞
SNR = 20 × log ⎜
⎟
⎝ NOISERMS ⎠
⎞
⎟
⎟
⎠
where V1 is the fundamental amplitude and V2–V7 are
the amplitudes of the 2nd-order through 7th-order harmonics (HD2–HD7).
Third-Order Intermodulation (IM3)
IM3 is the total power of the third-order intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones fIN1 and fIN2. The
individual input tone levels are at -7dBFS. The thirdorder intermodulation products are: 2 x fIN1 - fIN2, 2 x
fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1.
Aperture Delay
Signal-to-Noise and Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS
noise includes all spectral components to the Nyquist
frequency excluding the fundamental, the first six harmonics (HD2–HD7), and the DC offset. RMS distortion
includes the first six harmonics (HD2–HD7).
⎛
SIGNALRMS
SINAD = 20 × log ⎜
⎜
2
2
⎝ NOISERMS + DISTORTIONRMS
⎛
V22 + V32 + V4 2 + V52 + V62 + V72
THD = 20 × log ⎜
⎜
V1
⎝
⎞
⎟
⎟
⎠
The input signal is sampled on the rising edge of the
sampling clock. There is a small delay between the rising edge of the sampling clock and the actual sampling
instant, which is defined as aperture delay (tAD).
Aperture Jitter
Aperture jitter (tAJ) is defined as the sample-to-sample
time variation in the aperture delay.
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The specified overdrive recovery time is
measured with an input transient that exceeds the fullscale limits by ±10%.
Chip Information
PROCESS: CMOS
______________________________________________________________________________________
33
MAX19515
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter, a
small signal is defined as a single tone with an amplitude
less than -35dBFS. This parameter captures the thermal
and quantization noise characteristics of the converter
and can be used to help calculate the overall noise figure
of a receive channel. Refer to www.maxim-ic.com for
application notes on Thermal + Quantization Noise Floor.
Dual-Channel, 10-Bit, 65Msps ADC
OVDD
D4B
D5B
D6B
D7B
D8B
D9B
D0A
D1A
D2A
OVDD
TOP VIEW
D3A
MAX19515
Pin Configuration
36 35 34 33 32 31 30 29 28 27 26 25
D4A
37
24
D3B
D5A
38
23
D2B
D6A
39
22
D1B
D7A
40
21
D0B
D8A
41
20
DCLKB
19
DORB
18
GND
D9A
42
DORA
43
DCLKA
44
17
GND
SDIN/FORMAT
45
16
CLK-
SCLK/DIV
46
15
CLK+
14
SYNC
13
AVDD
3
4
5
6
7
8
9
10 11 12
SPEN
REFIO
SHDN
I.C.
INB+
INB-
CMB
2
AVDD
1
INA-
48
INA+
AVDD
CMA
47
*EP
+
AVDD
CS/OUTSEL
MAX19515
*EXPOSED PAD
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
34
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND
PATTERN NO.
48 TQFN-EP
T4877+4
21-0144
90-0130
______________________________________________________________________________________
Dual-Channel, 10-Bit, 65Msps ADC
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0
7/08
Initial release
—
1
10/08
Corrected error in vertical scale for TOC32
11
2
9/10
Updated timing characteristics due to CMOS output driver changes
3
1/11
Added automotive qualified part to Ordering Information
5, 6, 28, 29, 30
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX19515
Revision History