HYNIX HMP351U7AFR8C-S5

240pin DDR2 SDRAM Unbuffered DIMMs based on 2Gb A version
This Hynix unbuffered Dual In-Line Memory Module (DIMM) series consists of 2Gb A version DDR2
SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 2Gb
version A based DDR2 Unbuffered DIMM series provide a high performance 8 byte interface in 133.35mm
width form factor of industry standard. It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2
Synchronous DRAMs (DDR2 SDRAMs) with
•
Fully differential clock operations (CK & CK)
•
Programmable Burst Length 4 / 8 with both
1.8V +/- 0.1V Power Supply
•
sequential and interleave mode
All inputs and outputs are compatible with
•
Auto refresh and self refresh supported
•
8192 refresh cycles / 64ms
•
Serial presence detect with EEPROM
•
DDR2 SDRAM Package:
SSTL_1.8 interface
•
8 Bank architecture
•
Posted CAS
•
Programmable CAS Latency 3,4,5, 6
•
OCD (Off-Chip Driver Impedance Adjustment)
•
ODT (On-Die Termination)
60ball FBGA(256Mx8)
•
133.35 x 30.00 mm form factor
•
RoHS compliant
Density
Org.
# of
DRAM
s
# of
ranks
Materials
ECC
HMP351U6AFR8C - Y5/S5/S6
4GB
512Mx64
16
2
Halogen-free
None
HMP351U7AFR8C - Y5/S5/S6
4GB
512Mx72
18
2
Halogen-free
ECC
ORDERING INFORMATION
Part Name
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Mar 2009
1
1240pin DDR2 SDRAM Unbuffered DIMMs
SPEED GRADE & KEY PARAMETERS
Y5
(DDR2-667)
S6
(DDR2-800)
S5
(DDR2-800)
Unit
Speed @CL3
400
400
400
Mbps
Speed @CL4
533
533
533
Mbps
Speed @CL5
667
800
800
Mbps
Speed @CL6
-
800
800
Mbps
CL-tRCD-tRP
5-5-5
6-6-6
5-5-5
tCK
ADDRESS TABLE
Density
Organization Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
4GB
512M x 64
2
256Mb x 8
16
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
4GB
512M x 72
2
256Mb x 8
18
14(A0~A13)/3(BA0~BA2)/10(A0~A9)
8K / 64ms
Rev. 0.1 / Mar 2009
2
1240pin DDR2 SDRAM Unbuffered DIMMs
Input/Output Functional Description
Symbol
CK[2:0], CK[2:0]
CKE[1:0]
Type
SSTL
SSTL
Polarity
Differential
Crossing
Active High
Pin Description
CK and /CK are differential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of /CK. Output(read) data
is reference to the crossing of CK and /CK (Both directions of crossing)
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when
low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self
Refresh mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the
S[1:0]
SSTL
Active Low
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is
selected by S1
RAS, CAS,
SSTL
Active Low
ODT[1:0]
SSTL
Active High
Vref
Supply
SDRAM mode register.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immu-
VDDQ
Supply
nity. For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane
BA[2:0]
SSTL
WE
/RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
as VDD pins.
-
Selects which DDR2 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, Address input defines the row
address(RA0~RA15)
During a Read or Write command cycle, Address input defines the column address when
sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to
A[9:0], A10/AP,
A[13:11]
SSTL
-
the column address, AP is used to invoke autoprecharge operation at the end of the
burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines
the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge
command cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to
precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BAn
inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.
DQ[63:0],
CB[7:0]
SSTL
-
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled
DM[8:0]
VDD,VSS
DQS[8:0],
DQS[8:0]
SSTL
Active High
pins are tied to VDD/VDDQ planes on these modules.
Differential
crossing
SA[2:0]
-
SDA
-
SCL
-
VDDSPD
Supply
Rev. 0.1 / Mar 2009
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS
loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic. VDD and VDDQ
Supply
SSTL
High coincident with that input data during a write access. DM is sampled on both edges
Data strobe for input and output data. For Rawcards using x16 organized DRAMs,
DQ0~7 connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of
the DRAM
These signals are tied at the system planar to either VSS or VDD to configure the serial
SPD EEPROM.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A
resister must be connected to VDD to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from SCL to VDD to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power
plane. EEPROM supply is operable from 1.7V to 3.6V.
3
1240pin DDR2 SDRAM Unbuffered DIMMs
PIN CONFIGURATION
Front Side
1 pin
64 pin 65 pin
121 pin
184 pin 185 pin
120 pin
240 pin
Back Side
PIN ASSIGNMENT
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
41
VSS
81
DQ33
121
VSS
161
NC(CB4)*
201
VSS
2
VSS
42
NC(CB0)*
82
VSS
122
DQ4
162
NC(CB5)*
202
DM4
3
DQ0
43
NC(CB1)*
83
DQS4
123
DQ5
163
VSS
203
NC
4
DQ1
44
VSS
84
DQS4
124
VSS
164
NC(DM8)*
204
VSS
5
VSS
45
NC(DQS8)*
85
VSS
125
DM0
165
NC
205
DQ38
6
DQS0
46
NC(DQS8)*
86
DQ34
126
NC
166
VSS
206
DQ39
7
DQS0
47
VSS
87
DQ35
127
VSS
167
NC(CB6)*
207
VSS
8
VSS
48
NC(CB2)*
88
VSS
128
DQ6
168
NC(CB7)*
208
DQ44
9
DQ2
49
NC(CB3)*
89
DQ40
129
DQ7
169
VSS
209
DQ45
10
DQ3
50
VSS
90
DQ41
130
VSS
170
VDDQ
210
VSS
11
VSS
51
VDDQ
91
VSS
131
DQ12
171
CKE1
211
DM5
12
DQ8
52
CKE0
92
DQS5
132
DQ13
172
VDD
212
NC
13
DQ9
53
VDD
93
DQS5
133
VSS
173
A15
213
VSS
14
VSS
54
BA2
94
VSS
134
DM1
174
A14
214
DQ46
15
DQS1
55
NC
95
DQ42
135
NC
175
VDDQ
215
DQ47
16
DQS1
56
VDDQ
96
DQ43
136
VSS
176
A12
216
VSS
17
VSS
57
A11
97
VSS
137
CK1
177
A9
217
DQ52
18
NC
58
A7
98
DQ48
138
CK1
178
VDD
218
DQ53
19
NC
59
VDD
99
DQ49
139
VSS
179
A8
219
VSS
20
VSS
60
A5
100
VSS
140
DQ14
180
A6
220
CK2
21
DQ10
61
A4
101
SA2
141
DQ15
181
VDDQ
221
CK2
22
DQ11
62
VDDQ
102
NC,TEST1
142
VSS
182
A3
222
VSS
* The pin names in parenthesizes are applied to DIMM with ECC only.
Rev. 0.1 / Mar 2009
4
PIN ASSIGNMENT(Continued)
Pin
Name
Pin
Name
Pin
Name
Pin
Name
23
VSS
24
DQ16
63
A2
64
VDD
25
DQ17
65
26
VSS
Pin
103
VSS
143
DQ20
183
104
DQS6
144
DQ21
184
VSS
105
DQS6
145
VSS
185
66
VSS
106
VSS
146
DM2
Name
Pin
Name
A1
223
DM6
VDD
224
NC
CK0
225
VSS
186
CK0
226
DQ54
27
DQS2
67
VDD
107
DQ50
147
NC
187
VDD
227
DQ55
28
DQS2
68
NC
108
DQ51
148
VSS
188
A0
228
VSS
29
VSS
69
VDD
109
VSS
149
DQ22
189
VDD
229
DQ60
30
DQ18
70
A10/AP
110
DQ56
150
DQ23
190
BA1
230
DQ61
31
DQ19
71
BA0
111
DQ57
151
VSS
191
VDDQ
231
VSS
32
VSS
72
VDDQ
112
VSS
152
DQ28
192
RAS
232
DM7
33
DQ24
73
WE
113
DQS7
153
DQ29
193
S0
233
NC
34
DQ25
74
CAS
114
DQS7
154
VSS
194
VDDQ
234
VSS
35
VSS
75
VDDQ
115
VSS
155
DM3
195
ODT0
235
DQ62
36
DQS3
76
S1
116
DQ58
156
NC
196
A13
236
DQ63
37
DQS3
77
ODT1
117
DQ59
157
VSS
197
VDD
237
VSS
38
VSS
78
VDDQ
118
VSS
158
DQ30
198
VSS
238
VDDSPD
39
DQ26
79
VSS
119
SDA
159
DQ31
199
DQ36
239
SA0
40
DQ27
80
DQ32
120
SCL
160
VSS
200
DQ37
240
SA1
*NC=No connect
Notes:
1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory
module products (DIMMs).
2. NC Pins should not be connected to anything, including bussing within the NC group.
1240pin DDR2 SDRAM Unbuffered DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx64) - HMP351U6AFR8C
/S1
/S0
/ DQS0
DQS0
/ DQS4
DQS4
DM0
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/CS
DQS /DQS
/
I/ O 0
I/ O 3
/CS
DM
DQS /DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/ O 0
I/ O 1
I/ O 2
DM
I/ O 1
D0
I/ O 2
D8
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS1
DQS1
DQS /DQS
/CS
DM
I/ O 0
I/ O 0
I/ O 1
I/ O 1
I/ O 2
/CS
DQS /DQS
I/ O 2
D4
I/ O 3
D12
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS5
DQS5
DM1
DM5
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CS
I/ O 0
I/ O 3
/CS
DQS /DQS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/ O 0
I/ O 1
I/ O 2
DM
DQS /DQS
I/ O 1
D1
I/ O 2
D9
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS2
DQS2
/CS
DQS /DQS
DM
/CS
DQS /DQS
I/ O 0
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D5
I/ O 3
D13
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS6
DQS6
DM2
DM6
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/CS
DM
DQS /DQS
I/ O 0
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
I/ O 3
D2
/CS
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D10
I/ O 3
I/ O 4
DM
DQS /DQS
/ DQS3
/ DQS7
DQS3
DQS7
DM3
DM7
I/ O 0
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
I/ O 1
I/ O 1
I/ O 2
I/ O 2
I/ O 3
D3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
BA0-BA2
A0-A15
CKE0
CKE1
/CAS
/RAS
/WE
ODT0
ODT1
Rev. 0.1 / Mar 2009
D11
I/ O 3
SDRAMS D0-D15
SDRAMS D0-D15
SDRAMS D0-D7
SDRAMS D8-D15
SDRAMS D0-D15
SDRAMS D0-D15
SDRAMS D0-D15
SDRAMS D0-D7
SDRAMS D8-D15
SCL
SCL
WP
A0
A1
A1
SA0
SA1
SA2
VDD SPD
Serial
PD
VDD /V DDQ
DO-D15
VREF
DO-D15
VSS
DO-D15
DM
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 3
/CS
DQS /DQS
I/ O 2
D7
D15
I/ O 3
I/ O 4
SDA
Serial PD
DQS /DQS
I/ O 0
DQS /DQS
D14
I/ O 3
I/ O 4
/CS
/CS
I/ O 2
D6
I/ O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/ O 0
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS /DQS
/CS
I/ O 0
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
Clock Signal Loads
Clock Input
SDRAMs
CK0, /CK0
4
CK1, /CK1
6
CK2, /CK2
6
Notes:
1. DQ,DM,DQS,/DQS resistors : 22 Ω +/- 5 %.
2. Bax,Ax,/RAS,/CAS,/WE resistors : 7.5 Ω +/- 5 %.
6
1240pin DDR2 SDRAM Unbuffered DIMMs
FUNCTIONAL BLOCK DIAGRAM
4GB(512Mbx72) - HMP351U7AFR8C
/S1
/S0
/ DQS0
DQS0
/ DQS4
D QS4
DM0
DM4
DM
D Q0
D Q1
D Q2
D Q3
D Q4
D Q5
D Q6
DQ7
/ CS
DM
DQ S / DQ S
I/ O 0
/ CS
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
D Q 39
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D0
I/ O 3
D9
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DM
DQ S / DQ S
/ DQS1
DQS1
/ CS
DM
DQ S / DQ S
/ CS
DQ S / DQ S
I/ O 0
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D4
I/ O 3
D13
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS5
D QS5
DM1
DM5
DM
D Q8
D Q9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
/ CS
DM
DQ S / DQ S
I/ O 0
/ CS
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
D Q 47
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D1
I/ O 3
D10
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DM
DQ S / DQ S
/ DQS2
/ CS
DM
DQ S / DQ S
I/ O 0
/ CS
DQ S / DQ S
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D5
I/ O 3
D14
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS6
DQS6
DQS2
DM2
D M6
/ CS
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DM
DQ S / DQ S
I/ O 0
/ CS
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D2
I/ O 3
D 11
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DM
DQ S / DQ S
/ DQS3
/ CS
DM
DQ S / DQ S
I/ O 0
/ CS
DQ S / DQ S
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D6
I/ O 3
D15
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS7
D QS7
DQS3
DM3
DM7
DM
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
/ CS
DM
DQ S / DQ S
I/ O 0
/ CS
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
D Q 63
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 2
D3
I/ O 3
D12
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
DM
DQ S / DQ S
/ CS
DM
DQ S / DQ S
I/ O 0
I/ O 0
I/ O 1
I/ O 1
I/ O 2
DQ S / DQ S
I/ O 2
D7
I/ O 3
/ CS
I/ O 3
D 16
I/ O 4
I/ O 4
I/ O 5
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
/ DQS8
DQS8
DM8
DM
C B0
C B1
C B2
C B3
C B4
C B5
C B6
CB7
/ CS
DM
DQ S / DQ S
I/ O 0
I/ O 0
I/ O 1
I/ O 1
I/ O 2
I/ O 3
I/ O 3
I/ O 5
I/ O 6
I/ O 7
I/ O 6
I/ O 7
Rev. 0.1 / Mar 2009
V DD SP D
Serial
PD
V D D /V D D Q
DO-D 17
Clock Signal Loads
D 17
Clock Input
SD RAM s
CK0, /C K0
6
V R EF
DO-D 17
CK1, /C K1
6
VSS
DO-D 17
CK2, /C K2
6
I/ O 4
I/ O 5
/W E
ODT0
ODT1
DQ S / DQ S
I/ O 2
D8
I/ O 4
BA0-BA2
A0-A13
CKE0
CKE1
/CAS
/RAS
/ CS
SDR AM S D0-D 17
SD RAM S D0-D17
SDR AM S D 0-D 8
SDR AM S D9-D 17
SD RAM S D0-D17
SDR AM S D0-D 17
SDR AM S D0-D 17
SD RAM S D 0-D8
SD RAM S D9-D17
SCL
SCL
WP
SDA
Serial P D
A0
A1
A1
S A0
SA1
S A2
Notes:
1. DQ ,DM ,D Q S,/DQ S resistors : 22 Ω +/- 5 % .
2. Bax,Ax,/RAS,/CAS,/W E resistors : 7.5 Ω +/- 5 % .
7
1240pin DDR2 SDRAM Unbuffered DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Note
VDD
- 1.0 ~ 2.3
V
1
VDDQ
- 0.5 ~ 2.3
V
1
VIN, VOUT
- 0.5 ~ 2.3
V
1
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Operation Conditions and Environmental Parameters
Parameter
Symbol
TOPR
Rating
0 ~ +55
Units
oC
Notes
TSTG
-50 ~ +100
oC
1
Storage Humidity(without condensation)
HSTG
5 to 95
%
1
DIMM Barometric Pressure(operating & storage)
PBAR
105 to 69
K Pascal
2
DRAM Component Case Temperature Range
TCASE
0 ~+95
DIMM Operating temperature(ambient)
Storage Temperature
o
C
3
Notes:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating con
ditions for extended periods may affect reliability.
2. Up to 9850 ft.
3. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Symbol
Parameter
Rating
Min.
Typ.
Max.
Units
Notes
VDD
Supply Voltage
1.7
1.8
1.9
V
1
VDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
1,2
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
1,2
VREF
Input Reference Voltage
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
mV
3,4
VTT
Termination Voltage
VREF-0.04
VREF
VREF+0.04
V
5
1.7
-
3.6
V
VDDSPD
EEPROM Supply Voltage
Notes:
1. Min. Type. and Max. values increase by 100mV for C3(DDR2-533 3-3-3) speed option.
2. VDDQ tracks with VDD,VDDL tracks with VDD. AC parameters are measured with VDD,VDDQ and VDD.
3. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the
value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
4. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
5. VTT of transmitting device must track VREF of receiving device.
Rev. 0.1 / Mar 2009
8
1240pin DDR2 SDRAM Unbuffered DIMMs
INPUT DC LOGIC LEVEL
Parameter
Symbol
Min
Max
Unit
dc Input logic HIGH
VIH(DC)
VREF + 0.125
VDDQ + 0.3
V
dc Input logic LOW
VIL(DC)
-0.30
VREF - 0.125
V
Note
INPUT AC LOGIC LEVEL
DDR2 667, 800
Parameter
Symbol
Unit
Min
Max
AC Input logic High
VIH(AC)
VREF + 0.200
-
V
AC Input logic Low
VIL(AC)
-
VREF - 0.200
V
Note
AC INPUT TEST CONDITIONS
Symbol
Condition
Value
Units
Notes
0.5 * VDDQ
V
1
Input signal maximum peak to peak swing
1.0
V
1
Input signal minimum slew rate
1.0
V/ns
2, 3
VREF
Input reference voltage
VSWING(MAX)
SLEW
Notes:
1.
Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3.
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and
VIH(ac) to VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
VSWING(MAX)
delta TF
Falling Slew =
delta TR
VREF - VIL(ac) max
Rising Slew =
delta TF
VIH(ac) min - VREF
delta TR
< Figure: AC Input Test Signal Waveform >
Rev. 0.1 / Mar 2009
9
1240pin DDR2 SDRAM Unbuffered DIMMs
Differential Input AC logic Level
Symbol
Parameter
VID (ac)
ac differential input voltage
VIX (ac)
ac differential cross point voltage
Min.
Max.
Units
Note
0.5
VDDQ + 0.6
V
1
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS)
level. The minimum value is equal to VIH(DC) - VIL(DC).
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ. VIX(AC) indicates the voltage at which differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
VOX (ac)
Parameter
ac differential cross point voltage
Min.
Max.
Units
Note
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
Note:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ. VOX(AC) indicates the voltage at which differential output signals must cross.
Rev. 0.1 / Mar 2009
10
1240pin DDR2 SDRAM Unbuffered DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
VOTR
Parameter
Output Timing Measurement Reference Level
SSTL_18
Units
Notes
0.5 * VDDQ
V
1
Note:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
Parameter
IOH(dc)
Output Minimum Source DC Current
IOL(dc)
Output Minimum Sink DC Current
SSTl_18
Units
Notes
- 13.4
mA
1, 3, 4
13.4
mA
2, 3, 4
Notes:
1.VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point along a 21 ohm
load line to define a convenient driver current for measurement.
Rev. 0.1 / Mar 2009
11
1240pin DDR2 SDRAM Unbuffered DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25°C)
4GB: HMP351U6AFR8C
Pin
CK, CK
CKE, ODT, CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
Symbol
Min
Max
Unit
CCK
CI1
CI2
CIO
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
Symbol
Min
Max
Unit
CCK
CI1
CI2
CIO
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
pF
pF
pF
pF
4GB: HMP351U7AFR8C
Pin
CK, CK
CKE, ODT, CS
Address, RAS, CAS, WE
DQ, DM, DQS, DQS
pF
pF
pF
Notes:
1. Pins not under test are tied to GND.
2. These value are guaranteed by design and tested on a sample basis only.
Rev. 0.1 / Mar 2009
12
1240pin DDR2 SDRAM Unbuffered DIMMs
4GB, 512M x 64 U - DIMM: HMP351U6AFR8C
Symbol
Y5
(DDR2 [email protected] 5)
S6
(DDR2 [email protected] 6)
Unit
IDD0
1120
1200
mA
IDD1
1200
1280
mA
IDD2P
192
192
mA
IDD2Q
720
800
mA
IDD2N
800
880
mA
IDD3P(F)
560
560
mA
IDD3P(S)
288
288
mA
IDD3N
1120
1280
mA
IDD4R
2000
2360
mA
IDD4W
1880
2200
mA
IDD5B
2160
2280
mA
IDD6
240
240
mA
IDD7
2640
2880
mA
Note
1
4GB, 512M x 72 ECC U-DIMM: HMP351U7AFR8C
Symbol
Y5
(DDR2 [email protected] 5)
S6
(DDR2 [email protected] 6)
Unit
IDD0
1260
1350
mA
IDD1
1350
1440
mA
IDD2P
216
216
mA
IDD2Q
810
900
mA
IDD2N
900
990
mA
IDD3P(F)
630
630
mA
IDD3P(S)
324
324
mA
IDD3N
1260
1440
mA
IDD4R
2250
2655
mA
IDD4W
2115
2475
mA
IDD5B
2430
2565
mA
IDD6
270
270
mA
IDD7
2970
3240
mA
Note
1
Note: 1. IDD6 current values are guaranteed up to Tcase of 85°C max.
Rev. 0.1 / Mar 2009
13
1240pin DDR2 SDRAM Unbuffered DIMMs
IDD MEASUREMENT CONDITIONS
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
mA
IDD1
Operating one bank active-read-precharge current; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0; tCK =
tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
mA
IDD2P
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2Q
Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control
and address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2N
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current; All banks open; tCK = tCK(IDD);
CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
mA
Slow PDN Exit MRS(12) = 1
mA
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
mA
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK
= tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
mA
IDD5B
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING.
IDD6 current values are guaranteed up to Tcase of 85℃ max.
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE
is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data
pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
Normal
Low Power
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met
with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC (max)
HIGH is defined as Vin ≥ VIHAC (min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not
including masks or strobes.
Rev. 0.1 / Mar 2009
14
1240pin DDR2 SDRAM Unbuffered DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
DDR2-800(S5)
DDR2-667(Y5)
Bin(CL-tRCD-tRP)
5-5-5
5-5-5
Parameter
min
min
CAS Latency
5
5
ns
tRCD
12.5
15
ns
tRP
12.5
15
ns
tRC
57.5
60
ns
tRAS
45
45
ns
Rev. 0.1 / Mar 2009
Unit
15
1240pin DDR2 SDRAM Unbuffered DIMMs
AC Timing Parameters by Speed Grade
Parameter
Symbol
DDR2-667
DDR2-800
min
max
min
max
Unit Note
DQ output access time from CK/CK
tAC
-450
+450
-400
+400
DQS output access time from CK/CK
tDQSCK
-400
+400
-350
+350
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL,
tCH)
-
min(tCL,
tCH)
-
ps
Clock cycle time, CL=x
tCK
3000
8000
2500
tDS
100
-
50
-
ps
1
tDH
175
-
125
-
ps
1
Control & Address input pulse width for each
input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
tCK
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
-
240
-
200
ps
DQ hold skew factor
tQHS
-
340
-
300
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
First DQS latching transition to associated clock
edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
Write preamble
tWPRE
0.35
-
0.35
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Address and control input setup time
tIS
200
-
175
-
ps
Address and control input hold time
tIH
275
-
250
-
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Auto-Refresh to Active/Auto-Refresh command period
tRFC
127.5
-
127.5
-
ns
Active to active command period for 1KB page
size products
tRRD
7.5
-
7.5
-
ns
Active to active command period for 2KB page
size products
tRRD
10
-
10
-
ns
Four Active Window for 1KB page size products
tFAW
37.5
-
35
-
ns
Four Active Window for 2KB page size products
tFAW
50
-
45
-
ns
DQ and DM input setup time
(differential strobe)
DQ and DM input hold time
(differential strobe)
Rev. 0.1 / Mar 2009
ps
ps
16
1240pin DDR2 SDRAM Unbuffered DIMMs
- continued Parameter
Symbol
CAS to CAS command delay
tCCD
Write recovery time
tWR
Auto precharge write recovery + precharge time tDAL
DDR2-667
min
DDR2-800
max
2
min
max
2
Unit Note
tCK
15
-
15
-
ns
WR+tRP
-
WR+tRP
-
tCK
-
7.5
-
ns
Internal write to read command delay
tWTR
7.5
Internal read to precharge command delay
tRTP
7.5
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC +
10
ns
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
Exit precharge power down to any non-read
command
tXP
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
2
tCK
tXARDS
7 - AL
8 - AL
tCK
tCKE
3
3
tCK
tAOND
2
2
2
2
tCK
tAC(min)
tAC(max)
+0.7
tAC(min)
tAC(max)
+0.7
ns
tAC(min)+2
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
ns
2.5
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)
+0.6
ns
tAC(min)
+2
2.5tCK+
tAC(max)+1
ns
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
tAON
ODT turn-on(Power-Down mode)
tAONPD
ODT turn-off delay
tAOFD
ODT turn-off
tAOF
tAC(min)
tAC(max)+
0.6
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)
+2
2.5tCK+
tAC(max)+1
ODT to power down entry latency
tANPD
3
3
ODT power down exit latency
tAXPD
8
8
OCD drive mode output delay
tOIT
0
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
tDelay
12
0
tCK
tCK
12
tIS+tCK
+tIH
tIS+tCK+tIH
ns
ns
tREFI
-
7.8
-
7.8
us
2
tREFI
-
3.9
-
3.9
us
3
Notes:
1. For details and notes, please refer to the relevant HYNIX component datasheet (HY5PS1G[8,16]31CFP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C < TCASE ≤ 95°C
Rev. 0.1 / Mar 2009
17
1240pin DDR2 SDRAM Unbuffered DIMMs
PACKAGE OUTLINE
512Mx 64 - HMP351U6AFR8C
Front
133.35
128.95
Side
4.00 max.
4.0±0.1
30.0
Detail-B
5.175
5.175
63.0
(2)
2.5
Detail-A
5.0
1.27 +/- 0.10
55.0
10.0
17.80
Back
3.0
3.0
1.0
Detail of Contacts B
2.50
3.80
0.20
2.50 ±0.20
Detail of Contacts A
0.8 ±0.05
1.50 ±0.10
5.00
Note : All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Mar 2009
18
1240pin DDR2 SDRAM Unbuffered DIMMs
PACKAGE OUTLINE
512Mx 72 - HMP351U7AFR8C
Front
Side
133.35
128.95
4.00 max.
4.0±0.1
30.0
Detail-B
5.175
5.175
63.0
(2)
2.5
Detail-A
5.0
1.27 +/- 0.10
55.0
17.80
10.0
Back
3.0
3.0
1.0
Detail of Contacts B
2.50
3.80
0.20
2.50 ±0.20
Detail of Contacts A
0.8 ±0.05
1.50 ±0.10
5.00
Note : All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Mar 2009
19
1240pin DDR2 SDRAM Unbuffered DIMMs
REVISION HISTORY
Revision
History
Date
0.1
Initial data sheet released
Mar. 2009
Rev. 0.1 / Mar 2009
20