Revised November 1999 74AC175 • 74ACT175 Quad D-Type Flip-Flop General Description Features The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flipflop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW. ■ ICC reduced by 50% ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Asynchronous common reset ■ True and complement output ■ Outputs source/sink 24 mA ■ ACT175 has TTL-compatible inputs Ordering Code: Order Number 74AC175SC 74AC175SJ 74AC175MTC Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 74AC175PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide 74ACT175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74ACT175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ACT175MTC MTC16 74ACT175PC N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D3 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q3 True Outputs Q0–Q3 Complement Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009936 www.fairchildsemi.com 74AC175 • 74ACT175 Quad D-Type Flip-Flop November 1988 74AC175 • 74ACT175 Functional Description Truth Table The AC/ACT175 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOWto-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The AC/ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Inputs Outputs @ tn, MR = H @ tn+1 Dn Qn Qn L L H H H L H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) −0.5V to VCC + 0.5V VO = VCC + 0.5V +20 mA 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ± 50 mA VCC @ 3.3V, 4.5V, 5.5V DC VCC or Ground Current 125 mV/ns Minimum Input Edge Rate (∆V/∆t) ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) −0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) −20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices −65°C to +150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V PDIP 140°C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = +25°C (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.1 0.1 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level Output Voltage 3.0 0.002 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 ±0.1 ± 1.0 µA VI = VCC, GND VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) IIN (Note 4) Maximum Input Leakage Current 5.5 IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC (Note 4) Maximum Quiescent Supply Current 5.5 40.0 µA VIN = VCC or GND 4.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC175 • 74ACT175 Absolute Maximum Ratings(Note 1) 74AC175 • 74ACT175 DC Electrical Characteristics for ACT Symbol Parameter Minimum HIGH Level VIH VIL VOH TA = +25°C VCC (V) Typ 4.5 1.5 TA = −40°C to +85°C Guaranteed Limits 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V VIN = VIL or VIH VOL 4.5 3.86 3.76 5.5 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 0.36 0.44 IOH = −24 mA V IOH = −24 mA (Note 5) V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH 4.5 IOL = 24 mA (Note 5) 5.5 0.36 0.44 IIN Maximum Input Leakage Current 5.5 ±0.1 ± 1.0 µA VI = VCC, GND ICCT Maximum ICC/Input 5.5 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current(Note 6) 5.5 −75 mA VOHD = 3.85V Min ICC Maximum Quiescent 40.0 µA Supply Current 0.6 5.5 4.0 VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol fMAX tPLH tPHL tPLH tPHL Parameter VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 7) Min Typ Maximum Clock 3.3 149 214 139 Frequency 5.0 187 244 187 Propagation Delay 3.3 2.0 9.5 12.0 2.0 13.5 CP to Qn or Qn 5.0 1.5 7.0 9.0 1.0 9.5 Propagation Delay 3.3 2.5 8.5 13.0 2.0 14.5 CP to Qn or Qn 5.0 1.5 6.0 9.5 1.5 10.5 Propagation Delay 3.3 3.0 7.5 12.5 2.5 13.5 MR to Qn 5.0 2.0 5.5 9.0 1.5 10.0 Propagation Delay 3.3 3.0 8.5 11.0 2.5 12.5 MR to Qn 5.0 2.0 6.0 8.5 1.5 9.0 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Max Min Units Max MHz ns ns ns ns Symbol tS tH tW tW Parameter TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF (Note 8) Typ Setup Time, HIGH or LOW 3.3 2.0 4.5 4.5 Dn to CP 5.0 1.0 3.0 3.0 Hold Time, HIGH or LOW 3.3 1.0 1.0 1.0 Dn to CP 5.0 1.0 1.0 1.0 CP Pulse Width 3.3 2.5 4.5 4.5 HIGH or LOW 5.0 2.0 3.5 3.5 MR Pulse Width, LOW tREC VCC Units Guaranteed Minimum 3.3 2.5 4.5 5.0 5.0 2.0 3.5 3.5 ns ns ns ns Recovery Time 3.3 −2.0 0 0 MR to CP 5.0 −1.0 0 0 ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol fMAX Parameter Maximum Clock Frequency tPLH Propagation Delay CP to Qn or Qn tPHL Propagation Delay CP to Qn or Qn tPLH VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Max Min Units (Note 9) Min Typ Max 5.0 175 236 5.0 2.0 6.0 10.0 1.5 11.0 ns 5.0 2.0 7.0 11.0 1.5 12.0 ns 5.0 2.0 6.0 9.5 1.5 10.5 ns 5.0 2.0 5.5 9.5 1.5 10.5 ns 145 MHz Propagation Delay MR to Qn tPHL Propagation Delay MR to Qn Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT Symbol Parameter TA = −40°C to +85°C CL = 50 pF Units 5.0 3.0 2.0 2.0 3.0 2.5 2.5 5.0 0 1.0 1.0 ns 5.0 4.0 3.0 3.5 ns MR Pulse Width, LOW 5.0 4.0 3.0 4.0 ns Recovery Time, MR to CP 5.0 0 0 0 ns Setup Time Dn to CP tH Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW trec CL = 50 pF Typ tS (H) tW TA = +25°C (V) (Note 10) tS (L) tW VCC Guaranteed Minimum ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF V CC = OPEN CPD Power Dissipation Capacitance 45.0 pF V CC = 5.0V 5 Conditions www.fairchildsemi.com 74AC175 • 74ACT175 AC Operating Requirements for AC 74AC175 • 74ACT175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M16A www.fairchildsemi.com 6 74AC175 • 74ACT175 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 7 www.fairchildsemi.com 74AC175 • 74ACT175 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 www.fairchildsemi.com 8 74AC175 • 74ACT175 Quad D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com