PRELIMINARY TECHNICAL DATA High-Efficiency Notebook Computer Power Supply Controller Preliminary Technical Data ADP3026 a FEATURES Wide Input Voltage Range: 6.5 V to 25 V High Conversion Efficiency > 96% Int egrated Current Sense—No External Resistor ReIntegrated quired Low Shutdown Current: 14 A (Typical) Voltage Mode PWM with Input Feed Forward for Fast Line Transient Response Dual Synchronous Buck Controllers with PWM/ Power-Saving Mode Operation Built-In Gate Drive Boost Circuit for Driving External N-Channel MOSFETs Two Fixed Output Voltages: 3.3 V, 5 V PWM Frequency: 300 kHz Extensive Circuit Protection Functions 28-Lead TSSOP Package GENERAL DESCRIPTION The ADP3026 is a highly efficient dual synchronous buck switching regulator controller optimized for converting the battery or adapter input into the system supply voltages required in notebook computers. The ADP3026 uses a dual-mode PWM/Power Saving Mode architecture to maintain efficiency over a wide load range. The ADP3026 provides accurate and reliable short circuit protection using an internal current sense circuit, which reduces cost and increases overall efficiency. Other protection features include programmable soft-start, UVLO, and integrated output undervoltage/overvoltage protection. APPLICATIONS Notebook Computers and PDAs Portable Instruments General Purpose DC-DC Converters FUNCTIONAL BLOCK DIAGRAM V IN 6.5V TO 25V ADP3026 5V LINEAR REF Q1 Q3 L2 L1 5V 5V SMPS Q4 REV. PrB 3.3V Q2 SS3 SS5 PWRGD 3.3V SMPS POWER-ON RESET 3/12/02 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA (@ T = –40ⴗC to +85ⴗC, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA, ADP3026–SPECIFICATIONS REF Load = 0 mA, SD = 5 V, unless otherwise noted.) A Parameter Symbol INTERNAL 5 V REGULATOR Input Voltage Range 5 V Voltage Line Regulation Total Variation Undervoltage Lockout Threshold Voltage Undervoltage Lockout Hysteresis INTVCC REFERENCE Output Voltage2 SUPPLY CURRENT Shutdown Current Standby Current TA = 25°C 6.5 V ≤ VIN ≤ 25 V Line, Temp INTVCC Falling POWER GOOD Output Voltage In Regulation Output Voltage Out of Regulation REF IQ fOSC MAIN SMPS CONTROLLERS Fixed 5 V Output Voltage PWM Mode Power-Saving Mode Fixed 3.3 V Output Voltage PWM Mode Power-Saving Mode Current Limit Threshold (PWM Mode) CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V Current Limit Threshold (Power-Saving Mode) CLSET5 = CLSET3 = Floating CLSET5 = CLSET3 = 0 V 6.5 4.95 4.8 4.2 Typ 5.025 0.3 4.4 Max Unit 25 5.15 V V mV/V V V 5.2 4.5 6.5 V ≤ VIN ≤ 25 V 792 SD = 0 V SS3 = SS5 = 0 V SD = 5 V No Loads SS3 = SS5 = 5 V FB5 = 5.05 V, FB3 = 3.33 V mV 800 808 V 14 100 20 200 µA µA 400 6.5 V ≤ VIN ≤ 25 V 264 10 kΩ Pull-Up to 5 V 10 kΩ Pull-Up to 5 V FB5 < 90% of Nominal Output Value FB5 Rising FB5 Falling CPOR = 1.2 V 4.8 300 µA 336 kHz 0.4 V V PWRGD PWRGD Trip Threshold PWRGD Hysteresis CPOR Pull-Up Current ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Min 300 Quiescent Current (Power-Saving Mode) OSCILLATOR Frequency Conditions –7 –3 4 1 –2 67 10 GBW % % µA dB MHz FB5 6.5 V ≤ VIN ≤ 25 V 6.5 V ≤ VIN ≤ 25 V 4.90 4.925 5.0 5.025 5.10 5.125 V V 6.5 V ≤ VIN ≤ 25 V 6.5 V ≤ VIN ≤ 25 V 3.234 3.250 3.3 3.316 3.366 3.382 V V 54 240 72 300 90 360 mV mV FB3 6.5 V ≤ VIN ≤ 25 V, TA = 25°C 6.5 V ≤ VIN ≤ 25 V, TA = 25°C 6.5 V ≤ VIN ≤ 25 V, TA = 25°C 6.5 V ≤ VIN ≤ 25 V, TA = 25°C –2– 16 70 mV mV REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 Parameter Power-Saving Mode Trip Threshold Soft-Start Current Soft-Start Turn-On Threshold Transition Time (DRVL) Rise Fall Transition Time (DRVH) Rise Fall Logic Input Low Voltage Logic Input High Voltage FAULT PROTECTION Output Overvoltage Trip Threshold Output Undervoltage Lockout Threshold Symbol Conditions Min Typ Max Unit 60 2.5 0.6 0.8 mV µA V 0.4 CLOAD = 3000 pF, 10%–90% CLOAD = 3000 pF, 90%–10% 40 40 70 70 ns ns tR(DRVH) CLOAD = 3000 pF, 10%–90% tF(DRVH) CLOAD = 3000 pF, 90%–10% SD SD 50 50 100 100 0.6 ns ns V V 120 80 125 85 % % CLSET5 = CLSET3 = 0 V, TA = 25°C SS3 = SS5 = 3 V SS5, SS3 tR(DRVL) tF(DRVL) With Respect to Nominal Output With Respect to Nominal Output 2.4 115 75 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 The reference’s line-regulation error is insignificant. The reference cannot be used for external load. Specifications subject to change without notice. REV. PrB –3– PRELIMINARY TECHNICAL DATA ADP3026 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 CS5 2 3 4 5 6 FB5 EAN5 EAO5 SS5 CLSET5 7 REF 8 9 AGND CLSET3 10 11 12 13 14 SS3 EAO3 EAN3 FB3 CS3 15 PWRGD 16 CPOR 17 18 19 20 21 22 BST3 DRVH3 SW3 DRVL3 VIN INTVCC 23 SD 24 25 26 27 28 PGND DRVL5 SW5 DRVH5 BST5 Current Sense Input for top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of the top N-channel MOSFET. Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode. Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation . Error Amplifier Output for the 5 V Buck Converter. Soft Start for the 5 V Buck Converter. Also used as an ON/OFF Pin. Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND. 800 mV Bandgap Reference. Bypass it with a capacitor (22 nF typical) to AGND. REF cannot be used directly with an external load. Analog Signal Ground. Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current limit is obtained by leaving it unconnected. A max current limit is obtained by connecting it to AGND. Soft Start for the 3.3 V Buck Converter. Also used as an ON/OFF Pin Error Amplifier Output for the 3.3 V Buck Converter. Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation. Feedback Input for the 3.3 V Buck Converter. Connect to output sense point. Current Sense Input for Top N-Channel MOSFET of the 3.3 V Buck Converter. It should be connected to the drain of the N-channel MOSFET. Power Good Output. PWRGD goes low with no delay, whenever the 5 V output drops 7% below its nominal value. When the 5 V output is within –3% of its nominal value, PWRGD will be released after a time delay determined by the timing capacitor on the CPOR pin. Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 1 µA pull-up current is used to charge the capacitor. A manual reset (MR) function can also be implemented by grounding this pin. Boost Capacitor Connection for High-Side Gate Driver of the 3.3 V Buck Converter. High-Side Gate Driver for 3.3 V Buck Converter. Switching Node (Inductor) Connection of the 3.3 V Buck Converter. Low-Side Gate Driver of 3.3 V Buck Converter. Main Supply Input (6.5 V to 25 V). Linear Regulator Bypass for the internal 5 V LDO. Bypass this pin with a 4.7 µF capacitor to AGND. Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown with very low quiescent current. For automatic start-up, connect SD to VIN directly. Power Ground. Low-Side Driver for 5 V Buck Converter. Switching Node (Inductor) Connection for 5 V Buck Converter. High-Side Gate Driver for 5 V Buck Converter. Boost Capacitor Connection for High-Side Gate Driver of the 5 V Buck Converter. –4– REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 PIN CONFIGURATION * ABSOLUTE MAXIMUM RATINGS* VIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +27 V AGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V INTVCC . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +6 V BST5, BST3 to PGND . . . . . . . . . . . . . . . . . –0.3 V to +32 V BST5 to SW5 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V BST3 to SW3 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V CS5, CS3 . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to VIN SW3, SW5 to PGND . . . . . . . . . . . . . . . . –2 V to VIN + 2 V SD . . . . . . . . . . . . . . . . . . . . . . . . . AGND – 0.3 V to +27 V DRVL5/3 to PGND . . . . . . . . –0.3 V to (INTVCC + 0.3 V) DRVH5/3 to SW5/3 . . . . . . . . –0.3 V to (INTVCC + 0.3 V) All Other Inputs and Outputs . . . . . . . . . . . . . . . . . . AGND – 0.3 V to INTVCC + 0.3 V θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W Operating Ambient Temperature Range . . . . –40°C to +85°C Junction Temperature Range . . . . . . . . . . . . –40°C to +150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C CS5 1 28 BST5 FB5 2 27 DRVH5 EAN5 3 ADP3026 EAO5 4 TOP VIEW (Not to Scale) 25 DRVL5 SS5 5 24 PGND CLSET5 6 23 SD REF 7 22 INTVCC 21 VIN AGND 8 20 DRVL3 SS3 10 19 SW3 EAO3 11 18 DRVH3 CLSET3 9 EAN3 *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. 26 SW5 17 BST3 12 FB3 13 16 CPOR CS3 14 15 PWRGD ORDERING GUIDE Model Temperature Range Package Description Package Option ADP3026ARU –40°C to +85°C Thin Shrink Small Outline RU-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this device features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. PrB –5– PRELIMINARY TECHNICAL DATA ADP3026 INPUT ADP3026 VIN + 72mV + 1 CS5 SD INTVCC 5V 14mV + +5V LINEAR REG + CLSET5 REF 800mV 800mV REF ULVO AGND BST5 DRVH5 SW5 INTVCC 300kHz OSC PWRGD DRVL5 CONTROL LOGIC POWER› ON RESET VOUT5 5V PGND FB5 ›3mV 1A FB5 + +2% 816mV + 800mV 0% + ›2% 784mV EAN5 EA + 800mV EAO5 SHUTDOWN + +20% + ›20% S 960mV 640mV OC Q 1.8V R + CPOR 2.5A SS5 + 0.6V ON5 DUPLICATE FOR SECOND CONTROLLER Figure 1. Block Diagram –6– REV. PrB PRELIMINARY TECHNICAL DATA Typical Performance Characteristics– ADP3026 300 +85ⴗC 100 VIN = 7V +25ⴗC 250 VIN = 15V CURRENT – A EFFICIENCY › % 90 80 –40ⴗC 200 70 150 60 100 5 50 0.01 0.1 1 OUTPUT CURRENT › A 10 15 20 25 INPUT VOLTAGE – V 10 TPC 4. Input Standby Current vs. Input Voltage TPC 1. Efficiency vs. 5 V Output Current 10 100 9 VIN = 7V 8 +85ⴗC 90 CURRENT – A 7 EFFICIENCY › % VIN = 15V 80 70 +25ⴗC 6 5 –40ⴗC 4 3 2 60 1 0 5 50 0.01 0.1 1 OUTPUT CURRENT › A 10 15 20 25 INPUT VOLTAGE – V 10 TPC 5. Input Shutdown Current vs. Input Voltage TPC 2. Efficiency vs. 3.3 V Output Current 900 315 SYNC = REF 310 +85ⴗC FREQUENCY › kHz CURRENT – A 800 700 +25ⴗC –40ⴗC 600 VIN = 25 305 VIN = 12 300 VIN = 7.5 500 400 295 5 10 15 20 290 ›40 25 INPUT VOLTAGE – V TPC 3. PSV Mode Input Current vs. Input Voltage REV. PrB VIN = 5.5 ›10 20 50 AMBIENT TEMPERATURE › ⴗC 80 TPC 6. PWM Mode Oscillator Frequency vs. Temperature –7– PRELIMINARY TECHNICAL DATA ADP3026 250 CURRENT LIMIT THRESHOLD › mV T [ STOP ] CLSET = GND 200 CH1 = 5V OUTPUT 150 VIN = 6.5V TO 25V 100 50 0 ›40 ›30 ›20 ›10 CH2 = I OUT = 10mA TO 3A 0 10 20 30 40 50 AMBIENT TEMPERATURE › ⴗC 60 70 80 CH1 200mV TPC 7.Current Limit Threshold vs. Temperature CH2 2.00V M 200s CH2 1.88V TPC 10. Power-Saving Mode, Transient Response 1.210 STOP T [ ] REFERENCE OUTPUT › V 1.205 CH1 = 5V OUTPUT (IOUT = 20mA) 1.200 1.195 1.190 VIN = 6.5V TO 25V 1.185 CH2 = SW5 1.180 ›40 ›30 ›20 ›10 0 10 20 30 40 50 AMBIENT TEMPERATURE › ⴗC 60 70 80 CH1 200mV TPC 8. Reference Output vs. Temperature TEK STOP: SINGLE SEQ 250 S/s [ T CH2 5.00V M 400s CH2 1.90V TPC 11. Power-Saving Mode, Waveforms STOP ] T [ ] CH1 = 5V OUTPUT CH1 = 3.3V OUTPUT CH2 = 2.5V OUTPUT CH3 = SS3 CH2 = I OUT = 10mA TO 3A VIN = 12V CH4 = SS5 CH1 CH3 2.00V 1.00V CH2 CH4 1.00V 1.00V M 200MS CH4 CH1 200mV 740mV CH2 2.00V M 200s CH2 1.88V TPC 12. PWM Mode, Transient Response TPC 9. Soft-Start Sequencing –8– REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 TEK STOP: SINGLE SEQ 250 S/s [ T ] CH1 CH2 CH1 10.0V CH2 200mV M 5.00ms CH1 10.8V TPC 13. VIN = 7.5 V to 22 V Transient, 5 V Output, CH1 – Input Voltage, CH2 – Output Voltage REV. PrB –9– PRELIMINARY TECHNICAL DATA ADP3026 THEORY OF OPERATION The ADP3026 is a dual-mode, step-down power supply controller for notebook computers or similar battery-powered applications. The device contains two synchronous stepdown buck controllers and a linear regulator controller. The buck controllers in the ADP3026 have the ability to provide fixed 3.3 V and 5 V outputs. High efficiency over a broad load range is achieved by using a proprietary dual-mode PWM/power-saving (PSV) mode architecture. Efficiency is further improved by deleting the external current sense resistor, which is the main contributor to loss during high current, low output voltage conditions. CIRCUIT DESCRIPTION Dual-Mode Architecture The ADP3026 contains two independent dual-mode, synchronous buck controllers. Traditional constant frequency PWM buck converters suffer from relatively low efficiency under light load conditions. In order to maintain high efficiency over a wide load range, the ADP3026 use a proprietary dual-mode architecture. At moderate to heavy loads, the buck converter operates in the traditional Pulsewidth Modulation (PWM) mode. At light loads, PSV mode is used to increase system efficiency. A proprietary detection scheme is used for transition from one mode to the other. Input current to the high-side MOSFET is detected when going from PWM mode to PSV mode, and output voltage information is used when changing from PSV mode to PWM mode. When the high-side N-channel MOSFET is turned on, the current going through the N-channel MOSFET is measured as a voltage between CS and SW. If the peak current through the MOSFET is less than 20% of the current limit value set by CLSET, an internal counter that is based on the oscillator frequency will be started. If the current stays below this threshold for 16 PWM cycles, the buck converter will enter power-saving mode. The counter will automatically reset if the peak current is higher than 20% of the current limit value any time prior to when the counter reaches 16. In PSV mode, the buck converter works like a window regulator. If the output voltage drops below the PWM mode nominal output voltage, the high-side MOSFET will be turned on. It will remain on until the output capacitors are charged up to 2% above the PWM mode nominal output voltage. The high-side MOSFET will then be latched off until the output capacitors are discharged to the lower threshold. The discharge rate is dependent on the output capacitor value and load current. It is important to note that the current limit threshold when in PSV mode is approximately 1/4 of the current limit threshold when in PWM mode. If a large load is applied to the converter when in PSV mode (for example, larger than the current limit in PSV mode), the output will continue to drop due to the lower current limit threshold of PSV mode. When the output voltage drops to 2% below the PWM mode nominal voltage, the converter will automatically return to PWM mode. Once in PWM mode, the current limit is quadrupled, and the output will be charged up to the nominal level, as long as the load does not exceed the higher PWM current limit. PWM/PSV Operation Table I shows the summary of the operating modes of the synchronous buck controllers. Table I. PWM Mode and PSV Mode Load Current Operating Mode Description Heavy Moderate Light PWM PWM PSV Constant-Frequency PWM Constant-Frequency PWM Variable-Frequency, Burst Mode Internal 5 V Supply (INTVCC) An internal low dropout regulator (LDO) generates a 5 V supply (INTVCC) that powers all of the functional blocks within the IC. The total current rating of this LDO is 50 mA. However, this current is used for supplying gate-drive power, and it is not recommended that current be drawn from this pin for other purposes. Bypass INTVCC to AGND with a 4.7 µF capacitor. A UVLO circuit is also included in the regulator. When INTVCC < 3.8 V, the two switching regulators, and the linear regulator controller are shut down. The UVLO hysteresis voltage is about 120 mV. The internal LDO has a built-in fold-back current limit, so that it will be protected if a short circuit is applied to the 5 V output. Reference (REF) The ADP3026 contains a precision 800 mV bandgap reference. Bypass REF to AGND with a 22 nF ceramic capacitor. The reference is intended for internal use only. Boost High-Side Gate Drive Supply (BST) The gate drive voltage for the high-side N-channel MOSFET is generated by a flying-capacitor boost circuit. The boost capacitor connected between BST and SW is charged from the INTVCC supply. Use only small-signal diodes for the boost circuit. Synchronous Rectifier (DRVL) Synchronous rectification is used to reduce conduction losses and to ensure proper start-up of the boost gate driver circuit. Antishoot-through protection has been included to prevent cross conduction during switch transitions. The low-side driver must be turned off before the high-side driver is turned on. For typical N-channel MOSFETs, the dead time is about 50 ns. On the other edge, a dead time of about 50 ns is achieved by an internal delay circuit. The synchronous rectifier is turned off when the current flowing through the low-side MOSFET falls to zero when in Discontinuous Conduction (DCM) PWM mode and PSV mode. In Continuous Conduction (CCM) PWM mode, the current flowing through the low-side MOSFET never reaches zero, so the synchronous rectifier is turned off by the next clock cycle. –10– REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 Shutdown (SD SD) SD clock cycles, and the output voltage is below 20% of the nominal output voltage, both controllers will be latched off and will not restart until SD or SS3/SS5 is toggled, or until VIN is cycled below 4 V. This feature is disabled during soft start. Holding SD = GND low will put the ADP3026 into ultralow current shutdown mode. For automatic start-up, SD can be tied directly to VIN. Soft-Start and Power-Up Sequencing (SS) SS3 and SS5 are soft-start pins for the two controllers. A 2.5 µA pull-up current is used to charge an external softstart capacitor. Power-up sequencing can easily be done by choosing different capacitance. When SS3/SS5 < 0.6 V, the two switching regulators are turned off. When 0.6 V < SS5/ SS3 < 1.8 V, the regulators start working in soft-start mode. When SS3/SS5 > 1.8 V, the regulators are in normal operating mode. The controllers are forced to stay in PWM mode during the soft-start period. The minimum soft-start time (~20 µs) is set by an internal capacitor. Table II shows the ADP3026 operating modes. Output Overvoltage Protection Both converter outputs are continuously monitored for overvoltage. If either output voltage is higher than the nominal output voltage by more than 20%, both converter’s high-side gate drivers (DRVH5/3) will be latched off, and the lowside gate drivers will be latched on, and will not restart until SD or SS5/SS3 are toggled, or until VIN is cycled below 4 V. The low-side gate driver (DRVL) is kept high when the controller is in off-state and the output voltage is less than 93% of the nominal output voltage. Discharging the output capacitors through the main inductor and low-side N-channel MOSFET will cause the output to ring. This will make the output momentarily go below GND. To prevent damage to the circuit, use a reverse-biased 1 A Schottky diode across the output capacitors to clamp the negative surge. Current Limiting (CLSET) A cycle-by-cycle current limiting scheme is used by monitoring current through the top N-channel MOSFET when it is turned on. By measuring the voltage drop across the high-side MOSFET VDS(ON), the external sense resistor can be deleted. The current limit value can be set by CLSET. When CLSET = Floating, the maximum VDS(ON) = 72 mV at room temperature; when CLSET = 0 V, the maximum VDS(ON) = 300 mV at room temperature. An external resistor can be connected between CLSET and AGND to choose a value between 72 mV and 300 mV. The relationship between the external resistance and the maximum VDS(ON) is: VDS(ON )MAX = 72 mV (110K + REXT ) (26K + REXT ) Power Good Output (PWRGD) The ADP3026 also provides a PWRGD signal for the microprocessor. During start-up, the PWRGD pin is held low until 5 V output is within –3% of its preset voltage. Then, after a time delay determined by an external timing capacitor connected from CPOR to GND, PWRGD will be actively pulled up to INTVCC by an external pull-up resistor. This delay can be calcualated by: (1) Td = The temperature coefficient of RDS(ON) of the N-channel MOSFET is canceled by the internal current limit circuitry, so that an accurate current limit value can be obtained over a wide temperature range. In PSV mode, the current limit value is reduced to about 1/4 of the value in PWM mode to reduce the interference noise to other components on the PC board. 1.2V × CCPOR 1µA CPOR can also be used as a manual reset (MR) function. When the 5 V output is lower than the preset voltage by more than 7%, PWRGD is immediately pulled low. APPLICATION INFORMATION A typical notebook PC application circuit using the ADP3026 is shown in Figure 2. Although the component values given in Figure 3 are based on a 5 V @ 4 A /3.3 V @ 4 A design, the ADP3026 output drivers are capable of Output Undervoltage Protection Each switching controller has an undervoltage protection circuit. When the current flowing through the high-side MOSFET reaches the current limit continuously for eight Table II. Operating Modes SD SS5 SS3 Mode Description Low High High High High High X SS5 < 0.6 V 0.6 V < SS5 < 1.8 V 1.8 V < SS5 X X X SS3 < 0.6 V X X 0.6 V < SS3 < 1.8 V 1.8 V < SS3 Shutdown Standby Run Run Run Run All Circuits Turned Off 5 V and 3.3 V Off; INTVCC = 5 V, REF = 0.8 V 5 V in Soft Start 5 V in Normal Operation 3.3 V in Soft Start 3.3 V in Normal Operation REV. PrB (2) –11– PRELIMINARY TECHNICAL DATA ADP3026 handling output currents anywhere from <1 A to over 10 A. Throughout this section, design examples and component values will be given for three different power levels. For simplicity, these levels will be referred to as low power, basic, and extended power. Table III shows the input/output specifications for these three levels. Table III. Typical Power Level Examples Input Voltage Range Switching Output 1 Switching Output 2 Low Power Basic Extended Power 6.5 V to 25 V 6.5 V to 25 V 6.5 V to 25 V 3.3 V/2 A 3.3 V/4 A 3.3 V/10 A 5 V/2 A 5 V/4 A 5 V/10 A Nominal Inductor Value The inductor design is based on the assumption that the inductor ripple current is 30% of the maximum output dc current at nominal 12 V input voltage. The inductor ripple current and inductance value are not critical, but this choice is quite important in analyzing the trade-offs between cost, size, efficiency, and volume. The higher the ripple current, the lower the inductor size and volume. However, this will lead to higher ac losses in the windings. Conversely, a higher inductor value means lower ripple current and smaller output filter capacitors, but transient response will be slower. Input Voltage Range The input voltage range of the ADP3026 is 6.5 V to 25 V though the converter design is optimized to deliver the best performance within a 7.5 V to 18 V range, which is the nominal voltage for three to four cell Li-Ion battery stacks. Voltages above 18 V may occur under light loads and when the system is powered from an ac adapter with no battery installed. Maximum Output Current and MOSFET Selection The maximum output current for each switching regulator is limited by sensing the voltage drop between the drain and source of the high-side MOSFET when it is turned on. A current sense comparator senses voltage drop between CS5 and SW5 for the 5 V converter and between CS3 and SW3 for the 3.3 V converter. The sense comparator threshold is 72 mV when the programming pin, CLSET, is floating, and is 300 mV when CLSET is connected to ground. Currentlimiting is based on sensing the peak current. Peak current varies with input voltage and depends on the inductor value. The higher the ripple current or input voltage, the lower the converter maximum output current at the set current sense amplifier threshold. The relation between peak and dc output current is given by: VIN (MAX ) – VOUT 2 × f × L × VIN(MAX ) I PEAK = IOUT + VOUT × I PEAK = VTH RDS (ON ) (4) Rearranging Equation 2 to solve for IOUT(MAX) gives: VTH RDS (ON ) The design of the inductor should be based on the maximum output current plus 15% (1/2 of the 30% ripple allowance) at the nominal input voltage: L ≥ 3 × (VIN (NOM) – VOUT ) × VOUT VIN(NOM) × IOUT × f (6) Optimum standard inductor values for the three power levels are shown in Table IV. Table IV. Standard Inductor Values Freq. 3.3 V/2 A 3.3 V/4 A 3.3 V/10 A 5 V/2 A 5 V/4 A 5 V/10 A 300 kHz 12 µH 6.8 µH 2.2 µH 15 µH 8.2 µH 3.3 µH Inductor Selection (3) At a given current comparator threshold VTH and MOSFET RDS(ON), the maximum inductor peak current is: IOUT (MAX ) = Normally, VTH should be set to its maximum value of 144 mV. For example, in the circuit of Figure 2, an Si4410, which has an RDS(ON) of 13.5 mΩ would have a maximum peak current limit of around 10 A. A less efficient way to achieve maximum power from the converter is to design the inductor with a larger inductance, (i.e., a lower ripple current). This helps reduce the peak-to-dc current ratio and increases maximum converter output, but may also increase the inductor value and its size. It is important to remember that this current limit circuit is designed to protect against high current or short circuit conditions only. This will protect the IC and MOSFETs long enough to allow the output undervoltage protection circuitry to latch off the supply. V –V – VOUT × IN (MAX ) OUT (5) 2 × f × L × VIN (MAX ) Once the value for the inductor is known, there are two ways to proceed; either to design the inductor in-house or to buy the closest inductor that meets the overall design goals. Standard Inductors Buying a standard inductor will provide the fastest, easiest solution, and many companies offer suitable power inductor solutions. A list of power inductor manufacturers is given in Table V. CIN and COUT Selection In continuous conduction mode, the source current of the upper MOSFET is approximately a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by: –12– REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 VIN 6.5V›25V C22 4.7F C18 470pF R10 10k⍀ R2 15.8k⍀ C1 68pF C2 1000pF R2 47k⍀ C4 22nF C5 22nF R3 47k⍀ C6 47nF C8 1000pF R4 15.8k⍀ C19 1000pF R11 4.53k⍀ C9 68pF U1 ADP3026 1 CS5 2 FB5 3 EAN5 SW5 26 4 EAO5 DRVL5 25 5 SS5 6 CLSET5 7 REF 8 AGND 9 CLSET3 10 SS3 C17 100nF D6 1N4148 C14B 10F L2 6.8H Q5 SI4410 D2 10BQ040 Q4 SI4410 PGND 24 + C27A 68F + + C24A 68F + VOUT5 5V, C27B 4A 68F INTVCC 22 VIN 21 DRVL3 20 C15 4.7F R5 10⍀ SW3 19 DRVH3 18 EAN3 BST3 17 13 FB3 CPOR 16 14 CS3 PWRGD 15 C13 1F C20A 10F C20B 10F D5 1N4148 Q2 C12 SI4410 R12 10k⍀ 100nF PWRGD Q3 SI4410 L1 6.8H D1 10BQ040 Figure 2. 33W, Dual Output DC-DC Converter REV. PrB D4 10BQ040 (OPTIONAL) SD 23 11 EAO3 12 C14A 10F BST5 28 DRVH5 27 R14 4.7⍀ –13– D3 10BQ040 (OPTIONAL) VOUT33 3.3V, C24B 4A 68F PRELIMINARY TECHNICAL DATA ADP3026 I RMS ≈ VOUT × (VIN – VOUT ) × I MAX VIN (7) This formula has a maximum at VIN = 2 × VOUT, where IRMS = IOUT/2. Note that the capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. If electrolytic or tantalum capacitors are used, an additional 0.1 µF–1 µF ceramic bypass capacitor should be placed in parallel with CIN. The selection of COUT is driven by the required effective series resistance (ESR) and the desired output ripple. A good rule of thumb is to limit the ripple voltage to 1% of the nominal output voltage. It is assumed that the total ripple is caused by two factors: 25% comes from the COUT bulk capacitance value, and 75% comes from the capacitor ESR. The value of COUT can be determined by: COUT = I RIPPLE 2 × f × VRIPPLE (8) where IRIPPLE = 0.3 × IOUT and VRIPPLE = 0.01 × VOUT. The maximum acceptable ESR of COUT can then be found using: ESR ≤ 0.75 × VRIPPLE I RIPPLE (9) Manufacturers such as Vishay, AVX, Elna, WIMA, and Sanyo provide good high-performance capacitors. Sanyo’s OSCON semiconductor dielectric capacitors have lower ESR for a given size, at a somewhat higher price. Choosing sufficient capacitors to meet the ESR requirement for COUT will normally exceed the amount of capacitance needed to meet the ripple current requirement. In surface-mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR, or RMS current handling requirements. Aluminum electrolytic and dry tantalum capacitors are available in surface-mount configurations. In the case of tantalum, it is critical that capacitors are surge tested for use in switching power supplies. Recommendations for output capacitors are shown in Table VI. Power MOSFET Selection N-channel power MOSFETs must be selected for use with the ADP3026 for both the main and synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage (VGS(TH)) and ON-resistance (RDS(ON)). An internal LDO generates a 5 V supply that is boosted above the input voltage using a bootstrap circuit. This floating 5 V supply is used for the upper MOSFET gate drive. Logic-level threshold MOSFETs must be used for both the main and synchronous switches. Maximum output current (IMAX) determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3026 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the load current. The duty cycles for the MOSFETs are given by: Table V. Recommended Inductor Manufacturers Coilcraft Coiltronics Murata Electronics North America Inc. Phone: 847/639-6400 Fax: 847/639-1469 Web: www.coilcraft.com Phone: 561/241-7876 Fax: 561/241-9339 Web: www.coiltronics.com Phone: 770/436-1300 Fax: 770/436-3030 Web: www.murata.com SMT Power Inductors, Series 1608, 3308, 3316, 5022, 5022HC, DO3340, Low Cost Solution SMT Shielded Power Inductors, Series DS5022, DS3316, DT3316, Best for Low EMI/RFI SMT Power Inductors, Series UNI-PAC2, UNI-PAC3 and UNI-PAC4, Low Cost Solution SMT Power Inductors, Series, ECONO-PAC, VERSA-PAC, Best for Low Profile or Flexible Design. SMT Power Inductors, Series LQT2535 Best for Low EMI/RFI Power Inductors and Chokes, Series DC1012, PCV-0, PCV-1, PCV-2, PCH-27, PCH-45, Low Cost Power Inductors CTX Series, Low EMI/RFI, Low Cost Toroidal Inductors but Not Miniature. Chip Inductors LQN6C, LQS66C –14– REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 VOUT VIN (10) VIN – VOUT VIN (11) Upper MOSFET Duty Cycle= Lower MOSFET Duty Cycle = From the duty cycle, the required minimum RDS(ON) for each MOSFET can be derived by the following equations: Upper MOSFET: RDS(ON ) (Upper ) = VIN × PD VOUT × I MAX2 × (1 + α∆T ) (VIN VIN × PD – VOUT ) × I MAX 2 × (1 + α∆T ) (13) where PD is the allowable power dissipation and α is the temperature dependency of RDS(ON). PD will be determined by efficiency and/or thermal requirements (see Efficiency ). (1 + α∆T) is generally given for a MOSFET in the form of a normalized RDS(ON) vs. temperature curve, but α = 0.007/°C can be used as an approximation for low voltage MOSFETs. Maximum MOSFET power dissipation occurs at maximum output current, and can be calculated as follows: Upper MOSFET: PD (Upper ) = VOUT × I MAX 2 × RDS(ON ) × (1 + α∆T ) VIN (14) VIN – VOUT × I MAX 2 × RDS(ON ) × (1 + α∆T ) (15) VIN The Schottky diode, D1 shown in Figure 2, conducts only during the dead time between conduction of the two power MOSFETs. D1’s purpose is to prevent the body-diode of the lower N-channel MOSFET from turning on and storing charge during the dead time, which could cost as much as 1% in efficiency. D1 should be selected for forward voltage of less than 0.5 V when conducting IMAX. Recommended transistors for upper and lower MOSFET’s are given in Table VII. (12) Lower MOSFET: RDS(ON ) (Lower ) = PD (Lower ) = Table VII. Recommended MOSFETs Maximum Output 2A 4A 10 A Vishay/ Siliconix Si4412DY, 28 mΩ Si4410DY, 13.5 mΩ Si4874DY, 7.5 mΩ International Rectifier IRF7805, 11 mΩ IRF7811, 8.9 mΩ IRF7805, 11 mΩ IRFBA3803, 5.5 mΩ IRF7809, 7.5 mΩ Soft Start The soft-start time of each of switching regulator can be programmed by connecting a soft-start capacitor to the corresponding soft-start pin (SS3 or SS5). The time it takes each regulator to ramp up to its full duty ratio depends proportionally on the values of the soft-start capacitors. The charging current is 2.5 µA ±20%. The capacitor value to set a given soft-start time, tSS, is given by: CSS ≅ 2.5 µA × Lower MOSFET: (tSS ) 2.6 V (pF ) Table VI. Recommended Capacitor Manufacturers Maximum Output Current Input Capacitors Output Capacitors +3.3 V Output Output Capacitors +5 V Output REV. PrB 2A 4A 10 A TOKIN Multilayer Ceramic Caps, 22 µF/25 V P/N: C55Y5U1E226Z TAIYO YUDEN INC. Ceramic Caps, Y5V Series 10 µF/25 V P/N: TMK432BJ106KM SANYO POSCAP TPC Series, 68 µF/10 V SANYO POSCAP TPC Series, 68 µF/10 V TOKIN Multilayer Ceramic Caps, 2 × 22 µF/25 V P/N: C55Y5U1E226Z TAIYO YUDEN INC. Ceramic Caps, Y5V Series 2 ×10 µF/25 V P/N: TMK432BJ106KM SANYO POSCAP TPC Series, 2 × 68 µF/10 V SANYO POSCAP TPC Series, 2 × 68 µF/10 V TOKIN Multilayer Ceramic Caps, 2 × 22 µF/25 V P/N: C55Y5U1E226Z VISHEY Ceramic Caps, Z5U Series, 2 × 15 µF/25 V –15– SANYO POSCAP TPB Series, 2 × 220 µF/4.0 V SANYO POSCAP TPB Series, 2 × 330 µF/6.3 V (16) PRELIMINARY TECHNICAL DATA ADP3026 multiple MOSFETs and thick traces may tend to lead to lower efficiency and higher price. This is due to the tradeoff between reduced resistive loss and increased gate drive loss that must be considered when optimizing efficiency. Fixed or Adjustable Output Voltage Each switching controller of the ADP3026 can be programmed to operate with a fixed or adjustable output voltage. As shown by the general application schematic in Figure 2, putting the ADP3026 into fixed mode gives a nominal output of 3.3 V and 5 V for the two switching buck converters. By using two identical resistor dividers per converter, any output voltage between 1.25 V and VIN–0.5 V can be set. The center point of one divider is connected to the feedback pin, FB, and the center point of the other identical divider is connected to EAN. It is important to use 1% resistors. A good value for the lower leg resistors is 10 kΩ, 1%, then the upper leg resistors for a given output voltage can be determined by: RUPPER = VOUT –1.2 V (k Ω ) 0.12 2. Switching losses due to the limited time of switching transitions. This occurs due to gate drive losses of both upper and lower MOSFETs, and switching node capacitive losses, as well as through hysteresis and eddy-current losses in power choke. Input and output capacitor ripple current losses should also be considered as switching losses. These losses are input-voltage-dependent and can be estimated as follows: (18) PSWLOSS = 2.5 × VIN1.85 × I MAX × CSN × f Table VIII shows the resistor values for the most common output voltages. where CSN is the overall capacitance of the switching node related to loss. PWM Mode/Power-Saving (PSV) Mode Operation Both converters operate in a dual PWM/PSV mode of operation. In dual mode, each converter has its own boundary output current when the converter switches from PSV mode to PWM mode and vice versa. There is an output current hysteresis for each mode transition to avoid improper operation. There are several design recommendations regarding dual mode operation. The trip output current level for switching between PWM mode and PSV mode is a percentage of the peak current sensed via the internal current sense comparator. However, the value of that current depends on the RDS(ON) of the upper MOSFET. For example, if the design uses an Si4420 versus an Si4410 power MOSFET (9 mΩ vs. 13.5 mΩ) the maximum output power of the converter and the mode trip output current will both be 50% higher. Efficiency Enhancement The efficiency of each switching regulator is inversely proportional to the losses during the switching conversion. The main factors to consider when attempting to maximize efficiency are: 1. Resistive losses, which include the RDS(ON) of upper and lower MOSFETs, trace resistances and output choke wire resistance. These losses contribute a major part of the overall power loss in low voltage battery-powered applications. However, trying to reduce these resistive losses by using (18) 3. Supply current of the switching controller (independent of the input current redirected to supply the MOSFETs’ gates). This is a very small portion of the overall loss, but it does increase with input voltage. Transient Response Considerations Both stability and regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in output load current. When a load step occurs, output voltage shifts by an amount equal to the current step multiplied by the total ESR of the summed output capacitor array. Output overshoot or ringing during the recovery time (in both directions of the current step change) indicates a stability problem. The external feedback compensation components shown in Figure 2 should provide adequate compensation for most applications. Feedback Loop Compensation The ADP3026 use Voltage Mode control to stabilize the switching controller outputs. Figure 4 shows the voltage mode control loop for one of the buck switching regulators. The internal reference voltage VREF is applied to the positive input of the internal error amplifier. The other input of the error amplifier is EAN, and is internally connected to the feedback sensing pin FB via an internal resistor. The error amplifier creates the closed-loop voltage level for the pulsewidth modulator that drives the external power MOSFETs. The output LC filter smooths the pulsewidth modulated input voltage to a dc output voltage. –16– REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 ADP3026 PWM COMPARATOR VIN 1 2 π × R2 × C1 (23) 1 2 π × (R1 + R3) × C3 (24) f Z1 = DRVH L1 V RAMP DRVL C2 The value of the internal resistor R1 is 89 kΩ for the 3.3 V switching regulator, and 150 kΩ for the 5 V switching regulator. PARASITIC ESR EAO C1 R2 Compensation Loop Design and Test Method C3 EAN 1. Choose the gain (R2/R1) for the desired bandwidth. R3 REF fZ2 = VOUT COUT R1 FB 2. Place fZ1 20%–30% below fLC. 3. Place fZ2 20%–30% above fLC. Figure 3. Buck Regulator Voltage Control Loop The pulsewidth modulator transfer function is VOUT/ VEAOUT, where VEAOUT is the output voltage of the error amplifier. That function is dominated by the impedance of the output filter with its double-pole resonance frequency (fLC) and a single zero at output capacitor (fESR) and the dc gain of the modulator, equal to the input voltage divided by the peak ramp height (VRAMP), which is equal to 1.2 V when VIN = 12 V f LC = 1 2 π × LF × COUT FESR = 1 2 π × ESR × COUT (19) (20) The compensation network consists of the internal error amplifier and two external impedance networks ZIN and ZFB. Once the application and the output filter capacitance and ESR are chosen, the specific component values of the external impedance networks Z IN and ZFB can be determined. There are two design criteria for achieving stable switching regulator behavior within the line and load range. One is the maximum bandwidth of the loop, which affects fast transient response, if needed, and the other is the minimum accepted by the design phase margin. The phase margin is the difference between the closed-loop phase and 180 degrees. Recommended phase margin is 45 to 60 degrees for most applications. 4. Place fP1 at fESR, check the output capacitor for worst-case ESR tolerances. 5. Place fP2 at 40%–60% of oscillator frequency. 6. Estimate phase margins in full frequency range (zero frequency to zero gain crossing frequency). 7. Apply the designed compensation and test the transient response under a moderate step load change (30%–60%) and various input voltages. Monitor the output voltage via oscilloscope. The voltage overshoot or undershoot should be within 1%–3% of the nominal output, without ringing and abnormal oscillation. Layout Considerations The following guidelines are recommended for optimal performance of a switching regulator in a portable PC system: General Recommendations 1. For best results, a four-layer (minimum) PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power, and wide interconnection traces in the rest of the power delivery current paths. Each square unit of 1 ounce copper trace has a resistance of ~ 0.53 mý at room temperature. 2. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 3. The power and ground planes should overlap each other as little as possible. It is generally easiest (although not necessary) to have the power and signal ground planes on the same PCB layer. The planes should be connected nearest to the first input capacitor where the input ground current flows from the converter back to the battery. The equations for calculating the compensation Poles and Zeros are: f P1 = 1 C1× C2 2 π × R2 × C1 + C2 fP2 = REV. PrB 1 2 π × R3 × C3 (21) (22) –17– PRELIMINARY TECHNICAL DATA ADP3026 4. If critical signal lines (including the voltage and current sense lines of the ADP3026) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. 5. The PGND pin of the ADP3026 should connect first to a ceramic bypass capacitor on the VIN pin, and then into the power ground plane using the shortest possible trace. However, the power ground plane should not extend under other signal components, including the ADP3026 itself. If necessary, follow the preceding guideline to use the signal plane as a shield between the power ground plane and the signal circuitry. 6. The AGND pin of the ADP3026 should connect first to the REF capacitor, and then into the signal ground plane. In cases where no signal ground plane can be used, short interconnections to other signal ground circuitry in the power converter should be used. 7. The output capacitors of the power converter should be connected to the signal ground plane even though power current flows in the ground of these capacitors. For this reason, it is advised to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane between the input and output capacitors. It is also advised to keep the planar interconnection path short (i.e., have input and output capacitors close together). 8. The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power. If the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. 9. Absolutely avoid crossing any signal lines over the switching power path loop, described below. help to minimize switching power dissipation in the upper FET. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower FET turns off in advance of the upper FET turning on (necessary to prevent crossconduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower FET, draws current through the inherent body-drain diode of the FET. The upper FET turns on, and the reverse recovery characteristic of the lower FET’s body-drain diode prevents the drain voltage from being pulled high quickly. The upper FET then conducts very large current while it momentarily has a high voltage forced across it, which translates into added power dissipation in the upper FET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower FET is turned off, and by virtue of its essentially nonexistent reverse recovery time. 12. Whenever a power-dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias (if it is a current path), and improved thermal performance, especially if the vias are extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 13. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the output capacitors, and back to the input capacitors. Power Circuitry 10. The switching power path should be routed on the PCB to encompass the smallest possible area in order to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precaution often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the two FETs (and the power Schottky diode if used), including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause highenergy ringing, and it accommodates the high current demand with minimal voltage loss. 11. A power Schottky diode (1 ~ 2 A dc rating) placed from the lower FET’s source (anode) to drain (cathode) will 14. For best EMI containment, the power ground plane should extend fully under all the power components except the output capacitors. These are: the input capacitors, the power MOSFETs and Schottky diode, the inductor, and any snubbing elements that might be added to dampen ringing. Avoid extending the power ground under any other circuitry or signal lines, including the voltage and current sense lines. Signal Circuitry 15. The CS and SW traces should be Kelvin-connected to the upper MOSFET drain and source so that the additional voltage drop due to current flow on the PCB at the current sense comparator connections does not affect the sensed voltage. It is desirable to have the ADP3026 close to the output capacitor bank and not in the output power path, so that any voltage drop between the output capacitors and the AGND pin is minimized, and voltage regulation is not compromised. –18– REV. PrB PRELIMINARY TECHNICAL DATA ADP3026 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE REV. PrB 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) –19– 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50)