27BV CY62127BV 64K x 16 Static RAM Features • 2.7V–3.6V operation • CMOS for optimum speed/power • Low active power (70 ns, LL version) — 54 mW (max.) (15 mA) • Low standby power (70 ns, LL version) — 54 µW (max.) (15 µA) • Automatic power-down when deselected — Power down either with CE or BHE and BLE HIGH • Independent control of Upper and Lower Bytes • Available in 44-pin TSOP II (forward) and fBGA Functional Description The CY62127BV is a high-performance CMOS Static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption by 99% when deselected. The device enters power-down mode when CE is HIGH or when CE is LOW and both BLE and BHE are HIGH. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY62127BV is available in standard 44-pin TSOP Type II (forward pinout) and fBGA packages. Logic Block Diagram Pin Configurations TSOP II (Forward) Top View SENSE AMPS A12 A11 A10 A9 A7 A6 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 64K x 16 RAM Array 1024 X 1024 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A4 A5 A8 A13 A14 A15 BHE WE CE OE BLE Cypress Semiconductor Corporation Document #: 38-05155 Rev. ** • 3901 North First Street • San Jose • 1 44 2 3 4 43 42 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC CA 95134 • 408-943-2600 Revised September 6, 2001 CY62127BV Pin Configurations (continued) fBGA 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O9 BHE A3 A4 CE I/O1 B I/O10 I/O11 A5 A6 I/O 2 I/O 3 C VSS I/O12 NC A7 I/O4 VCC D VCC I/O13 NC NC I/O 5 VSS E I/O15 I/O14 A14 A15 I/O6 I/O7 F I/O16 NC A12 A13 WE I/O8 G NC A8 A9 A10 A11 NC H 62127BV–3 Selection Guide 62127BV-55 62127BV-70 Units Maximum Access Time 55 70 ns Maximum Operating Current 20 15 mA Maximum CMOS Standby Current 15 15 µA Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Industrial Ambient Temperature[2] VCC –40°C to +85°C 2.7V–3.6V DC Input Voltage[1] ................................–0.5V to VCC + 0.5V Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. Document #: 38-05155 Rev. ** Page 2 of 11 CY62127BV Electrical Characteristics Over the Operating Range 62127BV–55, 70 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –1.0 mA VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current GND ≤ VI ≤ VCC IOZ Output Leakage Current GND ≤ VI ≤ VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE ≥ VIH VIN ≥ VIH or VIN ≤ VIL, f = fMAX ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f=0 Typ.[3] Min. Max. Unit 2.2 V 0.4 V 2.0 VCC + 0.3 V –0.3 0.4 V –1 +1 µA –1 +1 µA 55 ns 20 mA 70 ns 15 mA 2 mA 15 µA 0.5 Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 9 pF 9 pF TA = 25°C, f = 1 MHz, VCC = 3.3V AC Test Loads and Waveforms R1 1076Ω 3.0V R1 1076 Ω 3.0V OUTPUT ALL INPUT PULSES VCC OUTPUT 30 pF R2 1262 Ω INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THÉVENIN EQUIVALENT R2 1262 Ω 5 pF INCLUDING JIG AND SCOPE 581 Ω GND Rise Time: 1 V/ns (b) 90% 10% 90% 10% Fall Time 1 V/ns 1.62V 62127BV-4 Notes: 3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25°C, VCC=3.0V). Parameters are guaranteed by design and characterization, and not 100% tested. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05155 Rev. ** Page 3 of 11 CY62127BV Switching Characteristics[5] Over the Operating Range Parameter Description 62127BV–55 62127BV–70 Min. Min. Max. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z 55 55 [7] 10 OE HIGH to High Z tLZCE CE LOW to Low Z[7] 70 20 ns 25 10 20 ns ns 5 10 [6, 7] ns 10 5 [6, 7] tHZOE 70 ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 55 70 ns tDBE Byte Enable to Data Valid 55 70 ns 0 [7] tLZBE Byte Enable to LOW Z tHZBE 0 5 [6, 7] Byte Disable to HIGH Z 25 ns 5 20 ns ns 25 ns [8] WRITE CYCLE tWC Write Cycle Time 55 70 ns tSCE CE LOW to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 40 50 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low Z[7] 5 5 ns [6, 7] tHZWE WE LOW to High Z tBW Byte Enable to End of Write 25 45 25 60 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZWE is less than tLZWE, and tHZBE is less than tLZBE, for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Refer to truth table for further conditions from BHE and BLE. Document #: 38-05155 Rev. ** Page 4 of 11 CY62127BV Data Retention Characteristics (Over the Operating Range for “L” and “LL” version only) Parameter Conditions[9] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[4] Chip Deselect to Data Retention Time Typ 2.0 VCC = VDR = 2.0V, CE > VCC-0.3V, VIN > VCC - 0.3V or, VIN < 0.3V. Operation Recovery Time tR Min. 0.5 Max. Unit 3.6 V 15 µA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V tCDR 3.0V tR CE 62127BV–5 Switching Waveforms Read Cycle No.1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 62127BV-6 Notes: 9. No input may exceed VCC + 0.3V. 10. Device is continuously selected. OE, CE, BHE, BLE = VIL. 11. WE is HIGH for read cycle. Document #: 38-05155 Rev. ** Page 5 of 11 CY62127BV Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[11, 12, 13] ADDRESS tRC CE tACE OE BHE, BLE tDBE tHZBE tLZBE DATA OUT tHZOE tDOE tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB 62127BV-7 Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS tSCE CE tSA tAW tHA BHE, BLE tBW tPWE WE tSD DATA I/O tHD DATA VALID 62127BV-8 Notes: 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH or BHE and BLE = VIH. 14. If CE, BHE, or BLE go HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05155 Rev. ** Page 6 of 11 CY62127BV Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE OE DATA I/O t HD t SD tHZOE DATAIN VALID NOTE 15 62127BV-9 Write Cycle No.3 (WE Controlled, OE LOW)[13, 14] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tBW BHE, BLE t tHZWE DATAI/O NOTE 15 tSD HD DATA VALID tLZWE 62127BV-10 Note: 15. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05155 Rev. ** Page 7 of 11 CY62127BV Truth Table CE OE WE BLE BHE H L I/O1–I/O8 I/O9–I/O16 Mode Power X X X X High Z High Z Power Down Standby (ISB) L H L L Data Out Data Out Read All Bits Active (ICC) L L H L H Data Out High Z Read Lower Bits Only Active (ICC) L L H H L High Z Data Out Read Upper Bits Only Active (ICC) L X L L L Data In Data In Write All Bits Active (ICC) L X L L H Data In High Z Write Lower Bits Only Active (ICC) L X L H L High Z Data In Write Upper Bits Only Active (ICC) L H H L L High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Power Down Standby (ISB) Ordering Information Speed (ns) 55 Ordering Code CY62127BVLL-55ZI CY62127BVLL-55BAI 70 CY62127BVLL-70ZI CY62127BVLL-70BAI Document #: 38-05155 Rev. ** Package Name Z44 BA48A Z44 BA48A Package Type 44-Lead TSOP II Operating Range Industrial 48-Ball Fine Pitch Ball Grid Array (fBGA) 44-Lead TSOP II 48-Ball Fine Pitch Ball Grid Array (fBGA) Page 8 of 11 CY62127BV Package Diagrams 48-Ball (7.00 mm x 7.00 mm) FBGA BA48A 51-85096-*D Document #: 38-05155 Rev. ** Page 9 of 11 CY62127BV Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A Document #: 38-05155 Rev. ** Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62127BV Document Title: CY62127BV 64K x 16 Static RAM Document Number: 38-05155 REV. ECN NO. Issue Date Orig. of Change ** 109899 01/10/02 SZV Document #: 38-05155 Rev. ** Description of Change Change from Spec number: 38-01018 to 38-05155 Page 11 of 11