LTC1065 DC Accurate, Clock-Tunable Linear Phase 5th Order Bessel Lowpass Filter U FEATURES DESCRIPTIO ■ The LTC®1065 is the first monolithic filter providing both clock-tunability with low DC output offset and over 12-bit DC accuracy. The frequency response of the LTC1065 closely approximates a 5th order Bessel polynomial. With appropriate PCB layout techniques the output DC offset is typically 1mV and is constant over a wide range of clock frequencies. With ±5V supplies and ±4V input voltage range, the CMR of the device is typically 80dB. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Clock-Tunable Cutoff Frequency 1mV DC Offset (Typical) 80dB CMR (Typical) Internal or External Clock 50µVRMS Clock Feedthrough 100:1 Clock-to-Cutoff Frequency Ratio 80µVRMS Total Wideband Noise 0.004% Noise + THD at 2VRMS Output Level 50kHz Maximum Cutoff Frequency Cascadable for Faster Roll-Off Operates from ±2.375 to ±8V Power Supplies Self-Clocking with 1 RC Available in 8-Pin DIP and 16-Pin SW Packages U APPLICATIO S ■ ■ ■ ■ ■ ■ ■ The filter cutoff frequency is controlled either by an internal or external clock. The clock-to-cutoff frequency ratio is 100 : 1. The on-board clock is nearly power supply independent and it is programmed via an external RC. The 50µVRMS clock feedthrough of the device is considerably lower than other existing monolithic filters. The LTC1065 wideband noise is 80µVRMS and it can process large AC input signals with low distortion. With ±7.5V supplies, for instance, the filter handles up to 4VRMS (94dB S/N ratio) while the standard 1kHz THD is below 0.005%; 87dB dynamic range (S/N + THD) is obtained with input levels between 2VRMS and 2.5VRMS. Audio Strain Gauge Amplifiers Anti-Aliasing Filters Low Level Filtering Digital Voltmeters Smoothing Filters Reconstruction Filters , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 4857860. The LTC1065 is available in 8-pin miniDIP and 16-pin SW packages. For a Butterworth response, see LTC1063 data sheet. The LTC1065 is pin compatible with the LTC1063. U TYPICAL APPLICATIO Frequency Response 10 3.4kHz Single 5V Supply Bessel Lowpass Filter 0 5V –10 + 1µF TANT 4.53k 1 8 2 7 0.1µF 3 LTC1065 VOUT 6 5 4 –20 5V 0.1µF GAIN (dB) 4.99k VIN –30 –40 –50 –60 –70 13k* 200pF* * SELF-CLOCKING SCHEME 1065 TA01 –80 –90 1 10 FREQUENCY (kHz) 100 1065 TA01b 1065fb 1 LTC1065 U W W W ABSOLUTE AXI U RATI GS (Note 1) Total Supply Voltage (V + to V –) .......................... 16.5V Power Dissipation ............................................. 400mW Voltage at Any Input .... (V – – 0.3V) ≤ VIN ≤ (V + + 0.3V) Burn-In Voltage ...................................................... 16V Storage Temperature Range ................ – 65°C to 150°C Operating Temperature Range (Note 7) LTC1065C .............................................. 0°C to 70°C LTC1065I ........................................... – 40°C to 85°C LTC1065M (OBSOLETE) .................. – 55°C to 125°C Lead Temperature (Soldering, 10 sec)................. 300°C U W U PACKAGE/ORDER I FOR ATIO TOP VIEW VIN 1 GND 2 V – 3 CLK OUT 4 8 VOS ADJ ORDER PART NUMBER TOP VIEW 7 VOUT 6 V + 5 CLK IN 16 VOS ADJ 15 NC 14 VOUT GND 3 LTC1065CN8 LTC1065IN8 V– LTC1065MJ8 12 5 V+ NC 6 11 NC NC 7 10 NC 9 CLK OUT 8 OBSOLETE PACKAGE LTC1065CSW LTC1065ISW 13 NC NC 4 N8 PACKAGE 8-LEAD PLASTIC DIP TJMAX = 100°C, θJA = 110°C/W (N) J8 PACKAGE 8-LEAD CERAMIC DIP TJMAX = 150°C, θJA = 100°C/W (J) NC 1 VIN 2 ORDER PART NUMBER CLK IN SW PACKAGE 16-LEAD PLASTIC SO WIDE TJMAX = 100°C, θJA = 85°C/W Consider the N Package for an Alernate Source Order Options Tape and Reel: Add #TR Lead Free: Add #PBF, Lead Free Tape and Reel: Add #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C unless otherwise specified. PARAMETER Clock-to-Cutoff Frequency Ratio (fCLK / fC) Maximum Clock Frequency (Note 2) Minimum Clock Frequency (Note 3) Input Frequency Range Filter Gain CONDITIONS ±2.375V ≤ VS ≤ ±7.5V VS = ±7.5V VS = ±5V VS = ±2.5V ±2.5V ≤ VS ≤ ±7.5V, TA < 85°C MIN TYP 100 ±0.5 5 4 3 30 0 VS = ±5V, fCLK = 25kHz, fC = 250Hz fIN = 250Hz fIN = 1kHz VS = ±5V, fCLK = 500kHz, fC = 5kHz fIN = 100Hz fIN = 1kHz = 0.2fC fIN = 2.5kHz = 0.5fC fIN = 4kHz = 0.8fC fIN = 5kHz = fC fIN = 10kHz = 2fC fIN = 20kHz = 4fC MAX UNITS MHz MHz MHz Hz 0.9fCLK ● ● – 3.5 – 43.0 – 3.1 – 41.0 – 2.7 – 39.0 dB dB ● – 0.215 – 1.1 – 2.35 – 3.35 – 14.5 – 43.0 0 – 0.175 – 0.972 – 2.13 – 3.1 – 14.15 – 41.15 – 0.135 – 0.84 – 1.9 – 2.7 – 13.0 – 39.0 dB dB dB dB dB dB dB ● ● ● ● ● 1065fb 2 LTC1065 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VS = ±5V, fCLK = 500kHz, fC = 5kHz, RL = 10k, TA = 25°C unless otherwise specified. PARAMETER Filter Gain Clock Feedthrough Wideband Noise (Note 4) THD + Wideband Noise (Note 5) Filter Output ± DC Swing CONDITIONS VS = ±2.375V, fCLK = 500kHz, fC = 5kHz fIN = 1kHz fIN = 2.5kHz fIN = 4kHz fIN = 5kHz fIN = 10kHz ±2.375V ≤ VS ≤ ±7.5V ±2.375V ≤ VS ≤ ±7.5V, 1Hz < f < fCLK VS = ±7.5V, fC = 20kHz, fIN = 1kHz, 2VRMS ≤ VIN ≤ 2.5VRMS VS = ±2.375V ● ● ● ● ● ● VS = ±5V ● VS = ±7.5V ● Input Bias Current Dynamic Input Impedance Output DC Offset (Note 6) Output DC Offset Drift Self-Clocking Frequency (fOSC) External CLK Pin Logic Thresholds Power Supply Current VS = ±2.375V VS = ±5V VS = ±7.5V VS = ±2.375V VS = ±5V VS = ±7.5V R (Pin 4 to 5) = 20k, C (Pin 5 to GND) = 470pF VS = ±2.375V LTC1065C LTC1065M VS = ±5V LTC1065C LTC1065M VS = ±7.5V LTC1065C LTC1065M VS = ±2.375V Min Logical “1” Max Logical “0” VS = ±5V Min Logical “1” Max Logical “0” VS = ±7.5V Min Logical “1” Max Logical “0” VS = ±2.375V, fCLK = 500kHz LTC1065C LTC1065M VS = ±5V, fCLK = 500kHz LTC1065C LTC1065M VS = ±7.5V, fCLK = 500kHz LTC1065C LTC1065M MIN TYP MAX – 0.225 – 1.1 – 2.35 – 3.35 – 14.5 – 0.185 – 1.0 – 2.15 – 3.1 –14.1 50 80 – 87 – 0.145 – 0.83 – 1.9 – 2.7 –13.0 1.5/– 2.0 1.3/– 1.8 4.0/– 4.5 3.8/– 4.3 6.5/– 7.0 6.3/– 6.8 ● ● ● ● ● ● 99 95 92 100 98 97 102 101 100 4.3/– 4.8 6.8/– 7.3 103 103 100 106 106 105 106 109 108 1.43 0.47 3 1 4.5 1.5 2.5 ● ● 5.5 ● ● 7.0 ● ● dB dB dB dB dB µVRMS µVRMS dB 1.7/– 2.2 10 800 2 0 –4 10 20 25 UNITS ±5 112 112 112 112 114 114 114 116 116 4.0 5.5 6.0 9 11 12 12.0 14.5 16.0 V V V V V V nA MΩ mV mV mV µV/°C µV/°C µV/°C kHz kHz kHz kHz kHz khz kHz kHz kHz V V V V V V mA mA mA mA mA mA mA mA mA 1065fb 3 LTC1065 ELECTRICAL CHARACTERISTICS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The maximum clock frequency is arbitrarily defined as the frequency at which the filter AC response exhibits ≥ 1dB of gain peaking. Note 3: At limited temperature ranges (i.e., TA ≤ 50°C) the minimum clock frequency can be as low as 10Hz. The typical minimum clock frequency is arbitrarily defined as the clock frequency at which the output DC offset changes by more than 1mV. Note 4: The wideband noise specification does not include the clock feedthrough. Note 5: To properly evaluate the filter’s harmonic distortion an inverting output buffer is recommended. An output buffer (although recommended) is not necessarily needed when measuring output DC offset or wideband noise (see Figure 3). Note 6: The output DC offset is optimized for ±5V supply. The output DC offset shifts when the power supplies change; however, this phenomenon is repeatable and predictable. Note 7: The LTC1065C is guaranteed to meet the specified performance from 0°C to 70°C and is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. The LTC1065I is guaranteed to meet specified performance from –40°C to 85°C. U W TYPICAL PERFOR A CE CHARACTERISTICS Output Offset vs Clock, Low Clock Rates Self-Clocking Frequency vs R 110 5 50 45 LTC1065 40 5 4 80 R C = 200pF fOSC ≅ 1/RC 70 C 60 50 40 OUTPUT OFFSET (mV) 90 25 20 15 10 5 300 FREQUENCY (kHz) 0 500 1 Gain vs Frequency; VS = ±2.5V –1 –2 A 10 –5 110 EXTERNAL CLOCK FREQUENCY (Hz) 210 Gain vs Frequency; VS = ±5V Gain vs Frequency; VS = ±7.5V 0 0 –10 –10 –20 –20 –20 A. fCLK = 0.5MHz B. fCLK = 1MHz C. fCLK = 2MHz –60 –30 A –40 B C D A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz –50 –60 VIN = 750mVRMS TA = 25°C 10 INPUT FREQUENCY (kHz) 100 200 1065 G04 E –30 A. fCLK = 1MHz B. fCLK = 2MHz C. fCLK = 3MHz D. fCLK = 4MHz E. fCLK = 5MHz –40 –50 VIN = 1.4VRMS TA = 25°C –80 –90 1 B C –70 VIN = 1.4VRMS TA = 25°C –80 –90 A –60 –70 –70 –80 D GAIN (dB) –50 GAIN (dB) –40 500 1000 EXTERNAL CLOCK FREQUENCY (kHz) 10 –10 C 0 1065 G03 0 B VS = ±2.5V –4 10 A VS = ±5V 0 1065 G02 10 GAIN (dB) 2 –3 B 1065 G01 –30 VS = ±7.5V 3 30 20 100 4 A. TA = 25°C B. TA = 85°C 35 30 10 VS = ±5V OUTPUT OFFSET (mV) 100 R PINS 4 TO 5 (kΩ) Output Offset vs Clock, Medium Clock Rates –90 1 10 INPUT FREQUENCY (kHz) 100 200 1065 G05 1 10 INPUT FREQUENCY (kHz) 100 200 1065 G06 1065fb 4 LTC1065 U W TYPICAL PERFOR A CE CHARACTERISTICS THD vs Frequency; VS = Single 5V, AGND = 2V THD + Noise vs Input Voltage; VS = Single 5V, AGND = 2V 1 1 1 fIN = 1kHz, TA = 25°C fIN = 1kHz, TA = 25°C 0.1 THD + NOISE (%) VIN = 0.75VRMS, S/N = 80dB fC = 5kHz, fCLK = 500kHz TA = 25°C 0.1 THD (%) THD + NOISE (%) THD + Noise vs Input Voltage; VS = ±5V B A 0.01 0.01 0.1 B 0.01 A A. fC = 10kHz, fCLK = 1MHz B. fC = 20kHz, fCLK = 2MHz A. fC = 5kHz, fCLK = 0.5MHz B. fC = 10kHz, fCLK = 1MHz 0.001 0.001 0.1 1 1 5 2 3 FREQUENCY (kHz) INPUT (VRMS) 4 5 0.001 0.1 1 INPUT (VRMS) 1065 G09 1065 G08 1065 G07 THD vs Frequency; VS = ±7.5V THD + Noise vs Input Voltage; VS = ±7.5V THD vs Frequency; VS = ±5V 1 1 1 fIN = 1kHz TA = 25°C THD (%) 0.01 VIN = 2.5VRMS, S/N = 90dB fC = 10kHz, fCLK = 1MHz TA = 25°C 0.1 0.1 THD (%) THD + NOISE (%) VIN = 1.5VRMS fC = 10kHz, fCLK = 1MHz TA = 25°C 0.1 5 B 0.01 0.01 A A. fC = 10kHz, fCLK = 1MHz B. fC = 20kHz, fCLK = 2MHz 0.001 0.001 0.1 10 5 FREQUENCY (kHz) 1 0 –40 –1 PHASE B B –80 PHASE –3 –120 –4 –160 fC =1kHz fCLK =100kHz fC =10kHz fCLK =1MHz 1k 10k INPUT FREQUENCY (Hz) –40°C 0.3 0.2 0.1 –240 100k 0 1065 G13 15 VS = ± 7.5V VIN = 1VRMS fC = 20kHz fCLK = 2MHz 0.4 –200 –5 –6 100 PHASE MISMATCH (±DEG) 0.5 PHASE (DEG) PASSBAND GAIN (dB) 0 A Power Supply Current vs Power Supply Voltage 0.6 40 10 5 FREQUENCY (kHz) 1065 G12 Typical Phase Matching Device to Device ±2.5V ≤ VS ≤ ±7.5V, TA = 25°C A 1 1065 G11 Passband Gain and Phase vs Input Frequency –2 0.001 INPUT (VRMS) 1065 G10 1 5 POWER SUPPLY CURRENT (mA) 1 0 2 4 6 8 10 12 14 16 18 20 22 24 INPUT FREQUENCY (kHz) 1065 G14 12 25°C 9 85°C 6 3 0 0 2 4 6 8 10 12 14 16 18 20 TOTAL POWER SUPPLY VOLTAGE (V) 1065 G15 1065fb 5 LTC1065 U W TYPICAL PERFOR A CE CHARACTERISTICS Transient Response Group Delay 45 40 GROUP DELAY (µs) 35 30 25 20 15 10 VS = ±5V fC = 10kHz 5 0 0 HORIZONTAL: 0.1ms/DIV, VERTICAL: 2V/DIV VS = ±5V, fC = 10kHz, VIN = 1kHz ±3VP SQUARE WAVE 3 12 6 9 15 INPUT FREQUENCY (kHz) 18 21 1065 G17 1065 G16 U U U PI FU CTIO S Power Supply Pins (Pins 6, 3, N Package) The positive and negative supply pin should be bypassed with a high quality 0.1µF ceramic capacitor. In applications where the clock pin (5) is externally swept to provide several cutoff frequencies, the output DC offset variation is minimized by connecting an additional 1µF solid tantalum capacitor in parallel with the 0.1µF disc ceramic. This technique was used to generate the graphs of the output DC offset variation versus clock; they are illustrated in the Typical Performance Characteristics section. When the power supply voltage exceeds ±7V, and when V – is applied before V + (if V+ is allowed to go below ground) connect a signal diode between the positive supply pin and ground to prevent latch-up (see Typical Applications). Ground Pin (Pin 2, N Package) degrade DC offset and it will increase clock feedthrough, noise and distortion. A small amount of AC current flows out of the ground pin whether or not the internal oscillator is used. The frequency of the ground current equals the frequency of the clock. The average value of this current is approximately 55µA, 110µA, 170µA for ±2.5V, ±5V and ±7.5V supplies respectively. For single supply operation, the ground pin should be preferably biased at half supply (see Typical Applications). VOS Adjust Pin (Pin 8, N Package) The VOS adjust pin can be used to trim any small amount of output DC offset voltage or to introduce a desired output DC level. The DC gain from the VOS adjust pin to the filter output pin equals two. Any DC voltage applied to this pin will reflect at the output pin of the filter multiplied by two. The ground pin merges the internal analog and digital ground paths. The potential of the ground pin is the reference for the internal switched-capacitor resistors, and the reference for the external clock. The positive input of the internal op amp is also tied to the ground pin. If the VOS adjust pin is not used, it should be shorted to the ground pin. The DC bias current flowing into the VOS adjust pin is typically 10pA. For dual supply operation, the ground pin should be connected to a high quality AC and DC ground. A ground plane, if possible, should be used. A poor ground will The VOS adjust pin should always be connected to an AC ground; AC signals applied to this pin will degrade the filter response. 1065fb 6 LTC1065 U U U PI FU CTIO S Input Pin (Pin 1, N Package) Pin 1 is the filter input and it is connected to an internal switched-capacitor resistor. If the input pin is left floating, the filter output will saturate. The DC input impedance of pin 1 is very high; with ±5V supplies and 1MHz clock, the DC input impedance is typically 1GΩ. A resistor RIN in series with the input pin will not alter the value of the filter’s DC output offset (Figure 1). RIN should however, be limited to a maximum value (Table 1), otherwise the filter’s passband will be affected. Refer to the Applications Information section for more details. RIN 1 8 7 2 V – 3 LTC1065 VOUT 6 POWER SUPPLY VS = ±2.5V VS = ±5V VS = ±7.5V VS = ±8V VS = 5V, 0V VS = 12V, 0V VS =15V, 0V VHIGH 1.5V 3V 4.5V 4.8V 4V 9.6V 12V VLOW 0.5V 1V 1.5V 1.6V 3V 7.2V 9V Clock Output Pin (Pin 4, N Package) V+ 5 f CLK 4 Table 2. Clock Pin Threshold Levels 1065 F01 Figure 1. Table 1. RIN(MAX) vs Clock and Power Supply RIN(MAX) VS = ±7.5V VS = ±5V VS = ±2.5V fCLK = 4MHz 1.82k – – fCLK = 3MHz 3.01k 2.49k – fCLK = 2MHz fCLK = 1MHz fCLK = 500kHz fCLK = 100kHz 4.32k 9.09k 17.8k 95.3k 3.65k 8.25k 16.9k 90.9k 2.37k 7.5k 16.9k 90.9k Output Pin (Pin 7, N Package) Pin 7 is the filter output. This pin can typically source over 20mA and sink 2mA. Pin 7 should not drive long coax cables, otherwise the filter’s total harmonic distortion will degrade. The maximum load the filter output can drive and still maintain the distortion levels, shown in the Typical Performance Characteristics, is 20k. Clock Input Pin (Pin 5, N Package) An external clock, when applied to pin 5, tunes the filter cutoff frequency. The clock-to-cutoff frequency ratio is Any external clock applied to the clock input pin appears at the clock output pin. The duty cycle of the clock output equals the duty cycle of the external clock applied to the clock input pin. The clock output pin swings to the power supply rails. When the LTC1065 is used in a self-clocking mode, the clock of the internal oscillator appears at the clock output pin with a 30% duty cycle. The clock output pin can be used to drive other LTC1065s or other ICs. The maximum capacitance, CL(MAX), the clock output pin can drive is illustrated in Figure 2. 200 MAXIMUM LOAD CAPACITANCE (pF ) VIN 100:1. The high (VHIGH) and low (VLOW) clock logic threshold levels are illustrated in Table 2. Square wave clocks with duty cycles between 30% and 50% are strongly recommended. Sinewave clocks are not recommended. VS = ±2.5V 180 TA = 25°C 160 140 120 VS = ±5V 100 VS = ±7.5V 80 60 40 20 0 1 3 2 4 5 6 7 8 9 10 CLOCK FREQUENCY (MHz) 1065 F02 Figure 2. Maximum Load Capacitance at the Clock Output Pin 1065fb 7 LTC1065 TEST CIRCUIT + VOUT LT1022 VIN 1 8 2 7 3 V– LTC1065 4 – 50k 50k 6 V+ 5 0.1µF 20pF 0.1µF CLOCK IN 1065 F03 Figure 3. Test Circuit for THD W U U UO APPLICATI S I FOR ATIO Self-Clocking Operation The LTC1065 features an internal oscillator which can be tuned via an external RC. The LTC1065’s internal oscillator is primarily intended for generation of clock frequencies below 500kHz. The first curve of the Typical Performance Characteristics section shows how to quickly choose the value of the RC for a given frequency. More precisely, the frequency of the internal oscillator is equal to: fCLK = K/RC For clock frequencies (fCLK) below 100kHz, K equals 1.07. Figure 4b shows the variation of the parameter K versus clock frequency and power supply. First choose the desired clock frequency (fCLK < 500kHz), then through Figure 4b pick the right value of K, set C = 200pF and solve for R. Note a 4pF parasitic capacitance is assumed in parallel with the external 200pF timing capacitor. Figure 5 shows the clock frequency variation from – 40°C to 85°C. The 200kHz clock of Example 1 will change by –1.75% at 85°C. For a limited temperature range, the internal oscillator of the LTC1065 can be used to generate clock frequencies above 500kHz (Figures 6 and 7). The data of Figure 6 is derived from several devices. For a given external (RC) value, the observed device-to-device clock frequency variation was ±1% (VS = ±5V), and ±1.25% for VS = ±2.5V. fCUTOFF = 20kHz, fCLK = 2MHz, VS = ±7.5V, TA = 25°C, C = 10pF from Figure 6, K = 0.575, and, R = (0.575)/(2MHz × 14pF) = 20.5k. Example 2: Example 1: fCUTOFF = 2kHz, fCLK = 200kHz, VS = ±5V, TA = 25°C, K = 1.0, C = 200pF then, 1.25 1.20 R = (1.0)/(200kHz × 204pF) = 24.5k. 1.15 fCLK = K/RC C = 200pF TA = 25°C 1.10 K 1.05 VIN 8 1 VS = ±7.5V 0.95 7 2 V– 1.00 3 LTC1065 6 VOUT 0.90 V+ 0.85 0.75 R VS = ±2.5V 0.80 5 4 VS = ±5V C 100 300 400 500 200 INTERNAL CLOCK FREQUENCY (kHz) 1065 F04b 1065 F04a Figure 4a. Figure 4b. fCLK vs K 1065fb 8 LTC1065 W U U UO APPLICATI S I FOR ATIO 4 C = 200pF fCLK CHANGE NORMALIZED TO ITS 25°C VALUE (%) 3 2 A 4pF parasitic capacitance is assumed in parallel with the external 10pF capacitor. A ±1% clock frequency variation from device to device can be expected. The 2MHz clock frequency designed above will typically drift to 1.74MHz at 70°C (Figure 7). TA = –40°C VS = ±5V VS = ±2.5V 1 VS = ±7.5V 0 TA = 85°C –1 The internal clock of the LTC1065 can be overridden by an external clock provided that the external clock source can drive the timing capacitor C, which is connected from the clock input pin to ground. VS = ±7.5V –2 VS = ±5V VS = ±2.5V –3 –4 100 300 400 200 CLOCK FREQUENCY (kHz) 0 500 Output Offset 1065 F05 The DC output offset of the LTC1065 is trimmed to typically less than ±1mV. The trimming is done at VS = ±5V. To obtain optimum DC offset performance, appropriate PC layout techniques should be used and the filter IC should be soldered to the PC board. A socket will degrade the output DC offset by typically 1mV. The output DC offset is sensitive to the coupling of the clock output pin 4 (N package) to the negative power supply pin 3 (N package). The negative supply pin should be well decoupled. When the surface mount package is used, all NC pins should be grounded. When the output DC voltage is measured with a voltmeter, the filter output pin should be buffered. Long test leads should be avoided. Figure 5. fCLK vs Temperature 0.80 fCLK = K/RC C = 10pF TA = 25°C 0.75 0.70 K 0.65 VS = ±7.5V 0.60 VS = ±5V 0.55 0.50 VS = ±2.5V 0.45 0.40 0.5 1.0 2.0 2.5 1.5 CLOCK FREQUENCY (MHz) 3.0 1065 F06 Figure 6. fCLK vs K 0.80 fCLK = K/RC C = 10pF TA = 70°C 0.75 0.70 Common Mode Rejection The common mode rejection is defined as the change of the output DC offset with respect to the DC change of the input voltage applied to the filter. K 0.65 0.60 VS = ±7.5V 0.55 VS = ±5V 0.50 0.45 0.40 0.5 CMR = 20log (∆VOS OUT /∆VIN)(dB) VS = ±2.5V 1.0 2.0 2.5 1.5 CLOCK FREQUENCY (MHz) With fixed power supplies, the output DC offset should not change by more than ±100µV over 10Hz to 1MHz clock frequency variation. When the filter clock frequency is fixed, the output DC offset will typically change by – 4mV (2mV) when the power supply varies from ±5V to ±7.5V (±2.5V). See Typical Performance Characteristics. 3.0 1065 F07 Table 3 illustrates the common mode rejection for three power supplies and three temperatures. The common mode rejection improves if the output offset is adjusted to approximately 0V. The output offset can be adjusted via pin 8 (N package). See Typical Applications. Figure 7. fCLK vs K 1065fb 9 LTC1065 U W U UO APPLICATI S I FOR ATIO ∆VIN – 40°C 25°C 85°C 25°C (VOS Nulled) ±1.8V 84dB 83dB 80dB 83dB ±5V ±4V 82dB 78dB 77dB 78dB ±7.5V ±6V 80dB 77dB 76dB 80dB POWER SUPPLY ±2.5V 5mV/DIV Table 3. CMR Data, fCLK = 100kHz The above data is valid for clock frequencies up to 800kHz, 900kHz, 1MHz, for VS = ±2.5V, ±5V, ±7.5V respectively. Clock Feedthrough 2µs/DIV fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW Figure 8. LTC1065 Output Clock Feedthrough + Noise 2µs/DIV fCLK = 100kHz, fC = 1kHz, VS = ±5V, 1MHz SCOPE BW Wideband Noise The wideband noise data is used to determine the operating signal-to-noise ratio at a given distortion level. The wideband noise (µVRMS) is nearly independent of the value of the clock frequency and excludes the clock feedthrough. The LTC1065’s typical wideband noise is 80µVRMS. Figure 9 shows the same scope photo as Figure 8 but with a more sensitive vertical scale. The clock feedthrough is imbedded in the filter’s wideband noise. The peak-to-peak wideband noise of the filter can be clearly seen; it is approximately 420µVP-P. Note that 420µVP-P equals the 80µVRMS wideband noise of the part multiplied by a crest factor of 5.25. 1065F08 0.5mV/DIV Clock feedthrough is defined as the RMS value of the clock frequency and its harmonics which are present at the filter’s output pin. The clock feedthrough is tested with the filter input grounded and it depends on the quality of the PC board layout and power supply decoupling. Any parasitic switching transients during the rise and fall of the incoming clock, are not part of the clock feedthrough specifications; their amplitude strongly depends on scope probing techniques as well as ground quality and power supply bypassing. For a power supply VS = ±5V, the clock feedthrough of the LTC1065 is 50µVRMS; for VS = ±7.5V, the clock feedthrough approaches 75µVRMS. Figures 8 and 9 show a typical scope photo of the LTC1065 output pin when the input pin is grounded. The filter cutoff frequency was 1kHz, while scope bandwidth was chosen to be 1MHz so that switching transients above the 100kHz clock frequency would show. 1063 F09 Figure 9. LTC1065 Output Clock Feedthrough + Noise Aliasing Aliasing is an inherent phenomenon of sampled data filters. It primarily occurs when the frequency of an input signal approaches the sampling frequency. For the LTC1065, an input signal whose frequency is in the range of fCLK ±6% will generate an alias signal into the filter’s passband and stopband. Table 4 shows details. Example: LTC1065, fCLK = 20kHz, fC = 200kHz, fIN = (19.6kHz, 100mVRMS) fALIAS = (400Hz, 3.16mVRMS) 1065fb 10 LTC1065 U W U UO APPLICATI S I FOR ATIO Table 4. Aliasing Data INPUT FREQUENCY OUTPUT FREQUENCY 0.9995 fCLK 0.995 fCLK 0.99 fCLK 0.9875 fCLK 0.985 fCLK 0.9825 fCLK 0.98 fCLK 0.975 fCLK 0.97 fCLK 0.965 fCLK 0.96 fCLK 0.955 fCLK 0.95 fCLK 0.94 fCLK 0.93 fCLK 0.9 fCLK 0.0005 fCLK 0.005 fCLK 0.01 fCLK 0.0125 fCLK 0.015 fCLK 0.0175 fCLK 0.02 fCLK 0.025 fCLK 0.03 fCLK 0.035 fCLK 0.04 fCLK 0.045 fCLK 0.05 fCLK 0.06 fCLK 0.07 fCLK 0.1 fCLK OUTPUT AMPLITUDE REFERENCED TO INPUT SIGNAL – 0.01 – 0.98 – 3.13 – 4.79 – 7.21 – 10.43 – 14.14 – 21.84 – 28.98 – 35.31 – 40.94 – 45.96 – 50.46 – 58.29 – 64.90 – 80.20 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB An input RC can be used to attenuate incoming signals close to the filter clock frequency (Figure 10). A Bessel passband response will be maintained if the value of the input resistor follows Table 1. R 8 1 VIN C 3 V– 0.1µF 7 2 4 LTC1065 VOUT 6 5 V+ fCLK fCLK 1 f ≤ ≤ CLK 20 2πRC 10 0.1µF 1065 F10 Figure 10. Adding an Input Anti-Aliasing RC 1065fb 11 LTC1065 U TYPICAL APPLICATIO S Cascading Two LTC1065s for Steeper Roll-Off VIN 8 1 3 0.1µF VIN LTC1065 6 5V 5 4 2 7 3 –5V 0.1µF 4 0.1µF 7 5 5V 0.1µF 0.1µF 4 C 8 1 3 –5V 5V 0.1µF 5 7 2 VOUT VOUT 6 R VIN 6 LTC1065 4 C 8 LTC1065 3 –5V 0.1µF R 1 8 1 2 7 2 –5V Sharing Clock for Multichannel Applications LTC1065 6 5 VOUT 5V 0.1µF 1065 TA03 fC ≅ (1/RC)(1/100) WIDEBAND NOISE = 110µVRMS ATTENUATION AT f = 2fC = 60dB 1065 TA02 1065fb 12 LTC1065 U PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) CORNER LEADS OPTION (4 PLCS) .023 – .045 (0.584 – 1.143) HALF LEAD OPTION .045 – .068 (1.143 – 1.650) FULL LEAD OPTION .005 (0.127) MIN .405 (10.287) MAX 8 7 6 5 .025 (0.635) RAD TYP .220 – .310 (5.588 – 7.874) 1 .300 BSC (7.62 BSC) 2 3 4 .200 (5.080) MAX .015 – .060 (0.381 – 1.524) .008 – .018 (0.203 – 0.457) 0° – 15° NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS .045 – .065 (1.143 – 1.651) .014 – .026 (0.360 – 0.660) .100 (2.54) BSC .125 3.175 MIN J8 0801 OBSOLETE PACKAGE 1065fb 13 LTC1065 U PACKAGE DESCRIPTIO N Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) ( +.035 .325 –.015 8.255 +0.889 –0.381 ) .045 – .065 (1.143 – 1.651) .130 ± .005 (3.302 ± 0.127) .065 (1.651) TYP .100 (2.54) BSC .120 (3.048) .020 MIN (0.508) MIN .018 ± .003 (0.457 ± 0.076) N8 1002 NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1065fb 14 LTC1065 U PACKAGE DESCRIPTIO SW Package 16-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP .398 – .413 (10.109 – 10.490) NOTE 4 16 N 15 14 13 12 11 10 9 N .325 ±.005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT 1 .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.737) 3 4 5 6 .093 – .104 (2.362 – 2.642) 7 8 .037 – .045 (0.940 – 1.143) 0° – 8° TYP NOTE 3 .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 2 .050 (1.270) BSC .004 – .012 (0.102 – 0.305) .014 – .019 (0.356 – 0.482) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) S16 (WIDE) 0502 1065fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1065 U TYPICAL APPLICATIO S Adjusting VOS(OUT) for ±7.5 Supply Operation Single 5V Supply Operation (fC = 3.4kHz) 7.5V 5V 4.99k + 1µF TANT 4.53k VIN 0.1µF 1 8 2 7 3 LTC1065 10k 10k VOUT LT1009 6 5V 13k VIN 0.1µF 5 4 200pF V– 1 8 2 7 3 LTC1065 ≅2.5mV VOUT V+ 7.5V 6 –7.5V 1065 TA04 1µF TANT 4 + 5 0.1µF fCLK 0.1µF * * OPTIONAL, 1N4148 1065 TA05 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1063 Clock Tunable, 5th Order Bessel Low Pass Internal or External Clock, 1mVDC Offset, Cascadable LTC1064-1/2/3/4/7 Clock Tunable, 8th Order Low Pass Elliptic, Butterworth, Bessel, Cauer or Linear Phase LTC1164-5/6/7 Clock Tunable, Low Power, 8th Order Low Pass Butterworth, Bessel or Elliptic, FO Max = 20KHz LTC1264-7 Clock Tunable, 8th Order Low Pass Flat Group Delay, FO Max = 200KHz, Steeper Roll-Off than Bessel LTC1569-6/7 Clock Tunable, 10th Order Low Pass Internal or External Clock, Root Raised Cosine Response 1065fb 16 Linear Technology Corporation LT/LT 0705 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 1993