LTC2225 12-Bit, 10Msps Low Power 3V ADC U FEATURES DESCRIPTIO ■ The LTC®2225 is a 12-bit 10Msps, low power 3V A/D converter designed for digitizing high frequency, wide dynamic range signals. The LTC2225 is perfect for demanding imaging and communications applications with AC performance that includes 71.3dB SNR and 90dB SFDR for signals well beyond the Nyquist frequency. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Sample Rate: 10Msps Single 3V Supply (2.7V to 3.4V) Low Power: 60mW 71.3dB SNR 90dB SFDR No missing codes Flexible Input: 1VP-P to 2VP-P Range 575MHz Full Power Bandwidth S/H Clock Duty Cycle Stabilizer Shutdown and Nap Modes Pin Compatible Family 125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) 105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) 80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) 65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) 40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) 25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit) 10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) 32-Pin (5mm × 5mm) QFN Package DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 0.25LSBRMS. A single 3V supply allows low power operation. A separate output supply allows the outputs to drive 0.5V to 3.6V logic. A single-ended CLK input controls converter operation. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. , LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U APPLICATIO S ■ ■ ■ ■ Wireless and Wired Broadband Communication Imaging Systems Spectral Analysis Portable Instrumentation U TYPICAL APPLICATIO Typical INL, 2V Range REFH REFL 1.0 FLEXIBLE REFERENCE 0.8 OVDD ANALOG INPUT INPUT S/H – 12-BIT PIPELINED ADC CORE CORRECTION LOGIC D11 • • • D0 OUTPUT DRIVERS OGND INL ERROR (LSB) + 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 CLOCK/DUTY CYCLE CONTROL –0.8 –1.0 2225 TA01 CLK 0 1024 2048 CODE 3072 4096 2225 G01 2225fa 1 LTC2225 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO OVDD = VDD (Notes 1, 2) Supply Voltage (VDD) ................................................. 4V Digital Output Ground Voltage (OGND) ....... –0.3V to 1V Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) Digital Input Voltage .................... –0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation ............................................ 1500mW Operating Temperature Range LTC2225C ............................................... 0°C to 70°C LTC2225I .............................................–40°C to 85°C Storage Temperature Range ..................–65°C to 125°C D9 D10 D11 OF MODE SENSE VCM VDD TOP VIEW 32 31 30 29 28 27 26 25 AIN+ 1 24 D8 AIN– 2 23 D7 REFH 3 22 D6 REFH 4 21 OVDD 33 REFL 5 20 OGND REFL 6 19 D5 VDD 7 18 D4 GND 8 17 D3 D2 D1 D0 NC NC OE CLK SHDN 9 10 11 12 13 14 15 16 UH PACKAGE 32-LEAD (5mm × 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD IS GND (PIN 33) MUST BE SOLDERED TO PCB QFN PART MARKING 2225* ORDER PART NUMBER LTC2225CUH LTC2225IUH Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. U CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS Resolution (No Missing Codes) MIN ● 12 TYP MAX UNITS Bits Integral Linearity Error Differential Analog Input (Note 5) ● –1.1 ±0.3 1.1 LSB Differential Linearity Error Differential Analog Input ● –0.7 ±0.15 0.7 LSB Offset Error (Note 6) ● –12 ±2 12 mV Gain Error External Reference ● –2.5 ±0.5 2.5 %FS ±10 µV/°C Internal Reference ±30 ppm/°C External Reference ±5 ppm/°C 0.25 LSBRMS Offset Drift Full-Scale Drift Transition Noise SENSE = 1V 2225fa 2 LTC2225 U U A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VIN Analog Input Range (AIN+ CONDITIONS 2.7V < VDD < 3.4V (Note 7) ● VIN,CM Analog Input Common Mode(AIN+ +AIN–)/2 Differential Input (Note 7) Single Ended Input (Note 7) ● ● 1 0.5 IIN Analog Input Leakage Current 0V < AIN+, AIN– < VDD ● ISENSE SENSE Input Leakage 0V < SENSE < 1V ● IMODE MODE Pin Leakage ● tAP Sample-and-Hold Acquisition Delay Time tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS CMRR Analog Input Common Mode Rejection Ratio 80 dB –AIN–) MIN TYP MAX UNITS ±0.5V to ±1V 1.5 1.5 V 1.9 2 V V –1 1 µA –3 3 µA –3 3 µA 0 ns W U DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP SNR Signal-to-Noise Ratio 5MHz Input 70MHz Input ● 69.8 71.3 70.7 dB dB SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic 5MHz Input 70MHz Input ● 76 90 85 dB dB SFDR Spurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input 70MHz Input ● 82 90 90 dB dB S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input 70MHz Input ● 69.5 71.3 70.4 dB dB IMD Intermodulation Distortion fIN1 = 4.3MHz, fIN2 = 4.6MHz 90 dB U U U I TER AL REFERE CE CHARACTERISTICS MAX UNITS (Note 4) PARAMETER CONDITIONS MIN TYP MAX VCM Output Voltage IOUT = 0 1.475 1.500 1.525 ±25 VCM Output Tempco UNITS V ppm/°C VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V VCM Output Resistance –1mA < IOUT < 1mA 4 Ω 2225fa 3 LTC2225 U U DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.8 V 10 µA LOGIC INPUTS (CLK, OE, SHDN) VIH High Level Input Voltage VDD = 3V ● VIL Low Level Input Voltage VDD = 3V ● IIN Input Current VIN = 0V to VDD ● CIN Input Capacitance (Note 7) 2 V –10 3 pF LOGIC OUTPUTS OVDD = 3V COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF ISOURCE Output Source Current VOUT = 0V 50 mA ISINK Output Sink Current VOUT = 3V 50 mA VOH High Level Output Voltage IO = –10µA IO = –200µA ● IO = 10µA IO = 1.6mA ● VOL Low Level Output Voltage 2.7 2.995 2.99 0.005 0.09 V V V V 0.4 OVDD = 2.5V VOH High Level Output Voltage IO = –200µA 2.49 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V VOH High Level Output Voltage IO = –200µA 1.79 V VOL Low Level Output Voltage IO = 1.6mA 0.09 V OVDD = 1.8V U W POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 8) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Analog Supply Voltage (Note 9) ● 2.7 3 3.4 V OVDD Output Supply Voltage (Note 9) IVDD Supply Current ● ● 0.5 3 3.6 V 20 23 mA PDISS Power Dissipation ● 60 69 mW PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 mW PNAP Nap Mode Power SHDN = H, OE = L, No CLK 15 mW 2225fa 4 LTC2225 WU TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fs Sampling Frequency (Note 9) ● 1 tL CLK Low Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 40 5 tH CLK High Time Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) ● ● 40 5 tAP Sample-and-Hold Aperture Delay tD CLK to DATA delay CL = 5pF (Note 7) ● 2.7 5.4 ns Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns BUS Relinquish Time (Note 7) ● 3.3 8.5 ns 10 MHz 50 50 500 500 ns ns 50 50 500 500 ns ns 0 1.4 Pipeline Latency ns 5 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3V, fSAMPLE = 10MHz, input range = 2VP-P with differential drive, unless otherwise noted. Cycles Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 7: Guaranteed by design, not subject to test. Note 8: VDD = 3V, fSAMPLE = 10MHz, input range = 1VP-P with differential drive. Note 9: Recommended operating conditions. U W TYPICAL PERFOR A CE CHARACTERISTICS Typical INL, 2V Range 8192 Point FFT, fIN = 5.1MHz, –1dB, 2V Range Typical DNL, 2V Range 1.0 1.0 0 0.8 0.8 –10 0.6 0.6 –20 0.2 0 –0.2 –0.4 0.4 0.2 0 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 AMPLITUDE (dB) 0.4 DNL ERROR (LSB) INL ERROR (LSB) –30 1024 2048 CODE 3072 4096 2225 G01 –60 –70 –80 –90 –100 –110 –1.0 0 –40 –50 0 1024 2048 CODE 3072 4096 2225 G02 –120 0 1 3 2 FREQUENCY (MHz) 4 5 2225 G03 2225fa 5 LTC2225 U W TYPICAL PERFOR A CE CHARACTERISTICS 8192 Point 2-Tone FFT, fIN = 4.3MHz and 4.6MHz, –1dB, 2V Range 0 0 –10 –10 –20 –20 –30 –30 –40 –40 AMPLITUDE (dB) –50 –60 –70 –80 Grounded Input Histogram 70000 61758 60000 50000 –50 COUNT AMPLITUDE (dB) 8192 Point FFT, fIN = 70.1MHz, –1dB, 2V Range –60 –70 –80 –100 –100 –110 –110 –120 –120 1 0 3 2 FREQUENCY (MHz) 4 5 30000 20000 –90 –90 40000 10000 2155 1607 0 1 0 3 2 FREQUENCY (MHz) 4 2049 CODE 2048 5 2050 2225 G06 2225 G05 2225 G04 SNR vs Input Frequency, –1dB, 2V Range SFDR vs Input Frequency, –1dB, 2V Range 75 SNR and SFDR vs Sample Rate, 2V Range, fIN = 5MHz, –1dB 100 100 74 90 SFDR (dBFS) 72 SNR (dBFS) SNR AND SFDR (dBFS) 95 73 71 70 69 68 85 80 75 90 80 70 67 70 66 65 0 10 40 30 20 50 60 INPUT FREQUENCY (MHz) 70 60 65 0 10 40 60 30 50 20 INPUT FREQUENCY (MHz) 2225 G07 10 12 4 6 8 SAMPLE RATE (Msps) 14 2225 G09 SFDR vs Input Level, fIN = 5MHz, 2V Range 120 80 dBFS dBFS 110 70 100 60 SFDR (dBc AND dBFS) SNR (dBc AND dBFS) 2 2225 G08 SNR vs Input Level, fIN = 5MHz, 2V Range 50 40 dBc 30 20 90 80 dBc 70 60 50 90dBc SFDR REFERENCE LINE 40 30 20 10 –0 –70 –60 0 70 10 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 2225 G10 0 –70 –60 –50 –40 –30 –20 INPUT LEVEL (dBFS) –10 0 2225 G11 2225fa 6 LTC2225 U W TYPICAL PERFOR A CE CHARACTERISTICS IOVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB, OVDD = 1.8V IVDD vs Sample Rate, 5MHz Sine Wave Input, –1dB 25 1.0 0.9 0.8 2V RANGE 0.7 IOVDD (mA) IVDD (mA) 20 1V RANGE 15 0.6 0.5 0.4 0.3 0.2 0.1 0 10 0 2 10 4 6 8 SAMPLE RATE (Msps) 12 14 2225 G12 0 2 8 6 4 10 SAMPLE RATE (Msps) 12 14 2225 G13 U U U PI FU CTIO S AIN+ (Pin 1): Positive Differential Analog Input. AIN- (Pin 2): Negative Differential Analog Input. REFH (Pins 3, 4): ADC High Reference. Short together and bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 5, 6 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. OE to GND results in nap mode with the outputs at high impedance. Connecting SHDN to VDD and OE to VDD results in sleep mode with the outputs at high impedance. OE (Pin 11): Output Enable Pin. Refer to SHDN pin function. NC (Pins 12, 13): Do Not Connect These Pins. D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26, 27): Digital Outputs. D11 is the MSB. REFL (Pins 5, 6): ADC Low Reference. Short together and bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as close to the pin as possible. Also bypass to pins 3, 4 with an additional 2.2µF ceramic chip capacitor and to ground with a 1µF ceramic chip capacitor. OVDD (Pin 21): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor. VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF ceramic chip capacitors. OF (Pin 28): Over/Under Flow Output. High when an over or under flow has occurred. GND (Pin 8): ADC Power Ground. MODE (Pin 29): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to GND selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 VDD selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 VDD selects 2’s complement output format and turns the clock duty cycle stabilizer on. VDD selects 2’s complement output format and turns the clock duty cycle stabilizer off. CLK (Pin 9): Clock Input. The input sample starts on the positive edge. SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal operation with the outputs enabled. Connecting SHDN to GND and OE to VDD results in normal operation with the outputs at high impedance. Connecting SHDN to VDD and OGND (Pin 20): Output Driver Ground. 2225fa 7 LTC2225 U U U PI FU CTIO S SENSE (Pin 30): Reference Programming Pin. Connecting SENSE to VCM selects the internal reference and a ±0.5V input range. VDD selects the internal reference and a ±1V input range. An external reference greater than 0.5V and less than 1V applied to SENSE selects an input range of ±VSENSE. ±1V is the largest valid input range. VCM (Pin 31): 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2µF ceramic chip capacitor. GND (Exposed Pad) (Pin 33): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. W FUNCTIONAL BLOCK DIAGRA U U AIN+ AIN– VCM INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE 1.5V REFERENCE SIXTH PIPELINED ADC STAGE SHIFT REGISTER AND CORRECTION 2.2µF RANGE SELECT REFH SENSE REFL INTERNAL CLOCK SIGNALS OVDD REF BUF OF D11 DIFF REF AMP REFH 0.1µF CLOCK/DUTY CYCLE CONTROL CONTROL LOGIC CLK SHDN OUTPUT DRIVERS • • • D0 2225 F01 REFL OGND MODE OE 2.2µF 1µF 1µF Figure 1. Functional Block Diagram 2225fa 8 LTC2225 WU W TI I G DIAGRA tAP ANALOG INPUT N+4 N+2 N N+3 tH N+5 N+1 tL CLK tD D0-D11, OF N–4 N–5 N–3 N–2 N–1 N 2225 TD01 U W U U APPLICATIO S I FOR ATIO DYNAMIC PERFORMANCE Intermodulation Distortion Signal-to-Noise Plus Distortion Ratio If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The THD calculated in this data sheet uses all the harmonics up to the fifth. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. The 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation distortion is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order intermodulation product. Spurious Free Dynamic Range (SFDR) Spurious free dynamic range is the peak harmonic or spurious noise that is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full scale input signal. Input Bandwidth The input bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. 2225fa 9 LTC2225 U W U U APPLICATIO S I FOR ATIO Aperture Delay Time The time from when CLK reaches mid-supply to the instant that the input signal is held by the sample and hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) CONVERTER OPERATION As shown in Figure 1, the LTC2225 is a CMOS pipelined multistep converter. The converter has six pipelined ADC stages; a sampled analog input will result in a digitized value five cycles later (see the Timing Diagram section). For optimal AC performance the analog inputs should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with slightly worse harmonic distortion. The CLK input is single-ended. The LTC2225 has two phases of operation, determined by the state of the CLK input pin. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and an interstage residue amplifier. In operation, the ADC quantizes the input to the stage and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage ADC for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2225 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. LTC2225 VDD CSAMPLE 4pF 15Ω AIN+ CPARASITIC 1pF VDD AIN– CSAMPLE 4pF 15Ω CPARASITIC 1pF VDD CLK 2225 F02 When CLK is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “Input S/H” shown in the block diagram. At the instant that CLK transitions from low to high, the sampled input is held. While CLK is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H during this high phase of CLK. When CLK goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When CLK goes back high, Figure 2. Equivalent Input Circuit During the sample phase when CLK is low, the transistors connect the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When CLK transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when CLK is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As CLK transitions from high to low, the inputs are reconnected to the sampling 2225fa 10 LTC2225 U W U U APPLICATIO S I FOR ATIO capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Single-Ended Input For cost sensitive applications, the analog inputs can be driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and DNL will remain unchanged. For a single-ended input, AIN+ should be driven with the input signal and AIN– should be connected to VCM or a low noise reference voltage between 0.5V and 1.5V. Common Mode Bias For optimal performance the analog inputs should be driven differentially. Each input should swing ±0.5V for the 2V range or ±0.25V for the 1V range, around a common mode voltage of 1.5V. The VCM output pin (Pin 31) may be used to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with a 2.2µF or greater capacitor. Input Drive Impedance As with all high performance, high speed ADCs, the dynamic performance of the LTC2225 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and reactance can influence SFDR. At the falling edge of CLK, the sampleand-hold circuit will connect the 4pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when CLK rises, holding the sampled input on the sampling capacitor. Ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance, it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2225 being driven by an RF transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Terminating on the transformer secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source impedance seen by the ADC does not exceed 100Ω for each ADC input. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. VCM 2.2µF 0.1µF ANALOG INPUT T1 1:1 25Ω 25Ω AIN+ LTC2225 0.1µF 12pF 25Ω T1 = MA/COM ETC1-1T 25Ω RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE AIN– 2225 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer Figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input frequencies. Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This circuit is not recommended if low distortion is required. The 25Ω resistors and 12pF capacitor on the analog inputs serve two purposes: isolating the drive circuitry from the 2225fa 11 LTC2225 U W U U APPLICATIO S I FOR ATIO sample-and-hold charging glitches and limiting the wideband noise at the converter input. LTC2225 VCM 1.5V ANALOG INPUT + – AIN+ 25Ω RANGE DETECT AND CONTROL LTC2225 TIE TO VDD FOR 2V RANGE; TIE TO VCM FOR 1V RANGE; RANGE = 2 • VSENSE FOR 0.5V < VSENSE < 1V 12pF – 0.5V 1V 2.2µF + CM 1.5V BANDGAP REFERENCE 2.2µF VCM HIGH SPEED DIFFERENTIAL 25Ω AMPLIFIER 4Ω AIN– SENSE BUFFER INTERNAL ADC HIGH REFERENCE 1µF 2225 F04 REFH Figure 4. Differential Drive with an Amplifier 2.2µF 0.1µF DIFF AMP VCM 1k 0.1µF ANALOG INPUT 1k 1µF 2.2µF 25Ω AIN REFL + INTERNAL ADC LOW REFERENCE LTC2225 12pF 25Ω 2225 F06 Figure 6. Equivalent Reference Circuit AIN– 0.1µF 2225 F05 1.5V Figure 5. Single-Ended Drive VCM 2.2µF 12k Reference Operation Figure 6 shows the LTC2225 reference circuitry consisting of a 1.5V bandgap reference, a difference amplifier and switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range; tying the SENSE pin to VCM selects the 1V range. The 1.5V bandgap reference serves two functions: its output provides a DC bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to generate the differential reference levels needed by the internal ADC circuitry. An external bypass capacitor is required for the 1.5V reference output, VCM. This provides a high frequency low impedance path to ground for internal and external circuitry. 0.75V 12k SENSE LTC2225 1µF 2225 F07 Figure 7. 1.5V Range ADC The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are connected to these outputs and they must be externally bypassed. Each output has two pins. The multiple output pins are needed to reduce package inductance. Bypass capacitors must be connected as shown in Figure 6. Other voltage ranges in-between the pin selectable ranges can be programmed with two external resistors as shown in Figure 7. An external reference can be used by applying its output directly or through a resistor divider to SENSE. 2225fa 12 LTC2225 U W U U APPLICATIO S I FOR ATIO It is not recommended to drive the SENSE pin with a logic device. The SENSE pin should be tied to the appropriate level as close to the converter as possible. If the SENSE pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1µF ceramic capacitor. Input Range The input range can be set based on the application. The 2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input range will have better SFDR performance, but the SNR will degrade by 3.8dB. Driving the Clock Input The CLK input can be driven directly with a CMOS or TTL level signal. A differential clock can also be used along with a low-jitter CMOS converter before the CLK pin (see Figure 8). The noise performance of the LTC2225 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2225 is 10Msps. For the ADC to operate properly, the CLK signal should have a 50% (±10%) duty cycle. Each half cycle must have at least 40ns for the ADC internal circuitry to have enough settling time for proper operation. CLEAN SUPPLY 4.7µF FERRITE BEAD An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2225 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2225 is 1Msps. DIGITAL OUTPUTS Table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. Table 1. Output Codes vs Input Voltage AIN+ – AIN– (2V Range) OF D11 – D0 (Offset Binary) D11 – D0 (2’s Complement) >+1.000000V +0.999512V +0.999024V 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.000488V 0.000000V –0.000488V –0.000976V 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 –0.999512V –1.000000V <–1.000000V 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 1000 0000 0001 1000 0000 0000 1000 0000 0000 0.1µF CLK 100Ω LTC2225 2225 F08 IF LVDS USE FIN1002 OR FIN1018. FOR PECL, USE AZ1000ELT21 OR SIMILAR Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter 2225fa 13 LTC2225 U W U U APPLICATIO S I FOR ATIO Table 2. MODE Pin Function Digital Output Buffers Figure 9 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2225 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. Lower OVDD voltages will also help reduce interference from the digital outputs. Data Format Using the MODE pin, the LTC2225 parallel digital output can be selected for offset binary or 2’s complement format. Connecting MODE to GND or 1/3VDD selects offset binary output format. Connecting MODE to 2/3VDD or VDD selects 2’s complement output format. An external resistor divider can be used to set the 1/3VDD or 2/3VDD logic values. Table 2 shows the logic states for the MODE pin. Output Format Clock Duty Cycle Stablizer Offset Binary Off 1/3VDD Offset Binary On 2/3VDD 2’s Complement On VDD 2’s Complement Off MODE Pin 0 Overflow Bit When OF outputs a logic high the converter is either overranged or underranged. Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. For example if the converter is driving a DSP powered by a 1.8V supply, then OVDD should be tied to that same 1.8V supply. OVDD can be powered with any voltage from 500mV up to 3.6V. OGND can be powered with any voltage from GND up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Output Enable The outputs may be disabled with the output enable pin, OE. OE high disables all data outputs including OF. The output Hi-Z state can be used to multiplex the data bus of several LTC2225s. Sleep and Nap Modes LTC2225 OVDD VDD 0.5V TO 3.6V VDD 0.1µF OVDD DATA FROM LATCH PREDRIVER LOGIC 43Ω TYPICAL DATA OUTPUT OE OGND 2225 F09 Figure 9. Digital Output Buffer The converter may be placed in shutdown or nap modes to conserve power. Connecting SHDN to GND results in normal operation. Connecting SHDN to VDD and OE to VDD results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mW. When exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. Connecting SHDN to VDD and OE to GND results in nap mode, which typically dissipates 15mW. In nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. In both sleep 2225fa 14 LTC2225 U W U U APPLICATIO S I FOR ATIO and nap modes, all digital outputs are disabled and enter the Hi-Z state. Grounding and Bypassing The LTC2225 requires a printed circuit board with a clean, unbroken ground plane. A multilayer board with an internal ground plane is recommended. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of particular importance is the 0.1µF capacitor between REFH and REFL. This capacitor should be placed as close to the device as possible (1.5mm or less). A size 0402 ceramic capacitor is recommended. The large 2.2µF capacitor between REFH and REFL can be somewhat further away. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2225 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2225 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the PC board. It is critical that all ground pins are connected to a ground plane of sufficient area. 2225fa 15 J3 CLOCK INPUT R8 49.9Ω E1 EXT REF VCM VDD R9 1k R7 1k L1 BEAD VCM VDD 4 2 EXT REF 5 6 3 1 JP3 SENSE NC7SVU04 NC7SVU04 C10 0.1µF C5 4.7µF 6.3V 4 • C19 0.1µF R10 33Ω VDD GND VDD R16 1k R15 1k 7 5 3 1 GND 1/3VDD 2/3VDD VDD 8 6 4 GND C15 2.2µF VDD 2 C8 0.1µF 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 C20 0.1µF C2 12pF C11 0.1µF VDD JP4 MODE JP2 OE C7 2.2µF R6 24.9Ω R4 24.9Ω C4 0.1µF R14 1k VDD R2 24.9Ω R3 24.9Ω C14 0.1µF VCM VDD VDD C9 1µF C6 1µF JP1 SHDN R5 50Ω •3 2 T1 ETC1-1T 5 1 C13 0.1µF C3 0.1µF VCM C1 0.1µF D6 C26 10µF 6.3V MODE D8 OVDD OF D11 D10 D9 R18 100k R17 105k OGND 33 GND SENSE VCM VDD OE D7 CLK SHDN D4 D5 GND D3 D2 D1 VDD REFL REFL REFH D0 NC AIN– REFH NC LTC2225 AIN+ LT1763 C16 0.1µF VCC 39 VCC OE1 VDD C28 1µF VCC 28 7 4 10 18 15 21 31 E3 GND C18 0.1µF C25 4.7µF E4 PWR GND E2 VDD 3V 5 6 8 7 C17 0.1µF 24LC025 1 VCC A0 2 WP A1 3 A2 SCL 4 A3 SDA RN4A 33Ω RN4B 33Ω RN4C 33Ω RN4D 33Ω RN3A 33Ω RN3B 33Ω RN3C 33Ω RN3D 33Ω RN2A 33Ω RN2B 33Ω RN2C 33Ω RN2D 33Ω RN1A 33Ω RN1B 33Ω RN1C 33Ω RN1D 33Ω VDD 2 O0 3 O1 5 O2 6 O3 8 O4 9 O5 11 O6 12 O7 13 O8 14 O9 16 O10 17 O11 19 O12 20 O13 22 O14 23 O15 GND GND LE1 VCC LE2 OE2 GND GND VCC GND VCC GND GND GND 74VCX16373MTD 47 I0 46 I1 44 I2 43 I3 41 I4 40 I5 38 I6 37 I7 36 I8 35 I9 33 I10 32 I11 30 I12 29 I13 27 I14 26 I15 1 24 48 25 42 NC7SV86P5X 1 8 IN OUT 2 7 ADJ GND 3 6 GND GND 4 5 BYP SHDN VCC C27 0.01µF 20 21 28 27 26 25 24 23 22 19 18 17 16 15 14 13 12 34 45 C21 0.1µF R11 10k R12 10k C22 0.1µF VCC R13 10k C23 0.1µF 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 40 38 2225 TA02 C24 0.1µF 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 3201S-40G1 39 39 37 37 35 35 33 33 31 31 29 29 27 27 25 25 23 23 21 21 19 19 17 17 15 15 13 13 11 11 9 9 7 7 5 5 3 3 1 1 U U W 16 C12 0.1µF VDD R1 OPT VCC APPLICATIO S I FOR ATIO U J1 ANALOG INPUT VCC LTC2225 2225fa LTC2225 U W U U APPLICATIO S I FOR ATIO Topside Silkscreen Top Inner Layer 2 GND 2225fa 17 LTC2225 U W U U APPLICATIO S I FOR ATIO Bottomside Inner Layer 3 Power Silkscreen Bottom 2225fa 18 LTC2225 U PACKAGE DESCRIPTIO UH Package 32-Lead Plastic QFN (5mm × 5mm) (Reference LTC DWG # 05-08-1693) 0.70 ±0.05 5.50 ±0.05 4.10 ±0.05 3.45 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC RECOMMENDED SOLDER PAD LAYOUT 5.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.115 TYP 0.75 ± 0.05 0.00 – 0.05 31 32 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 3.45 ± 0.10 (4-SIDES) (UH32) QFN 1004 0.200 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC 2225fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2225 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 14-Bit, 80Msps, 5V ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 150mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 78dB SNR, 100dB SFDR, 64-Pin QFN LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN LTC2225 12-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN LTC2226 12-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN LTC2227 12-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN LTC2228 12-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 71.3dB SNR, 90dB SFDR, 32-Pin QFN LTC2229 12-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 70.6dB SNR, 90dB SFDR, 32-Pin QFN LTC2236 10-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN LTC2237 10-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN LTC2238 10-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN LTC2239 10-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN LTC2245 14-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN LTC2246 14-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN LTC2247 14-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN LTC2248 14-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN LTC2249 14-Bit, 80Msps, 3V ADC, Lowest Power 222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN LTC2250 10-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN LTC2251 10-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN LTC2252 12-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN LTC2253 12-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN LTC2254 14-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF and LO Ports 2225fa 20 Linear Technology Corporation LT 0106 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2004