LINER LTC2498CUHF-PBF

LTC2498
24-Bit 8-/16-Channel ΔΣ
ADC with Easy Drive Input
Current Cancellation
DESCRIPTION
FEATURES
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Up to 8 Differential or 16 Single-Ended Inputs
Easy Drive™ Technology Enables Rail-to-Rail
Inputs with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
600nV RMS Noise
Integrated High Accuracy Temperature Sensor
GND to VCC Input/Reference Common Mode Range
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
2ppm INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
2x Speed Mode (15Hz Using Internal Oscillator)
No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel is Selected
Single Supply 2.7V to 5.5V Operation (0.8mW)
Internal Oscillator
Tiny QFN 5mm × 7mm Package
APPLICATIONS
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Direct Sensor Digitizer
Direct Temperature Measurement
Instrumentation
Industrial Process Control
The LTC®2498 is a 16-channel (8-differential) 24-bit No
Latency ΔΣ™ ADC with Easy Drive technology. The patented sampling scheme eliminates dynamic input current
errors and the shortcomings of on-chip buffering through
automatic cancellation of differential input current. This
allows large external source impedances, and rail-to-rail
input signals to be directly digitized while maintaining
exceptional DC accuracy.
The LTC2498 includes a high accuracy temperature sensor
and an integrated oscillator. This device can be conﬁgured
to measure an external signal (from combinations of 16
analog input channels operating in single ended or differential modes) or its internal temperature sensor. The
integrated temperature sensor offers 1/30th °C resolution
and 2°C absolute accuracy.
The LTC2498 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can be
selected and the ﬁrst conversion after a new channel is
selected is valid. Access to the multiplexer output enables
optional external ampliﬁers to be shared between all analog
inputs and auto calibration continuously removes their
associated offset and drift.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Δ∑ is a
trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
TYPICAL APPLICATION
Data Acquisition System with Temperature Compensation
Absolute Temperature Error
5
2.7V TO 5.5V
4
MUXOUT/
ADCIN
0.1μF
VCC
10μF
REF+
IN+
24-BIT ΔΣ ADC
WITH EASY-DRIVE
IN–
REF–
SDI
SCK
SDO
CS
4-WIRE
SPI INTERFACE
3
ABSOLUTE ERROR (°C)
CH0
CH1
•
•
•
CH7
CH8 16-CHANNEL
MUX
•
•
•
CH15
2
1
0
–1
–2
–3
COM
–4
TEMPERATURE
SENSOR
FO
MUXOUT/
ADCIN
OSC
2498 TA01a
–5
–55
–30
–5
20
45
70
TEMPERATURE (°C)
95
120
2498 TA01b
2498fc
1
LTC2498
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage
(CH0 to CH15, COM) ................–0.3V to (VCC + 0.3V)
Reference Input Voltage
ADCINN, ADCINP, MUXOUTP,
MUXOUTN ................................–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage ...................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2498C ................................................ 0°C to 70°C
LTC2498I.............................................. –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
GND
GND
SDI
FO
CS
SCK
SDO
TOP VIEW
38 37 36 35 34 33 32
GND 1
31 GND
NC 2
30 REF–
GND 3
29 REF+
GND 4
28 VCC
GND 5
27 MUXOUTN
GND 6
26 ADCINN
39
COM 7
25 ADCINP
CH0 8
24 MUXOUTP
CH1 9
23 CH15
CH2 10
22 CH14
CH3 11
21 CH13
20 CH12
CH4 12
CH11
CH10
CH9
CH8
CH7
CH6
CH5
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2498CUHF#PBF
LTC2498CUHF#TRPBF
2498
38-Lead (5mm × 7mm) Plastic QFN
0°C to 70°C
LTC2498IUHF#PBF
LTC2498IUHF#TRPBF
2498
38-Lead (5mm × 7mm) Plastic QFN
–40°C to 85°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based ﬁnish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The l denotes the speciﬁcations which
apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l
2
1
10
ppm of VREF
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
l
0.5
2.5
μV
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
25
ppm of VREF
Positive Full-Scale Error
Positive Full-Scale Error Drift
Negative Full-Scale Error
24
Bits
10
l
nV/°C
0.1
l
ppm of VREF/°C
25
ppm of VREF
2498fc
2
LTC2498
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The l denotes the speciﬁcations which
apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
MIN
TYP
0.1
ppm of VREF/°C
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
5.5V < VCC < 2.7V, 2.5V ≤ VREF ≤ VCC,
GND ≤ IN+ = IN– ≤ VCC (Note 13)
0.6
μVRMS
Internal PTAT Signal
TA = 27°C (Note 5)
27.8
MAX
28.0
Internal PTAT Temperature Coefﬁcient
UNITS
28.2
mV
93.5
μV/°C
ELECTRICAL CHARACTERISTICS (2X SPEED)
The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤5.5V, VREF = 2.5V, VIN(CM) = 1.2V (Note 6)
l
2
1
10
ppm of VREF
ppm of VREF
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
l
0.5
2
mV
25
ppm of VREF
, GND ≤ IN+ = IN– ≤ V
Offset Error Drift
2.5V ≤ VREF ≤ VCC
Positive Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
Positive Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF
Negative Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF
5V ≤ VCC ≤ 2.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC
Output Noise
24
Bits
100
CC
nV/°C
l
0.1
ppm of VREF/°C
l
25
ppm of VREF
0.1
ppm of VREF/°C
0.85
μVRMS
CONVERTER CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9)
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5)
VREF = 2.5V, IN+ = IN– = GND
VREF = 2.5V, IN+ = IN– = GND (Notes 7, 9)
VREF = 2.5V, IN+ = IN– = GND (Notes 8, 9)
Input Common Mode Rejection 60Hz ±2%
Input Common Mode Rejection 50Hz ±2%
Input Normal Mode Rejection 50Hz ±2%
Input Normal Mode Rejection 60Hz ±2%
Input Normal Mode Rejection 50Hz/60Hz ±2%
Reference Common Mode Rejection DC
Power Supply Rejection DC
Power Supply Rejection, 50Hz ±2%
Power Supply Rejection, 60Hz ±2%
MIN
TYP
MAX
UNITS
l
140
dB
l
140
dB
l
140
l
110
120
l
110
120
l
87
l
120
dB
dB
dB
dB
140
dB
120
dB
120
dB
120
dB
ANALOG INPUT AND REFERENCE
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
(IN+ Corresponds to the Selected Positive Input Channel)
CONDITIONS
MIN
GND – 0.3V
TYP
MAX
VCC + 0.3V
UNITS
V
2498fc
3
LTC2498
ANALOG INPUT AND REFERENCE
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN–
Absolute/Common Mode IN– Voltage
(IN– Corresponds to the Selected Negative Input Channel)
CONDITIONS
VIN
Input Differential Voltage Range (IN+ – IN–)
FS
Full Scale of the Differential Input (IN+ – IN–)
LSB
REF+
MIN
TYP
MAX
UNITS
GND – 0.3V
VCC + 0.3V
l
–FS
+FS
l
0.5VREF
Least Signiﬁcant Bit of the Output Code
l
FS/224
Absolute/Common Mode REF+ Voltage
l
0.1
REF–
Absolute/Common Mode REF– Voltage
l
VREF
Reference Voltage Range (REF+ – REF–)
l
CS(IN+)
IN+ Sampling Capacitance
11
pF
CS(IN–)
IN– Sampling Capacitance
11
pF
CS(VREF)
VREF Sampling Capacitance
IDC_LEAK(IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
l
IDC_LEAK(IN–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
IDC_LEAK(REF+)
IDC_LEAK(REF–)
REF+ DC Leakage Current
Sleep Mode, REF+ = VCC
REF– DC Leakage Current
Sleep Mode, REF– = GND
tOPEN
MUX Break-Before-Make
QIRR
MUX Off Isolation
V
V
V
V
GND
VCC
+
REF – 0.1V
0.1
VCC
V
V
11
–10
1
l
–10
l
–100
l
–100
VIN = 2VP-P DC to 1.8MHz
pF
10
nA
1
10
nA
1
100
nA
1
100
nA
50
ns
120
dB
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage (CS, FO, SDI)
2.7V ≤ VCC ≤ 5.5V
l
VIL
Low Level Input Voltage (CS, FO, SDI)
2.7V ≤ VCC ≤ 5.5V
l
TYP
MAX
UNITS
VCC – 0.5
V
0.5
V
0.5
V
VIH
High Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
l
VIL
Low Level Input Voltage (SCK)
2.7V ≤ VCC ≤ 5.5V (Notes 10, 15)
l
IIN
Digital Input Current (CS, FO, SDI)
0V ≤ VIN ≤ VCC
l
–10
10
μA
IIN
Digital Input Current (SCK)
0V ≤ VIN ≤ VCC (Notes 10, 15)
l
–10
10
μA
CIN
Digital Input Capacitance (CS, FO, SDI)
CIN
Digital Input Capacitance (SCK)
(Notes 10, 17)
VOH
High Level Output Voltage (SDO)
IO = –800μA (Notes 10, 17)
l
VOL
Low Level Output Voltage (SDO)
IO = 1.6mA (Notes 10, 17)
l
VOH
High Level Output Voltage (SCK)
IO = –800μA
l
VOL
Low Level Output Voltage (SCK)
IO = 1.6mA
l
IOZ
Hi-Z Output Leakage (SDO)
l
VCC – 0.5
V
10
pF
10
pF
VCC – 0.5
V
0.4
V
0.4
V
10
μA
VCC – 0.5
V
–10
POWER REQUIREMENTS
The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
CONDITIONS
MIN
l
Conversion Current (Note 12)
Temperature Measurement (Note 12)
Sleep Mode (Note 12)
l
l
l
TYP
2.7
160
200
1
MAX
UNITS
5.5
V
275
300
2
μA
μA
μA
2498fc
4
LTC2498
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
(Note 16)
MIN
TYP
MAX
UNITS
l
10
4000
kHz
l
0.125
50
μs
l
0.125
50
μs
l
l
l
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
ms
ms
ms
l
l
l
78.7
65.6
72.2
80.3
66.9
73.6
81.9
68.2
75.1
20556/fEOSC (in kHz)
ms
ms
ms
ms
38.4
fEOSC/8
kHz
kHz
fEOSC
External Oscillator Frequency Range
tHEO
External Oscillator High Period
tLEO
External Oscillator Low Period
tCONV_1
Conversion Time for 1x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
tCONV_2
Conversion Time for 2x Speed Mode
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
l
fESCK
External SCK Frequency Range
(Note 10)
l
tLESCK
External SCK Low Period
(Note 10)
l
tHESCK
External SCK High Period
(Note 10)
l
125
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator
External Oscillator
l
0.81
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 10)
t1
45
55
%
4000
kHz
125
ns
ns
0.83
256/fEOSC (in kHz)
0.85
32/fESCK (in kHz)
ms
ms
ms
CS↓ to SDO Low
l
0
200
ns
t2
CS↑ to SDO High Z
l
0
200
ns
t3
CS↓ to SCK↑
Internal SCK Mode
l
0
200
ns
External SCK Mode
l
50
t4
CS↓ to SCK↑
tKQMAX
SCK↓ to SDO Valid
tKQMIN
SDO Hold After SCK↓
l
ns
200
ns
l
15
ns
SCK Set-Up Before CS↓
l
50
ns
t6
SCK Hold After CS↓
l
t7
SDI Setup Before SCK↑
(Note 5)
l
100
ns
t8
SDI Hold After SCK↑
(Note 5)
l
100
ns
t5
(Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise speciﬁed.
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise speciﬁed.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
50
ns
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The SCK can be conﬁgured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output.
2498fc
5
LTC2498
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
–45°C
1
25°C
0
85°C
–1
–2
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
INL (ppm OF VREF)
2
1
–45°C, 25°C, 90°C
0
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN(CM) = 1.25V
FO = GND
8
85°C
25°C
–45°C
–4
2
12
85°C
–4
Noise Histogram (6.8sps)
12
12
NUMBER OF READINGS (%)
8
6
4
2
–0.75
–4
1.8
2498 G07
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
1.25
2498 G06
Long-Term ADC Readings
5
VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V
4 TA = 25°C, RMS NOISE = 0.60μV
10,000 CONSECUTIVE
READINGS
RMS = 0.59μV
VCC = 2.7V
AVERAGE = –0.19μV
VREF = 2.5V
10 VIN = 0V
TA = 25°C
3
8
6
4
2
1
0
–1
–2
–3
–4
–5
0
1.2
85°C
–45°C
–12
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2
0
25°C
0
Noise Histogram (7.5sps)
14
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
4
2498 G05
14
1.25
–8
2498 G04
NUMBER OF READINGS (%)
8
–45°C
0
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
25°C
4
–12
–1.25
2.5
10,000 CONSECUTIVE
READINGS
RMS = 0.60μV
VCC = 5V
AVERAGE = –0.69μV
VREF = 5V
10 VIN = 0V
TA = 25°C
–0.25
0.25
0.75
INPUT VOLTAGE (V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
–8
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
–0.75
2498 G03
TUE (ppm OF VREF)
12
4
0
–1
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
TUE (ppm OF VREF)
TUE (ppm OF VREF)
8
0
2498 G02
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
–45°C, 25°C, 90°C
–3
–1.25
1.25
2498 G01
12
1
–2
–3
–1.25
2.5
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
ADC READING (μV)
INL (ppm OF VREF)
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
1.2
1.8
2498 G08
0
10
30
40
20
TIME (HOURS)
50
60
2498 G09
2498fc
6
LTC2498
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
0.8
0.7
0.6
0.5
RMS Noise vs Temperature (TA)
1.0
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.9
RMS NOISE (μV)
RMS NOISE (ppm OF VREF)
0.9
RMS Noise vs VIN(CM)
1.0
0.8
0.7
0.6
–1
0
2
1
3
5
4
OFFSET ERROR (ppm OF VREF)
RMS NOISE (μV)
RMS NOISE (μV)
0.8
0.7
0.6
0.5
0.5
3.5
3.9 4.3
VCC (V)
4.7
5.1
0
5.5
1
2
3
VREF (V)
–0.1
–0.2
0 15 30 45 60
TEMPERATURE (°C)
–0.1
–0.2
–1
75
90
2498 G16
0
1
3
2
VIN(CM) (V)
5
4
0.2
0.1
Offset Error vs VREF
0.3
REF+ = 2.5V
– = GND
REF
VIN = 0V
VIN(CM) = GND
TA = 25°C
0
–0.1
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.2
0.1
0
–0.1
–0.2
–0.3
2.7
6
2498 G15
OFFSET ERROR (ppm OF VREF)
0
–0.3
–45 –30 –15
0
Offset Error vs VCC
0.3
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.1
0.1
2498 G14
Offset Error vs Temperature
0.2
0.2
5
4
2498 G13
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
–0.3
0.4
3.1
90
Offset Error vs VIN(CM)
0.3
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.9
0.6
75
2498 G12
RMS Noise vs VREF
1.0
0.7
0 15 30 45 60
TEMPERATURE (°C)
2498 G11
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
0.4
2.7
0.4
–45 –30 –15
6
VIN(CM) (V)
0.8
0.3
0.6
0.4
2.5
RMS Noise vs VCC
0.9
0.7
0.5
2498 G10
1.0
0.8
0.5
0.4
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
0.9
RMS NOISE (μV)
1.0
–0.2
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2498 G17
–0.3
0
1
2
3
VREF (V)
4
5
2498 G18
2498fc
7
LTC2498
TYPICAL PERFORMANCE CHARACTERISTICS
On-Chip Oscillator Frequency
vs VCC
310
310
306
304
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
300
–45 –30 –15
306
304
0 15 30 45 60
TEMPERATURE (°C)
75
300
90
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
–80
–120
–120
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
2498 G22
SUPPLY CURRENT (μA)
SLEEP MODE CURRENT (μA)
120
1.0
0.8
VCC = 2.7V
250
3
2
VCC = 5V
VCC = 3V
2498 G25
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
0
25°C, 90°C
–1
–45°C
–2
100
90
90
1
200
150
75
75
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
0.4
0.2
0 15 30 45 60
TEMPERATURE (°C)
2498 G24
450
VCC = 5V
VCC = 5V
VCC = 2.7V
140
100
–45 –30 –15
30800
500
VREF = VCC
IN+ = GND
IN– = GND
400 SCK = NC
SDO = NC
350 SDI = GND
CS GND
F = EXT OSC
300 O
TA = 25°C
1M
160
Conversion Current
vs Output Data Rate
2.0
0 15 30 45 60
TEMPERATURE (°C)
180
FO = GND
CS = GND
SCK = NC
SDO = NC
SDI = GND
2498 G23
Sleep Mode Current
vs Temperature
FO = GND
1.8 CS = VCC
SCK = NC
1.6
SDO = NC
1.4 SDI = GND
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
2498 G21
200
–60
–100
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
10
Conversion Current
vs Temperature
VCC = 4.1V DC ±0.7V
= 2.5V
V
–20 INREF
+ = GND
– = GND
IN
–40 FO = GND
TA = 25°C
–100
0
–45 –30 –15
1
CONVERSION CURRENT (μA)
–80
0.6
–140
0
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
1.2
5.5
PSRR vs Frequency at VCC
–60
–140
–80
2498 G20
REJECTION (dB)
REJECTION (dB)
–40
–60
–120
PSRR vs Frequency at VCC
–20
–40
–100
302
2498 G19
0
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–20
INL (ppm OF VREF)
302
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
308
FREQUENCY (kHz)
FREQUENCY (kHz)
308
PSRR vs Frequency at VCC
0
REJECTION (dB)
On-Chip Oscillator Frequency
vs Temperature
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2498 G26
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
2.5
2498 G27
2498fc
8
LTC2498
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
1
90°C
0
–45°C, 25°C
–1
–2
16
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
INL (ppm OF VREF)
2
INL (ppm OF VREF)
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
1
90°C
0
–45°C, 25°C
–1
–2
–3
–1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–3
–1.25
1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
OFFSET ERROR (μV)
RMS NOISE (μV)
0.4
VCC = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
240
194
192
190
188
186
–1
1
0
3
VIN(CM) (V)
2
4
5
OFFSET ERROR (μV)
OFFSET ERROR (μV)
VCC = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
230
150
100
220
–40
210
200
190
4
3.5
VCC (V)
4.5
5
5.5
2498 G34
160
–60
–80
–100
–120
170
3
90
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
–20
180
50
75
PSRR vs Frequency at VCC
(2x Speed Mode)
0
240
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
0 15 30 45 60
TEMPERATURE (°C)
2498 G33
Offset Error vs VREF
(2x Speed Mode)
250
2.5
190
160
–45 –30 –15
6
REJECTION (dB)
Offset Error vs VCC
(2x Speed Mode)
2
200
2498 G32
2498 G31
0
210
170
180
5
220
180
182
4
188.6
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
230
184
3
2
VREF (V)
183.8
186.2
OUTPUT READING (μV)
2498 G30
OFFSET ERROR (μV)
196
0.8
0.6
181.4
Offset Error vs Temperature
(2x Speed Mode)
VCC = 5V
VREF = 5V
VIN = 0V
FO = GND
TA = 25°C
198
200
4
0
179
1.25
200
1
6
Offset Error vs VIN(CM)
(2x Speed Mode)
1.0
0
8
2498 G29
RMS Noise vs VREF
(2x Speed Mode)
0.2
RMS = 0.85μV
10,000 CONSECUTIVE
AVERAGE = 0.184mV
14 READINGS
VCC = 5V
12 VREF = 5V
VIN = 0V
GAIN = 256
10
TA = 25°C
2
2498 G28
0
Noise Histogram
(2x Speed Mode)
NUMBER OF READINGS (%)
3
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
–140
0
1
2
3
VREF (V)
4
5
2498 G35
1
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
1M
2498 G36
2498fc
9
LTC2498
TYPICAL PERFORMANCE CHARACTERISTICS
PSRR vs Frequency at VCC
(2x Speed Mode)
RREJECTION (dB)
–20
–40
–60
0
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
FO = GND
TA = 25°C
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
–40 IN– = GND
FO = GND
–60 TA = 25°C
–20
REJECTION (dB)
0
PSRR vs Frequency at VCC
(2x Speed Mode)
–80
–80
–100
–100
–120
–120
–140
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2498 G37
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2498 G38
PIN FUNCTIONS
GND (Pins 1, 3, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground current ﬂow and VCC decoupling. Connect each one of these
pins to a common ground plane through a low impedance
connection. All eight pins must be connected to ground
for proper operation.
ADCINN (Pin 26): Negative ADC Input. Tie to the output
of a buffer/ampliﬁer driven by MUXOUTN or tie directly
to MUXOUTN.
NC (Pin 2): No Connection, this pin can be left ﬂoating
or tied to GND.
VCC (Pin 28): Positive Supply Voltage. Bypass to GND with
a 10μF tantalum capacitor in parallel with a 0.1μF ceramic
capacitor as close to the part as possible.
COM (Pin 7): The common negative input (IN–) for all
single-ended multiplexer conﬁgurations. The voltage on
CH0 to CH15 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN–) provide a bipolar input range
(VIN = IN+ – IN–) from –0.5 • VREF to 0.5 • VREF. Outside
this input range, the converter produces unique over-range
and under-range output codes.
CH0 to CH15 (Pins 8 to 23): Analog Inputs. May be programmed for single-ended or differential mode.
MUXOUTP (Pin 24): Positive Multiplexer Output. Used
to drive an external buffer/ampliﬁer or can be shorted
directly to ADCINP.
ADCINP (Pin 25): Positive ADC Input. Tie to the output
of a buffer/ampliﬁer driven by MUXOUTP or tie directly
to MUXOUTP.
MUXOUTN (Pin 27): Negative Multiplexer Output. Used
to drive an external buffer/ampliﬁer or can be shorted
directly to ADCINN.
REF+ (Pin 29), REF– (Pin 30): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (REF = REF+
– REF–) sets the full-scale range for all input channels.
When performing an on-chip temperature measurement,
the minimum value of REF = 2V.
SDI (Pin 34): Serial Data Input. This pin is used to select the
line frequency rejection mode, 1x or 2x mode, temperature
sensor, as well as the input channel. The serial data input
is applied under control of the serial clock (SCK) during
the data output/input operation. The ﬁrst conversion following a new input or mode change is valid.
2498fc
10
LTC2498
PIN FUNCTIONS
FO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When FO is
connected to VCC or GND, the converter uses its internal
oscillator running at 307.2kHz. The conversion clock may
also be overridden by driving the FO pin with an external
clock in order to change the output rate and the digital
ﬁlter rejection null.
CS (Pin 36): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output aborts the data transfer and starts
a new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedance state. During the conversion and sleep periods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes low. The conversion
status is monitored by pulling CS LOW.
SCK (Pin 38): Bidirectional, Digital I/O, Clock Pin. In Internal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin . In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power up and during the most recent falling edge of CS.
Exposed Pad (Pin 39): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain ﬂoating.
FUNCTIONAL BLOCK DIAGRAM
TEMP
SENSOR
VCC
INTERNAL
OSCILLATOR
MUXOUTP ADCINP
GND
–
CH0
CH1
CH15
COM
•
•
•
+
DIFFERENTIAL
3RD ORDER
ΔΣ MODULATOR
MUX
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
REF+
REF–
SERIAL
INTERFACE
SDI
SCK
SDO
CS
DECIMATING FIR
ADDRESS
2498 BD
MUXOUTN ADCINN
Figure 1. Functional Block Diagram
2498fc
11
LTC2498
TEST CIRCUITS
VCC
SDO
1.69k
1.69k
CLOAD = 20pF
SDO
CLOAD = 20pF
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
2498 TC01
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2498 TC02
TIMING DIAGRAMS
Timing Diagram Using Internal SCK (SCK HIGH with CS↓)
CS
t1
t2
SDO
tKQMIN
t3
tKQMAX
SCK
t7
t8
SDI
2498 TD01
SLEEP
DATA IN/OUT
CONVERSION
Timing Diagram Using External SCK (SCK LOW with CS↓)
CS
t1
t2
SDO
t5
tKQMIN
t6
t4
tKQMAX
SCK
t7
t8
SDI
2498 TD02
SLEEP
DATA IN/OUT
CONVERSION
2498fc
12
LTC2498
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2498 is a multi-channel, low power, delta-sigma
analog-to-digital converter with an easy to use 4-wire interface and automatic differential input current cancellation.
Its operation is made up of three states (See Figure 2).
The converter operating cycle begins with the conversion, followed by the sleep state and ends with the data
input/output cycle. The 4-wire interface consists of serial
data output (SDO), serial clock (SCK), chip select (CS)
and serial data input (SDI).The interface, timing, operation
cycle, and data output format is compatible with Linear’s
entire family of ΔΣ converters.
Initially, at power up, the LTC2498 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in this sleep state, if CS in HIGH, power
consumption is reduced by two orders of magnitude. The
part remains in the sleep state as long as CS is HIGH. The
conversion result is held indeﬁnitely in a static shift register
while the part is in the sleep state.
Once CS is pulled LOW, the device powers up, exits the
sleep mode, and enters the data input/output state. If CS
is brought HIGH before the ﬁrst rising edge of SCK, the
device returns to the sleep state and the power is reduced.
If CS is brought HIGH after the ﬁrst rising edge of SCK, the
POWER UP
IN+= CH0, IN–= CH1
50/60Hz,1X
CONVERT
SLEEP
CS = LOW
AND
SCK
data output cycle is aborted and a new conversion cycle
begins. The data output corresponds to the conversion
just completed. This result is shifted out on the serial data
output pin (SDO) under the control of the serial clock pin
(SCK). Data is updated on the falling edge of SCK allowing
the user to reliably latch data on the rising edge of SCK (See
Figure 3). The conﬁguration data for the next conversion
is also loaded into the device at this time. Data is loaded
from the serial data input pin (SDI) on each rising edge
of SCK. The data input/output cycle is concluded once 32
bits are read out of the ADC or when CS is brought HIGH.
The device automatically initiates a new conversion and
the cycle repeats.
Through timing control of the CS and SCK pins, the LTC2498
offers several ﬂexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming and do not
disturb the cyclic operation described above. These modes
of operation are described in detail in the Serial Interface
Timing Modes section.
Ease of Use
The LTC2498 data output has no latency, ﬁlter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion, immediately following a newly selected input or
mode, is valid and accurate to the full speciﬁcations of
the device.
The LTC2498 automatically performs offset and full scale
calibration every conversion cycle independent of the
input channel selected. This calibration is transparent to
the user and has no effect with the operation cycle described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage variation, input channel,
and temperature drift.
Easy Drive Input Current Cancellation
CHANNEL SELECT
CONFIGURATION SELECT
DATA OUTPUT
2498 F02
Figure 2. LTC2498 State Transition Diagram
The LTC2498 combines a high precision delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling network
2498fc
13
LTC2498
APPLICATIONS INFORMATION
transparently removes the differential input current. This
enables external RC networks and high impedance sensors to directly interface to the LTC2498 without external
ampliﬁers. The remaining common mode input current
is eliminated by either balancing the differential input
impedances or setting the common mode input equal to
the common mode reference (see Automatic Differential
Input Current Cancellation Section). This unique architecture does not require on-chip buffers thereby enabling
signals to swing beyond ground or up to VCC. Moreover, the
cancellation does not interfere with the transparent offset
and full-scale auto-calibration and the absolute accuracy
(full scale + offset + linearity + drift) is maintained even
with external RC networks.
Power-Up Sequence
The LTC2498 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of
the conversion result, input channel selection, and serial
clock mode.
When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channel IN+ = CH0, IN– =
CH1, simultaneous 50Hz/60Hz rejection and 1x output
rate. The ﬁrst conversion following a POR cycle is accurate
within the speciﬁcation of the device if the power supply
voltage is restored to (2.7V to 5.5V) before the end of the
POR interval. A new input channel, rejection mode, speed
mode, or temperature selection can be programmed into
the device during this ﬁrst data input/output cycle.
Reference Voltage Range
This converter accepts a truly differential external reference
voltage. The absolute/common mode voltage range for
REF+ and REF– pins covers the entire operating range of
the device (GND to VCC). For correct converter operation,
VREF must be positive (REF+ > REF–)
The LTC2498 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND. The converter output noise is determined by the thermal noise of the front
end circuits, and as such, its value in nano volts is nearly
constant with reference voltage. A decrease in reference
voltage will not signiﬁcantly improve the converter’s effective resolution. On the other hand, a decreased reference
will improve the converter’s overall INL performance.
Input Voltage Range
The analog input is truly differential with an absolute, common mode range for CH0 to CH15 and COM input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD projection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2498 converts the bipolar differential
input signal VIN = IN+ + IN– (where IN+ and IN– are the
selected input channels), from –FS = –0.5 • VREF to +FS =
0.5 • VREF where VREF = REF+ – REF–. Outside this range,
the converter indicates the overrange or the underrange
condition using distinct output codes.
Signals applied to the input (CH0 to CH15, COM) may
extend 300mV below ground and above VCC. In order to
limit any fault current, resistors of up to 5k may be added
in series with the input. The effect of series resistance on
the converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent error due to input leakage current. A 1nA
input leakage current will develop a 1ppm offset error
on a 5k resistor if VREF = 5V. This error has a very strong
temperature dependency.
MUXOUT/ADCIN
The output of the multiplexer (MUXOUT) and the input
to the ADC (ADCIN) can be used to perform input signal
conditioning on any of the selected input channels or simply shorted together for direct digitization. If an external
ampliﬁer is used, the LTC2498 automatically calibrates
both the offset and drift of this circuit and the Easy Drive
sampling scheme enables a wide variety of ampliﬁers to
be used.
2498fc
14
LTC2498
APPLICATIONS INFORMATION
In order to achieve optimum performance, if an external
ampliﬁer is not used, short these pins directly together
(ADCINP to MUXOUTP and ADCINN to MUXOUTN) and
minimize their capacitance to ground.
SERIAL INTERFACE PINS
The LTC2498 transmits the conversion result, reads the
input conﬁguration, and receives a start of conversion
command through a synchronous 3- or 4-wire interface.
During the conversion and sleep states, this interface
can be used to access the converter status. During the
data output state, it is used to read the conversion result,
program the input channel, rejection frequency, speed
multiplier, and select the temperature sensor.
Serial Clock Input/Output (SCK)
The serial clock pin (SCK) is used to synchronize the data
input/output transfer. Each bit is shifted out of the SDO
pin on the falling edge of SCK and data is shifted into the
SDI pin on the rising edge of SCK.
The serial clock pin (SCK) can be conﬁgured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply ﬂoating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of CS. Speciﬁc
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB ﬁrst) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When CS is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If CS is brought LOW during the conversion
phase, the EOC bit (SDO pin) will be driven HIGH. Once
the conversion is complete, if CS is brought LOW, EOC will
be driven LOW indicating the conversion is complete and
the result is ready to be shifted out of the device.
Chip Select (CS)
The active low CS pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while CS is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
CS must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 32 data bits read) or by pulling
CS HIGH any time between the ﬁrst and 32nd rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input channel, rejection frequency, speed multiplier and to access
the integrated temperature sensor. Data is shifted into the
device during the data output/input state on the rising edge
of SCK while CS is low.
OUTPUT DATA FORMAT
The LTC2498 serial output stream is 32 bits long. The
ﬁrst bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 24 bits are the conversion result, MSB ﬁrst. The
remaining 5 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (ﬁrst output bit) is the end of conversion (EOC)
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever CS is LOW. This
bit is HIGH during the conversion cycle, goes LOW once
the conversion is complete, and is HIGH-Z when CS is
HIGH.
2498fc
15
LTC2498
APPLICATIONS INFORMATION
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indicator (SIG). If the selected input (VIN = IN+ – IN–) is greater
than 0V, this bit is HIGH. If VIN < 0, this bit is LOW.
Bit 28 (fourth output bit) is the most signiﬁcant bit (MSB)
of the result. This bit in conjunction with Bit 29 also provides underrange and overrange indication. If both Bit 29
and Bit 28 are HIGH, the differential input voltage is above
+FS. If both Bit 29 and Bit 28 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2498 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 • VREF
0
0
1
1
0V ≤ VIN < 0.5 • VREF
0
0
1
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < –0.5 • VREF
0
0
0
0
Bits 28 to 5 are the 24-bit conversion result MSB ﬁrst.
Bit 5 is the least signiﬁcant bit (LSB24).
Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to
0 may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must ﬁrst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the ﬁrst
rising edge of SCK. Bit 30 is shifted out of the device on
the ﬁrst falling edge of SCK. The ﬁnal data bit (Bit 0) is
shifted out on the on the falling edge of the 31st SCK and
may be latched on the rising edge of the 32nd SCK pulse.
On the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins remains
between –0.3V and VCC + 0.3V (absolute maximum operating range) a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input voltages below –FS, the conversion result is clamped to the
value –FS – 1LSB.
CS
1
2
3
4
5
1
0
EN
SGL
ODD
EOC
“0”
SIG
MSB
6
7
8
9
A2
A1
A0
EN2
10
11
12
13
14
32
SCK
(EXTERNAL)
SDI
SDO
DON'T CARE
Hi-Z
IM
FA
FB
SPD
DON'T CARE
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17
CONVERSION
SLEEP
DATA INPUT/OUTPUT
BIT 0
CONVERSION
2498 F03
Figure 3. Channel Selection, Conﬁguration Selection and Data Output Timing
2498fc
16
LTC2498
APPLICATIONS INFORMATION
Table 2. Output Data Format
Differential Input Voltage
VIN*
VIN* ≥ 0.5 • VREF**
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
0
0
1
1
0
0
0
…
0
0.5 • VREF** – 1LSB
0
0
1
0
1
1
1
…
1
0.25 • VREF**
0
0
1
0
1
0
0
…
0
0.25 • VREF** – 1LSB
0
0
1
0
0
1
1
…
1
0
0
0
1
0
0
0
0
…
0
–1LSB
0
0
0
1
1
1
1
…
1
–0.25 • VREF**
0
0
0
1
1
0
0
…
0
–0.25 • VREF** – 1LSB
0
0
0
1
0
1
1
…
1
–0.5 • VREF**
0
0
0
1
0
0
0
…
0
VIN* < –0.5 • VREF**
0
0
0
0
1
1
1
…
1
*The differential input voltage VIN = IN+ – IN–. **The differential reference voltage VREF = REF+ – REF–.
INPUT DATA FORMAT
The LTC2498 serial input word is 13 bits long and contains
two distinct sets of data. The ﬁrst set (SGL, ODD, A2, A1,
A0) is used to select the input channel. The second set
of data (IM, FA, FB, SPD) is used to select the frequency
rejection, speed mode (1x, 2x), and temperature measurement.
After power up, the device initiates an internal reset cycle
which sets the input channel to CH0 – CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The ﬁrst
conversion automatically begins at power up using this
default conﬁguration. Once the conversion is complete,
a new word may be written into the device.
The ﬁrst 3 bits shifted into the device consist of two preenable bits and one enable bit. As demonstrated in Figure 3,
the ﬁrst three bits shifted into the device enable the device
conﬁguration and input channel selection. Valid settings for
these three bits are 000, 100 and 101. Other combinations
should be avoided. If the ﬁrst three bits are 000 or 100, the
following data is ignored (don’t care) and the previously
selected input channel and conﬁguration remain valid for
the next conversion.
If the ﬁrst 3 bits shifted into the device are 101, then the
next 5 bits select the input channel for the next conversion
cycle, see Table 3.
The ﬁrst input bit following the 101 sequence (SGL)
determines if the input selection is differential (SGL = 0)
or single-ended (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input. For
SGL = 1, one of 16 channels is selected as the positive
input. The negative input is COM for all single ended operations. The remaining 4 bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
The next serial input bit immediately following the input
channel selection is the enable bit for the conversion
conﬁguration (EN2). If this bit is set to 0, then the next
conversion is performed using the previously selected
converter conﬁguration. This is useful in systems using
the same rejection/speed for all input channels and for
backward compatibility with the LTC2418/LTC2414 families
of delta sigma ADCs.
A new conﬁguration can be loaded into the device by
setting EN2 = 1, see Table 4. The ﬁrst bit (IM) is used
to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next 2 bits (FA and FB) are used to set the rejection
frequency. The ﬁnal bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the ﬁnal conversion result) or the 2x output rate if SPD
= 1 (offset calibration disabled, multiplexing output rates
2498fc
17
LTC2498
APPLICATIONS INFORMATION
Table 3 Channel Selection
MUX ADDRESS
ODD/
SGL SIGN
A2
A1
CHANNEL SELECTION
A0
0
1
IN+
IN–
*0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
*Default at power up
2498fc
18
LTC2498
APPLICATIONS INFORMATION
Table 4. Converter Conﬁguration
1
0
EN
SGL
ODD
A2
A1
A0
EN2
IM
FA
FB
SPD
CONVERTER CONFIGURATION
1
0
0
X
X
X
X
X
X
X
X
X
X
Keep Previous
1
0
1
X
X
X
X
X
0
X
X
X
X
Keep Previous (Change Channel)
0
0
0
X
X
X
X
X
X
X
X
X
X
Keep Previous
1
0
1
X
X
X
X
X
1
0
0
0
0
External Input (See Table 3)
50Hz/60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
0
1
0
External Input (See Table 3)
50Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
1
0
0
External Input (See Table 3)
60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
0
0
0
1
External Input (See Table 3)
50Hz/60Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
0
0
1
1
External Input (See Table 3)
50Hz Rejection, 2x
1
0
1
X
X
X
X
X
1
1
0
0
X
Measure Temperature
50Hz/60Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
1
0
1
X
Measure Temperature
50Hz Rejection, 1x
1
0
1
X
X
X
X
X
1
1
1
0
X
Measure Temperature
60Hz Rejection, 1x
up to 15Hz with no latency). When IM = 1 (temperature
measurement), SPD will be ignored and the device will
operate in 1x mode. The conﬁguration remains valid until
a new input word with EN = 1 (the ﬁrst 3 bits are 101) and
EN2 = 1 is shifted into the device.
unchanged from the 1x mode performance. In both the 1x
and 2x mode there is no latency. This enables input steps
or multiplexer changes to settle in a single conversion
cycle easing system overhead and increasing the effective
conversion rate. During temperature measurements, the 1x
mode is always used independent of the value of SPD.
Rejection Mode (FA, FB)
The LTC2498 includes a high accuracy on-chip oscillator
with no required external components. Coupled with an
integrated 4th order digital low pass ﬁlter, the LTC2498 rejects line frequency noise. In the default mode, the LTC2498
simultaneously rejects 50Hz and 60Hz by at least 87dB. If
more rejection is required, the LTC2498 can be conﬁgured
to reject 50Hz or 60Hz to better than 110dB.
Temperature Sensor
Speed Mode (SPD)
The digital output is proportional to the absolute temperature of the device. This feature allows the converter
to perform cold junction compensation for external
thermocouples or continuously remove the temperature
effects of external sensors.
Every conversion cycle, two conversions are combined to
remove the offset (default mode). This result is free from
offset and drift. In applications where the offset is not
critical, the auto-calibration feature can be disabled with
the beneﬁt of twice the output rate. While operating in the
2x mode (SPD = 1), the linearity and full-scale errors are
The LTC2498 includes an integrated temperature sensor.
The temperature sensor is selected by setting IM = 1.
During temperature readings, MUXOUTN/MUXOUTP
remains connected to the selected input channel. The
ADC internally connects to the temperature sensor and
performs a conversion.
The internal temperature sensor output is 28mV at 27°C
(300°K), with a slope of 93.5μV/°C independent of VREF.
2498fc
19
LTC2498
APPLICATIONS INFORMATION
Slope calibration is not required if the reference voltage (VREF) is known. A 5V reference has a slope of 314
LSBs24/°C. The temperature is calculated from the output
code (DATAOUT24) for a 5V reference using the following
formula:
TK = DATAOUT24/314 in Kelvin
If a different value of VREF is used, the temperature output
is:
DATAOUT24 • VREF
TK =
in Kelvin
1570
If the value of VREF is not known, the slope is determined by
measuring the temperature sensor at a known temperature
TN (in °K) and using the following formula:
SLOPE = DATAOUT24/TN
All Kelvin temperature readings can be converted to TC
(°C) using the fundamental equation:
TC = TK – 273
SERIAL INTERFACE TIMING MODES
The LTC2498’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several ﬂexible modes
of operation. These include internal/external serial clock,
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (FO = LOW or FO = HIGH) or an external oscillator
connected to the FO pin. For each mode, the operating cycle,
data input format, data output format, and performance
remain the same. Refer to Table 5 for a summary.
This value of slope can be used to calculate further temperature readings using:
TK = DATAOUT24/SLOPE
140000
5
VCC = 5V
VREF = 5V
120000 SLOPE = 314 LSB /K
24
4
ABSOLUTE ERROR (°C)
3
DATAOUT24
100000
80000
60000
40000
2
1
0
–1
–2
–3
20000
0
–4
0
100
–5
–55
400
200
300
TEMPERATURE (K)
–30
–5
20
45
70
TEMPERATURE (°C)
2498 F04
95
120
2498 F05
Figure 4. Internal PTAT Digital Output vs Temperature
Figure 5. Absolute Temperature Error
Table 5. LTC2498 Interface Timing Modes
CONFIGURATION
SCK
CONVERSION
DATA OUTPUT CONNECTION AND
SOURCE CYCLE CONTROL
CONTROL
WAVEFORMS
External SCK, Single Cycle
Conversion
External
CS and SCK
CS and SCK
Figures 6, 7
External SCK, 3-Wire I/O
External
SCK
SCK
Figure 8
Internal SCK, Single Cycle
Conversion
Internal
CS↓
CS↓
Figures 9, 10
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal
Continuous
Internal
Figure 11
2498fc
20
LTC2498
APPLICATIONS INFORMATION
External Serial Clock, Single Cycle Operation
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the ﬁrst rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on each rising edge of SCK (including the ﬁrst rising
edge). The channel selection and converter conﬁguration
mode will be used for the following conversion cycle. If
the input channel or converter conﬁguration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on
the ﬁrst rising edge of SCK and the last bit of the conversion result can be latched on the 32nd rising edge of SCK.
On the 32nd falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 6.
The external serial clock mode is selected during the powerup sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
2.7V TO 5.5V
10μF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2498
0.1μF
29
REFERENCE
VOLTAGE
0.1V TO VCC
30
8
•
•
•
ANALOG
INPUTS
FO
15
16
•
•
•
23
7
REF+
REF–
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(EXTERNAL)
SDI
DON'T CARE
Hi-Z
SDO
IM
FA
SLEEP
SPD
DON'T CARE
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
BIT 20 BIT 19
DATA INPUT/OUTPUT
BIT 18 BIT 17
BIT 0
CONVERSION
2498 F06
Figure 6. External Serial Clock, Single Cycle Operation
2498fc
21
LTC2498
APPLICATIONS INFORMATION
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 32nd falling edge of SCK, see Figure 7. On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter conﬁguration remains
unchanged. In order to program both the input channel
and converter conﬁguration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally
generated serial clock (SCK) signal, see Figure 8. CS is
permanently tied to ground, simplifying the user interface
or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
On the falling edge of EOC, the conversion result is load-
2.7V TO 5.5V
10μF
28
VCC
FO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2498
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF+
30
REF–
8
•
•
•
ANALOG
INPUTS
15
16
•
•
•
23
7
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
1
0
EN
SGL
ODD
A2
A1
A0
EOC
“0”
SIG
MSB
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24
CONVERSION
SLEEP
DON'T CARE
DATA INPUT/OUTPUT
BIT 23
CONVERSION
SLEEP
2498 F07
Figure 7. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
2498fc
22
LTC2498
APPLICATIONS INFORMATION
2.7V TO 5.5V
10μF
28
VCC
FO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2498
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF+
30
–
8
•
•
•
ANALOG
INPUTS
15
16
•
•
•
23
7
REF
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
38
3-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(EXTERNAL)
SDI
DON'T CARE
SDO
IM
FA
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
SPD
BIT 20 BIT 19
DATA INPUT/OUTPUT
SLEEP
DON'T CARE
BIT 18 BIT 17
BIT 0
CONVERSION
2498 F08
Figure 8. External Serial Clock, 3-Wire Operation (CS = 0)
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the falling edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
32nd falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 9.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be ﬂoating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (FO is tied LOW),
the ﬁrst rising edge of SCK occurs 12μs (tEOCTEST = 12μs)
after the falling edge of CS. If FO is driven by an external
oscillator of frequency fEOSC, then tEOCTEST = 3.6/fEOSC.
If CS remains LOW longer than tEOCTEST, the ﬁrst rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 32nd rising edge of SCK a new conversion automatically begins. SDO goes HIGH (EOC = 1) and SCK
2498fc
23
LTC2498
APPLICATIONS INFORMATION
2.7V TO 5.5V
10μF
28
VCC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
FO
LTC2498
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
REF+
SDI
30
REF–
SCK
8
•
•
•
15
16
ANALOG
INPUTS
•
•
•
VCC
29
23
7
34
CH0
•
•
•
CH7
SDO
CH8
•
CS
OPTIONAL
10k
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
<tEOCTEST
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
SLEEP
SPD
DON'T CARE
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
BIT 20 BIT 19
DATA INPUT/OUTPUT
BIT 18 BIT 17
BIT 0
CONVERSION
2498 F09
Figure 9. Internal Serial Clock, Single Cycle Operation
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling CS HIGH any time between the 1st rising edge and
the 32nd falling edge of SCK, see Figure 10. On the rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter conﬁguration remains
unchanged. In order to program both the input channel
and converter conﬁguration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 11. In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is ﬂoating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has ﬁnished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
2498fc
24
LTC2498
APPLICATIONS INFORMATION
2.7V TO 5.5V
10μF
28
VCC
FO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2498
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
REF+
SDI
30
REF–
SCK
8
•
•
•
15
16
ANALOG
INPUTS
•
•
•
VCC
29
23
7
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
OPTIONAL
10k
38
4-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
<tEOCTEST
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
16
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
FB
DON'T CARE
Hi-Z
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
SPD
SLEEP
BIT 20 BIT 19
BIT 18 BIT 17
DATA INPUT/OUTPUT
CONVERSION
2498 F10
Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Conﬁguration Selection
2.7V TO 5.5V
10μF
28
VCC
FO
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
35
LTC2498
0.1μF
REFERENCE
VOLTAGE
0.1V TO VCC
29
REF+
30
–
8
•
•
•
ANALOG
INPUTS
15
16
•
•
•
23
7
REF
VCC
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
34
OPTIONAL
10k
38
3-WIRE
SPI INTERFACE
37
36
•
•
CH15
COM
GND
1,3,4,5,6,31,32,33,39
CS
1
2
3
4
5
6
7
8
9
1
0
EN
SGL
ODD
A2
A1
A0
EN2
EOC
“0”
SIG
MSB
10
11
12
13
14
32
SCK
(INTERNAL)
SDI
DON'T CARE
SDO
IM
FA
BIT 31 BIT 30 BIT 29 BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
CONVERSION
FB
SPD
BIT 20 BIT 19
DATA INPUT/OUTPUT
DON'T CARE
BIT 18 BIT 17
BIT 0
CONVERSION
2498 F11
Figure 11. Internal Serial Clock, Continuous Operation
2498fc
25
LTC2498
APPLICATIONS INFORMATION
The input data is shifted through the SDI pin on the rising edge of SCK (including the ﬁrst rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 32nd rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is ﬂoating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2498’s internal pull-up at
SCK is disabled. Normally, SCK is not externally driven if
the device is operating in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If the driver goes Hi-Z after outputting a
LOW signal, the internal pull-up is disabled. An external
10k pull-up resistor prevents the device from exiting the
internal SCK mode under this condition.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. If CS goes HIGH before the time tEOCtest,
the internal pull-up is activated. If SCK is heavily loaded,
the internal pull-up may not restore SCK to a HIGH state
before the next falling edge of CS. The external 10k pull-up
resistor prevents the device from exiting the internal SCK
mode under this condition.
PRESERVING THE CONVERTER ACCURACY
The LTC2498 is designed to reduce as much as possible
sensitivity to device decoupling, PCB layout, anti-aliasing
circuits, line frequency perturbations, and temperature
sensitivity. In order to achieve maximum performance a
few simple precautions should be observed.
Digital Signal Levels
The LTC2498’s digital interface is easy to use. Its digital
inputs (SDI, FO, CS, and SCK in external serial clock mode)
accept standard CMOS logic levels. Internal hysteresis
circuits can tolerate edge transition times as slow as
100μs.
The digital input signal range is 0.5V to VCC – 0.5V. During
transitions, the CMOS input circuits draw dynamic current. For optimal performance, application of signals to
the serial data interface should be reserved for the sleep
and data output periods.
During the conversion period, overshoot and undershoot
of fast digital signals applied to both the serial digital interface and the external oscillator pin (FO) may degrade
the converter performance. Undershoot and overshoot
occur due to impedance mismatch of the circuit board
trace at the converter pin when the transition time of an
external control signal is less than twice the propagation
delay from the driver to the input pin. For reference, on a
regular FR-4 board, the propagation delay is approximately
183ps/inch. In order to prevent overshoot, a driver with
a 1ns transition time must be connected to the converter
through a trace shorter than 2.5 inches. This becomes
difﬁcult when shared control lines are used and multiple
reﬂections occur.
Parallel termination near the input pin of the LTC2498 will
eliminate this problem, but will increase the driver power
dissipation. A series resistor from 27Ω to 54Ω (depending on the trace impedance and connection) placed near
the driver will also eliminate over/under shoot without
additional driver power dissipation.
For many applications, the serial interface pins (SCK, SDI,
CS, FO) remain static during the conversion cycle and
no degradation occurs. On the other hand, if an external
oscillator is used (FO driven externally) it is active during
the conversion cycle. Moreover, the digital ﬁlter rejection
is minimal at the clock rate applied to FO. Care must be
taken to ensure external inputs and reference lines do not
cross this signal or run near it. These issues are avoided
when using the internal oscillator.
2498fc
26
LTC2498
APPLICATIONS INFORMATION
Driving the Input and Reference
terminals in order to ﬁlter unwanted noise (anti-aliasing)
results in incomplete settling.
The input and reference pins of the LTC2498 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simpliﬁed equivalent circuit is
shown in Figure 12.
The LTC2498 offers two methods of removing these errors.
The ﬁrst is an automatic differential input current cancellation (Easy Drive) and the second is the insertion of buffer
between the MUXOUT and ADCIN pins, thus isolating the
input switching from the source resistance.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
When using the LTC2498’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the input/reference pins. If the total external RC time constant
is less then 580ns the errors introduced by the sampling
process are negligible since complete settling occurs.
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns requied
for 1ppm accuracy. For example, a 10k bridge driving a
0.1μF capacitor has a time constant an order of magnitude
greater than the required maximum.
Typically, the reference inputs are driven from a low impedance source. In this case complete settling occurs even
with large external bypass capacitors. The inputs (CH0 to
CH15, COM), on the other hand, are typically driven from
larger source resistances. Source resistances up to 10k
may interface directly to the LTC2498 and settle completely;
however, the addition of external capacitors at the input
IIN+
INPUT
MULTIPLEXER
INTERNAL
SWITCH
NETWORK
EXTERNAL
CONNECTION
100Ω
IN+
The LTC2498 uses a propriatary switching algorithm
that forces the average differential input current to zero
10k
MUXOUTP
ADCINP
( )
I IN+
IIN–
100Ω
IN–
IREF
+
ADCINN
AVG
AVG
VIN(CM) VREF(CM)
=
(
0.5•REQ
1.5VREF + VREF(CM) – VIN(CM)
0.5 • REQ
)–
VIN2
VREF • REQ
VREF = REF + REF CEQ
12pF
10k
REF + – REF VREF(CM) = 2
VIN = IN+ IN , WHERE IN+ AND IN ARE THE SELECTED INPUT CHANNELS
IN+ – IN VIN(CM) = 2
REQ = 2.71M INTERNAL OSCILLATOR 60Hz MODE
–
REF–
)
( )
= I IN–
where:
EXTERNAL
CONNECTION
REF+
IREF
(
I REF +
10k
MUXOUTN
AVG
10k
2498 F12
REQ = 2.98M INTERNAL OSCILLATOR 50Hz/60Hz MODE
(
)
REQ = 0.833• 1012 /fEOSC EXTERNAL OSCILLATOR
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 12. LTC2498 Equivalent Analog Input Circuit
2498fc
27
LTC2498
APPLICATIONS INFORMATION
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and common mode input current are zero. The accuracy of the
converter is not compromised by settling errors.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common mode
of 1.5V, the common mode input current is approximately
0.74μA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current does not degrade the accuracy
if the source impedances tied to IN+ and IN– are matched.
Mismatches in source impedance lead to a ﬁxed offset
error but do not effect the linearity or full scale reading.
A 1% mismatch in a 1k source resistance leads to a 74μV
shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2498, leading
to little degradation in accuracy. Mismatches in source
impedances lead to gain errors proportional to the difference between the common mode input and common
mode reference. 1% mismatches in 1k source resistances
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA Max) results
in a small offset shift. A 1k source resistance will create a
1μV typical and a 10μV maximum offset voltage.
Automatic Offset Calibration of External Buffers/
Ampliﬁers
In addition to the Easy Drive input current cancellation,
the LTC2498 enables an external amplifer to be inserted
between the multiplexer output and the ADC input, see
Figure 13. This is useful in applications where balanced
source impedances are not possible. One pair of external
buffers/amplifers can be shared between all 17 analog
inputs. The LTC2498 performs an internal offset calibration
every conversion cycle in order to remove the offset and
drift of the ADC. This calibration is performed through a
combination of front end switching and digital processing. Since the external ampliﬁer is placed between the
multiplexer and the ADC, it is inside this correction loop.
This results in automatic offset correction and offset drift
removal of the external amplifer.
LTC2498
ANALOG 17
INPUTS
SDI
ΔΣ ADC
WITH
EASY DRIVE
INPUTS
INPUT
MUX
MUXOUTN
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current in the negative input (IIN–). Over the complete
conversion cycle, the average input current (IIN+ – IIN–)
is zero. While the differential input current is zero, the
common mode input current (IIN+ + IIN–)/2 is proportional
to the difference between the common mode input voltage (VIN(CM)) and the common mode reference voltage
(VREF(CM)).
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the accuracy of the internal oscillator, a one-time calibration will
remove this error.
MUXOUTP
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
of buffers.
SCK
SDO
CS
2
–
1/2 LTC6078
3
6
1k
0.1μF
+
–
1/2 LTC6078
5
1
+
7
1k
0.1μF
2498 F13
Figure 13. External Buffers Provide High Impedance Inputs and
Ampliﬁer Offsets are Automatically Cancelled.
2498fc
28
LTC2498
APPLICATIONS INFORMATION
Reference Current
Similar to the analog inputs, the LTC2498 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete settling occurs (as a function the reference source resistance
and reference bypass capacitance) linearity and gain errors
are introduced.
For relatively small values of external reference capacitance (CREF < 1nF), the voltage on the sampling capacitor
settles for reference impedances of many kΩ (if CREF =
100pF up to 10k will not degrade the performance), see
Figures 14, 15.
In cases where large bypass capacitors are required on
the reference inputs (CREF > 0.01μF) full-scale and linearity errors are proportional to the value of the reference
90
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
80
+FS ERROR (ppm)
70
60
50
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
40
30
10
0
0
10
1k
100
RSOURCE (Ω)
0
–10
–20
–30
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
–40
–50
VCC = 5V
–60 VREF = 5V
V + = 1.25V
–70 VIN– = 3.75V
IN
–80 FO = GND
TA = 25°C
–90
10
0
1k
100
RSOURCE (Ω)
10k
100k
2498 F15
Figure 15. –FS Error vs RSOURCE at VREF (Small CREF)
resistance. Every ohm of reference resistance produces
a full-scale error of approximately 0.5ppm (while operating in simultaneous 50Hz/60Hz mode), see Figures 16
and 17. If the input common mode voltage is equal to
the reference common mode voltage, a linearity error of
approximately 0.67ppm per 100Ω of reference resistance
results, see Figure 18. In applications where the input and
reference common mode voltages are different, the errors
increase. A 1V difference in between common mode input
and common mode reference results in a 6.7ppm INL error
for every 100Ω of reference resistance.
In addition to the reference sampling charge, the reference
ESD projection diodes have a temperature dependent leakage current. This leakage current, nominally 1nA (±10nA
max) results in a small gain error. A 100Ω reference
resistance will create a 0.5μV full scale error.
Normal Mode Rejection and Anti-aliasing
20
–10
10
–FS ERROR (ppm)
The LTC6078 is an excellent ampliﬁer for this function.
It operates with supply voltages as low as 2.7V and its
noise level is 18nV/√Hz. The Easy Drive input technology
of the LTC2498 enables an RC network to be added directly
to the output of the LTC6078. The capacitor reduces the
magnitude of the current spikes seen at the input to the
ADC and the resistor isolates the capacitor load from the
op-amp output enabling stable operation.
10k
100k
2498 F14
Figure 14. +FS Error vs RSOURCE at VREF (Small CREF)
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ﬁltering. Combined
with a large oversample ratio, the LTC2498 signiﬁcantly
simpliﬁes anti-aliasing ﬁlter requirements. Additionally,
the input current cancellation feature allows external low
pass ﬁltering without degrading the DC performance of
the device.
2498fc
29
LTC2498
APPLICATIONS INFORMATION
500
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
+FS ERROR (ppm)
400
300
CREF = 1μF, 10μF
CREF = 0.1μF
200
CREF = 0.01μF
100
0
200
0
600
400
RSOURCE (Ω)
800
1000
2498 F16
Figure 16. +FS Error vs RSOURCE at VREF (Large CREF)
The SINC4 digital ﬁlter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS), see Figures 19
and 20. The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
fS = FEOSC/20 when operating with an external oscillator
of frequency FEOSC.
When using the internal oscillator, the LTC2498 is designed
to reject line frequencies. As shown in Figure 21, rejection nulls occur at multiples of frequency fN, where fN is
determined by the input control bits FA and FB (fN = 50Hz
or 60Hz or 55Hz for simultaneous rejection). Multiples of
the modulator sampling rate (fS = fN • 256) only reject noise
0
–FS ERROR (ppm)
–100
CREF = 0.01μF
–200
CREF = 1μF, 10μF
–300
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
–400
–500
0
200
CREF = 0.1μF
600
400
RSOURCE (Ω)
800
INPUT NORMAL MODE REJECTION (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
1000
2498 F17
Figure 17. –FS Error vs RSOURCE at VREF (Large CREF)
2498 F19
Figure 19. Input Normal Mode Rejection, Internal Oscillator
and 50Hz Rejection Mode
0
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10μF
INPUT NORMAL MODE REJECTION (dB)
INL (ppm OF VREF)
10
R = 1k
2
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
–10
–0.5
–0.3
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0.1
–0.1
VIN/VREF (V)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0.3
0.5
2498 F18
Figure 18. INL vs Differential Input Voltage and Reference
Source Resistance for CREF > 1μF
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2498 F20
Figure 20. Input Normal Mode Rejection, Internal Oscillator
and 60Hz Rejection Mode
2498fc
30
LTC2498
APPLICATIONS INFORMATION
to 15dB (see Figure 22), if noise sources are present at
these frequencies anti-aliasing will reduce their effects.
Traditional high order delta-sigma modulators suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2498 third
order modulator resolves this problem and guarantees
stability with input signals 150% of full-scale. In many
industrial applications, it is not uncommon to have microvolt level signals superimposed over unwanted volt
level error sources with several volts of peak-to-peak
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2498 F23
Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)
0
fN = fEOSC/5120
–10
MEASURED DATA
CALCULATED DATA
–20
–120
NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
0
NORMAL MODE REJECTION (dB)
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 23, 24,
and 25. Measured values of normal mode rejection are
shown superimposed over the theoretical values in all
three rejection modes.
0
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
–120
8fN
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2498 F21
Figure 21. Input Normal Mode Rejection at DC
2498 F24
Figure 24. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)
0
NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
0
MEASURED DATA
CALCULATED DATA
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2498 F22
Figure 22. Input Normal Mode Rejection at fS = 256 • fN
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
2498 F25
Figure 25. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
2498fc
31
LTC2498
APPLICATIONS INFORMATION
Using the 2x speed mode of the LTC2498 alters the rejection characteristics around DC and multiples of fS. The
device bypasses the offset calibration in order to increase
the output rate. The resulting rejection plots are shown
in Figures 28 and 29. 1x type frequency rejection can be
achieved using the 2x mode by performing a running
average of the conversion results, see Figure 30.
Output Data Rate
When using its internal oscillator, the LTC2498 produces up
to 7.5 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
–100
–120
of the sleep and data output cycles which are controlled
by the user and can be made insigniﬁcantly short. When
operating with an external conversion clock (FO connected
to an external oscillator), the LTC2498 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSC over the nominal 307.2kHz will translate
into a proportional increase in the maximum output data
rate (up to a maximum of 100sps). The increase in output
rate leads to degradation in offset, full-scale error, and effective resolution as well as a shift in frequency rejection.
When using the integrated temperature sensor, the internal
oscillator should be used (fO = 0) or an external oscillator
applied to fO, fEOSC, should be set to 307.2kHz Max.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
0
INPUT NORMAL REJECTION (dB)
noise. Figures 26 and 27 show measurement results for
the rejection of a 7.5V peak-to-peak noise source (150%
of full scale) applied to the LTC2498. From these curves,
it is shown that the rejection performance is maintained
even in extremely noisy environments.
–20
–40
–60
–80
–100
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (fN)
8fN
2498 F26
2498 F28
Figure 26. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
Figure 28. Input Normal Mode Rejection 2x Speed Mode
NORMAL MODE REJECTION (dB)
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
INPUT NORMAL REJECTION (dB)
0
0
–20
–40
–60
–80
–100
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (fN)
2498 F29
2498 F27
Figure 27. Measure Input Normal Mode Rejection vs Input
Frequency With input Perturbation of 150% (50Hz Notch)
Figure 29. Input Normal Mode Rejection 2x Speed Mode
2498fc
32
LTC2498
APPLICATIONS INFORMATION
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the effectiveness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full scale errors, and
decreased resolution, see Figures 31 to 38.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
50
NO AVERAGE
–90
WITH
RUNNING
AVERAGE
–100
–110
–120
–130
3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
40
3000
+FS ERROR (ppm OF VREF)
–80
OFFSET ERROR (ppm OF VREF)
NORMAL MODE REJECTION (dB)
–70
30
TA = 85°C
20
10
2500
TA = 85°C
2000
1500
0
500
–10
0
60
62
54 56
58
48 50
52
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
Figure 30. Input Normal Mode Rejection
2x Speed Mode with and Without Running
Averaging
2498 F32
Figure 31. Offset Error vs Output Data
Rate and Temperature
0
Figure 32. +FS Error vs Output Data
Rate and Temperature
24
22
TA = 25°C
–500
22
20
RESOLUTION (BITS)
–1000
TA = 25°C
–1500
TA = 85°C
–2000
–2500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
20
18
16
14
12
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2498 F33
Figure 33.–FS Error vs Output Data Rate
and Temperature
RESOLUTION (BITS)
–FS ERROR (ppm OF VREF)
TA = 85°C
–3500
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2498 F31
2498 F30
–3000
TA = 25°C
1000
TA = 25°C
–140
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
10
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2498 F34
Figure 34. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
18
TA = 85°C
TA = 25°C
16
14
VIN(CM) = VREF(CM)
12 VCC = VREF = 5V
FO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2498 F35
Figure 35. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
2498fc
33
LTC2498
APPLICATIONS INFORMATION
24
VIN(CM) = VREF(CM)
VIN = 0V
15 FO = EXT CLOCK
TA = 25°C
22
VCC = VREF = 5V
5
0
–5
VCC = 5V, VREF = 2.5V
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F36
Figure 36. Offset Error vs Output Data
Rate and Reference Voltage
20
20
VCC = 5V, VREF = 2.5V
18
16
14 VIN(CM) = VREF(CM)
VIN = 0V
FO = EXT CLOCK
12 T = 25°C
A
RES = LOG 2 (VREF/NOISERMS)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2498 F37
Figure 37. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
RESOLUTION (BITS)
10
–10
22
VCC = VREF = 5V
RESOLUTION (BITS)
OFFSET ERROR (ppm OF VREF)
20
18
VCC = VREF = 5V
16
VCC = 5V, VREF = 2.5V
VIN(CM) = VREF(CM)
14
VIN = 0V
REF– = GND
12 FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2498 F38
Figure 38. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference
Voltage
2498fc
34
LTC2498
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 p 0.05
5.50 p 0.05
5.15 ± 0.05
4.10 p 0.05
3.15 ± 0.05
3.00 REF
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 p 0.10
0.75 p 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 p0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
7.00 p 0.10
5.50 REF
3.15 ± 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 p 0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2498fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC2498
TYPICAL APPLICATION
External Buffers Provide High Impedance Inputs and Ampliﬁer Offsets are Automatically Cancelled.
LTC2498
ΔΣ ADC
WITH
EASY DRIVE
INPUTS
MUXOUTN
INPUT
MUX
MUXOUTP
ANALOG 17
INPUTS
SDI
SCK
SDO
CS
2
–
1/2 LT6078
3
6
1k
0.1μF
+
–
1/2 LT6078
5
1
7
1k
0.1μF
+
2498 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790
Micropower SOT-23 Low Dropout Reference Family
0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ΔΣ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410
24-Bit, No Latency ΔΣ ADC with Differential Inputs
0.8μVRMS Noise, 2ppm INL
LTC2411/LTC2411-1 24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP
24-Bit, No Latency ΔΣ ADC with Differential Inputs
LTC2413
LTC2415/LTC2415-1 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
1.45μVRMS Noise, 4ppm INL, Simultaneous 50Hz/60Hz
Rejection (LTC2411-1)
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
Pin Compatible with the LTC2410
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency ΔΣ ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA
LTC2440
High Speed, Low Noise 24-Bit ΔΣ ADC
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2480
16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2482/LTC2484
LTC2481
16-Bit ΔΣ ADC with Easy Drive Inputs, 600nV Noise, I2C
Interface, Programmable Gain, and Temperature Sensor
Pin Compatible with LTC2483/LTC2485
LTC2482
16-Bit ΔΣ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2484
LTC2483
16-Bit ΔΣ ADC with Easy Drive Inputs, and I2C Interface
Pin Compatible with LTC2481/LTC2485
LTC2484
24-Bit ΔΣ ADC with Easy Drive Inputs
Pin Compatible with LTC2480/LTC2482
LTC2485
24-Bit ΔΣ ADC with Easy Drive Inputs, I2C Interface, and
Pin Compatible with LTC2481/LTC2483
Temperature Sensor
LTC2496
16-Bit 8-/16-Channel ΔΣ ADC with Easy Drive Input Current
Cancellation
Pin Compatible with LTC2498/LTC2449
2498fc
36 Linear Technology Corporation
LT 1008 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006

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