LTC3561 1A, 4MHz, Synchronous Step-Down DC/DC Converter U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®3561 is a constant-frequency, synchronous, step-down DC/DC converter. Intended for medium power applications, it operates from a 2.63V to 5.5V input voltage range and has a user configurable operating frequency up to 4MHz, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. The output voltage is adjustable from 0.8V to 5V. Internal synchronous 0.11Ω power switches with 1.4A peak current ratings provide high efficiency. The LTC3561’s current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Uses Tiny Capacitors and Inductor High Frequency Operation: Up to 4MHz High Switch Current: 1.4A Low RDS(ON) Internal Switches: 0.110Ω High Efficiency: Up to 95% VIN: 2.63V to 5.5V Stable with Ceramic Capacitors Current Mode Operation for Excellent Line and Load Transient Response Short-Circuit Protected Low Dropout Operation: 100% Duty Cycle Low Shutdown Current: IQ ≤ 1µA Low Quiescent Current: 240µA Output Voltages from 0.8V to 5V Low Noise Pulse-Skipping Operation Small 8-Pin DFN Package To further maximize battery life, the P-channel MOSFET is turned on continuously in dropout (100% duty cycle). The no-load quiescent current is only 240µA. In shutdown, the device draws <1µA. U APPLICATIO S ■ ■ ■ ■ Wireless LAN Power Notebook Computers Digital Cameras Cellular Phones Board Mounted Power Supplies U ■ , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6127815, 6304066, 6498466, 6580258, 6611131. TYPICAL APPLICATIO Step-Down 2.5V/1A Regulator Efficiency and Power Loss vs Load Current VIN 2.63V TO 5.5V 1000 100 95 22µF 90 ITH LTC3561 2.2µH SW 887k SHDN/RT 13k 1000pF SGND VFB 22µF 75 POWER LOSS 70 412k 60 55 NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE. 100 80 10 65 PGND 324k VOUT 2.5V/1A EFFICIENCY (%) SVIN 85 3561 F01 50 10 POWER LOSS (mW) PVIN EFFICIENCY VIN = 3.3V VOUT = 2.5V fO = 1MHz 100 LOAD CURRENT (mA) 1 1000 3561 TA01 3561f 1 LTC3561 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) TOP VIEW PVIN, SVIN Voltages .....................................– 0.3V to 6V VFB, SHDN/RT Voltages ................ – 0.3V to (VIN + 0.3V) ITH Voltage ................................................– 0.3V to 1.4V SW Voltage ................................... – 0.3V to (VIN + 0.3V) Operating Ambient Temperature Range (Note 2) .................................................. – 40°C to 85°C Junction Temperature (Notes 5, 8) ....................... 125°C Storage Temperature Range ................. – 65°C to 125°C SHDN/RT 1 8 ITH SGND 2 7 VFB 6 SVIN 5 PVIN 9 SW 3 PGND 4 DD PACKAGE 8-LEAD (3mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 3°C/W EXPOSED PAD (PIN 9) MUST BE SOLDERED TO GROUND ORDER PART NUMBER DD PART MARKING LTC3561EDD LCJJ Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V, RT = 324k unless otherwise specified. (Note 2) SYMBOL VIN IFB VFB ∆VLINEREG ∆VLOADREG PARAMETER Operating Voltage Range Feedback Pin Input Current Feedback Voltage Reference Voltage Line Regulation Output Voltage Load Regulation gm(EA) IS Error Amplifier Transconductance Input DC Supply Current (Note 4) Active Mode Shutdown Shutdown Threshold High Active Oscillator Resistor Oscillator Frequency VSHDN/RT fOSC ILIM RDS(ON) ISW(LKG) VUVLO Peak Switch Current Limit Top Switch On-Resistance (Note 6) Bottom Switch On-Resistance (Note 6) Switch Leakage Current Undervoltage Lockout Threshold CONDITIONS (Note 3) (Note 3) VIN = 2.7V to 5V ITH = 0.36, (Note 3) ITH = 0.84, (Note 3) ITH Pin Load = ±5µA (Note 3) ● MIN 2.625 TYP 0.784 0.8 0.04 0.02 – 0.02 800 ● ● VFB = 0.75V VSHDN/RT = 3.3V RT = 324k (Note 7) ITH = 1.3 VIN = 3.3V VIN = 3.3V VIN = 6V, VITH/RUN = 0V, VFB = 0V VIN Ramping Down Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. No pin shall exceed 6V. Note 2: The LTC3561E is guaranteed to meet specified performance from 0°C to 85°C. Specifications over the – 40°C to 85°C operating ambient 0.85 1.4 2.375 MAX 5.5 ±0.1 0.816 0.2 0.2 – 0.2 240 350 0.1 1 VIN – 0.6 VIN – 0.4 324k 1M 1 1.15 4 1.7 0.11 0.15 0.11 0.15 0.01 1 2.5 2.625 UNITS V µA V %/V % % µS µA µA V Ω MHz MHz A Ω Ω µA V temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3561 is tested in a feedback loop which servos VFB to the midpoint for the error amplifier (VITH = 0.6V). Note 4: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. 3561f 2 LTC3561 ELECTRICAL CHARACTERISTICS Note 8: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: TJ is calculated from the ambient TA and power dissipation PD according to the following formula: LTC3561EDD: TJ = TA + (PD • 43°C/W) Note 6: Switch on-resistance is guaranteed by correlation to wafer level measurements. Note 7: 4MHz operation is guaranteed by design but not production tested and is subject to duty cycle limitations (see Applications Information). U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs VIN Switching Waveforms Load Step 100 IOUT = 0.4A 95 VOUT 10mV/ DIV VOUT 100mV/ DIV EFFICIENCY (%) 90 IL1 100mA/ DIV IOUT = 1.0A 85 80 IL1 0.4A/ DIV 75 70 VIN = 3.3V 2µs/DIV VOUT = 2.5V ILOAD = 50mA CIRCUIT OF FIGURE 6 65 3561 G02.eps VIN = 3.3V 40µs/DIV VOUT = 2.5V ILOAD = 0.20A TO 1A CIRCUIT OF FIGURE 6 VOUT = 2.5V CIRCUIT OF FIGURE 6 60 2.5 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 3561 G06.eps 3561 G05 Load Regulation Line Regulation 0.4 VIN = 3.3V VOUT = 2.5V 0.3 10 VOUT = 1.8V TA = 25°C 0.45 0 –0.1 –0.2 FREQUENCY VARIATION (%) VOUT ERROR (%) 0.1 0.35 0.30 0.25 0.20 IOUT = 1.0A 0.15 IOUT = 400mA 6 4 2 0 –2 –4 –0.3 0.10 –0.4 0.05 –8 –0.5 0 –10 1 10 100 1000 LOAD CURRENT (mA) 10000 3561 G07 2 3 VOUT = 1.8V IOUT = 1A TA = 25°C 8 0.40 0.2 VOUT ERROR (%) Frequency vs VIN 0.50 4 VIN (V) 5 6 3561 G08 –6 2 3 4 VIN (V) 5 6 3561 G09 3561f 3 LTC3561 U W TYPICAL PERFOR A CE CHARACTERISTICS Frequency Variation vs Temperature Efficiency vs Frequency 100 10 EFFICIENCY (%) 0 –2 –4 TA = 25°C 115 95 RDS(ON) (mΩ) REFERENCE VARIATION (%) 6 2 120 VIN = 3.3V VOUT = 2.5V IOUT = 500mA TA = 25°C 8 4 RDS(ON) vs VIN 90 –6 110 SYNCHRONOUS SWITCH 105 MAIN SWITCH 100 95 –8 –10 –50 85 –25 0 25 50 75 TEMPERATURE (°C) 100 125 0 1 2 3 FREQUENCY (MHz) 3561 G10 4 3561 G11 90 2.5 3 3.5 4 4.5 VIN (V) 5 5.5 6 3561 G12 U U U PI FU CTIO S SHDN/RT (Pin 1): Combination Shutdown and Timing Resistor Pin. The oscillator frequency is programmed by connecting a resistor from this pin to ground. Forcing this pin to SVIN causes the device to be shut down. In shutdown all functions are disabled. PVIN (Pin 5): Main Supply Pin. Must be closely decoupled to PGND. SGND (Pin 2): The Signal Ground Pin. All small signal components and compensation components should be connected to this ground (see Board Layout Considerations). VFB (Pin 7): Receives the feedback voltage from the external resistive divider across the output. Nominal voltage for this pin is 0.8V. SW (Pin 3): The Switch Node Connection to the Inductor. This pin swings from PVIN to PGND. ITH (Pin 8): Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.5V. PGND (Pin 4): Main Power Ground Pin. Connect to the (–) terminal of COUT, and (–) terminal of CIN. SVIN (Pin 6): The Signal Power Pin. All active circuitry is powered from this pin. Must be closely decoupled to SGND. SVIN must be greater than or equal to PVIN. Exposed Pad (Pin 9): Thermal Connection to PCB. This pin should be soldered to ground to achieve rated thermal performance. 3561f 4 LTC3561 W BLOCK DIAGRA 0.8V SVIN SGND ITH PVIN 6 2 8 5 PMOS CURRENT COMPARATOR VOLTAGE REFERENCE ITH LIMIT + + VFB 7 – ERROR AMPLIFIER – – + VB SLOPE COMPENSATION OSCILLATOR 3 SW + LOGIC NMOS COMPARATOR – + REVERSE COMPARATOR – 4 PGND 1 SHDN/RT 3561 BD U OPERATIO The LTC3561 uses a constant frequency, current mode architecture. The operating frequency is determined by the value of the RT resistor. The output voltage is set by an external divider returned to the VFB pin. An error amplifier compares the divided output voltage with a reference voltage of 0.8V and adjusts the peak inductor current accordingly. Main Control Loop During normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the VFB voltage is below the reference voltage. The current into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the inductor flows through the bottom switch (Nchannel MOSFET) into the load until the next clock cycle. The peak inductor current is controlled by the voltage on the ITH pin, which is the output of the error amplifier. This amplifier compares the VFB pin to the 0.8V reference. When the load current increases, the VFB voltage decreases slightly below the reference. This decrease causes the error amplifier to increase the ITH voltage until the average inductor current matches the new load current. At low load currents, the inductor current becomes discontinuous, and pulses may be skipped to maintain regulation. The main control loop is shut down by pulling the SHDN/RT pin to SVIN. A digital soft-start is enabled after shutdown, which will slowly ramp the peak inductor current up over 1024 clock cycles or until the output reaches regulation, whichever is first. Soft-start can be lengthened by ramping the voltage on the ITH pin (see Applications Information section). Dropout Operation When the input supply voltage decreases toward the output voltage, the duty cycle increases to 100% which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. Low Supply Operation The LTC3561 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2.5V to prevent unstable operation. 3561f 5 LTC3561 U U W U APPLICATIO S I FOR ATIO A general LTC3561 application circuit is shown in Figure 4. External component selection is driven by the load requirement, and begins with the selection of the inductor L1. Once L1 is chosen, CIN and COUT can be selected. fO(MAX) ≈ 6.67 • (VOUT / VIN(MAX)) (MHz) The minimum frequency is limited by leakage and noise coupling due to the large resistance of RT. Operating Frequency Selection of the operating frequency is a tradeoff between efficiency and component size. High frequency operation allows the use of smaller inductor and capacitor values. Operation at lower frequencies improves efficiency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. The operating frequency, fO, of the LTC3561 is determined by an external resistor that is connected between the RT pin and ground. The value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: RT = 9.78 • 1011( fO ) −1.08 (Ω ) or can be selected using Figure 1. 4.5 The maximum usable operating frequency is limited by the minimum on-time and the duty cycle. This can be calculated as: Inductor Selection Although the inductor does not influence the operating frequency, the inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance and increases with higher VIN or VOUT: ∆IL = Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple, greater core losses, and lower output current capability. A reasonable starting point for setting ripple current is ∆IL = 0.4 × IOUT(MAX), where IOUT(MAX) is 1A. The largest ripple current ∆IL occurs at the maximum input voltage. To guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation: TA = 25°C 4.0 L= 3.5 FREQUENCY (MHz) VOUT ⎛ VOUT ⎞ • 1− f O• L ⎜⎝ V IN ⎟⎠ 3.0 VOUT f O• ∆IL ⎛ ⎞ V • ⎜ 1 − OUT ⎟ ⎝ V IN(MAX) ⎠ 2.5 Inductor Core Selection 2.0 1.5 1.0 0.5 0 0 500 1000 RT (kΩ) Figure 1. Frequency vs RT 1500 3561 F02 Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and do not radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3561 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3561 applications. 3561f 6 LTC3561 U U W U APPLICATIO S I FOR ATIO Table 1. Representative Surface Mount Inductors MANUFACTURER PART NUMBER Output Capacitor (COUT) Selection MAX DC VALUE CURRENT DCR HEIGHT Toko A914BYW-2R2M-D52LC 2.2µH 2.05A 49mΩ 2mm Coilcraft D01608C-222 2.2µH Coilcraft LP01704-222M 2.2µH 2.3A 70mΩ 3mm 2.4A 120mΩ 1mm Sumida CDRH2D18/HP-2R2 2.2µH 1.6A 48mΩ Taiyo Yuden N05DB2R2M 2.2µH 2.9A 32mΩ 2.8mm Murata LQN6C2R2M04 2.2µH 3.2A 24mΩ Cooper SD3112-2R2 2.2µH 1.1A 140mΩ 1.2mm TDK VLF3010AT-2R2M1R0 2.2µH 1.0A 100mΩ 1.0mm EPCO B82470A1222M 2.2µH 1.6A 90mΩ 1.2mm 2mm 5mm Input Capacitor (CIN) Selection In continuous mode, the input current of the converter is a square wave with a duty cycle of approximately VOUT/ VIN. To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: IRMS ≈ IMAX VOUT (VIN − VOUT ) VIN where the maximum average output current IMAX equals the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ∆IL/2. This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst case is commonly used to design because even significant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of the design. An additional 0.1µF to 1µF ceramic capacitor is also recommended on VIN for high frequency decoupling, when not using an all ceramic capacitor solution. The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering. The output ripple (∆VOUT) is determined by: ⎛ 1 ⎞ ∆VOUT ≈ ∆IL ⎜ ESR + 8fO C OUT ⎟⎠ ⎝ where f = operating frequency, COUT = output capacitance and ∆IL = ripple current in the inductor. The output ripple is highest at maximum input voltage since ∆IL increases with input voltage. With ∆IL = 0.3 • ILIM the output ripple will be less than 100mV at maximum VIN and fO = 1MHz with: ESRCOUT < 150mΩ Once the ESR requirements for COUT have been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement, except for an all ceramic solution. In surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, ESR or RMS current handling requirement of the application. Aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. The OS-CON semiconductor dielectric capacitor available from Sanyo has the lowest ESR(size) product of any aluminum electrolytic at a somewhat higher price. Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density than other types. Tantalum capacitors have the highest capacitance density, but it has a larger ESR and it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. Aluminum electrolytic capacitors have a significantly larger ESR, and is often used in extremely cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have the lowest ESR and cost but also have the lowest capacitance density, a high voltage and temperature coefficient and exhibit audible 3561f 7 LTC3561 U W U U APPLICATIO S I FOR ATIO piezoelectric effects. In addition, the high Q of ceramic capacitors along with trace inductance can lead to significant ringing. Other capacitor types include the Panasonic specialty polymer (SP) capacitors. In most cases, 0.1µF to 1µF of ceramic capacitors should also be placed close to the LTC3561 in parallel with the main capacitors for high frequency decoupling. Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting for switching regulator use because of their very low ESR. Unfortunately, the ESR is so low that it can cause loop stability problems. Solid tantalum capacitor ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in giving acceptable loop phase margin. Ceramic capacitors remain capacitive to beyond 300kHz and usually resonate with their ESL before ESR becomes effective. Also, ceramic caps are prone to temperature effects which requires the designer to check loop stability over the operating temperature range. To minimize their large temperature and voltage coefficients, only X5R or X7R ceramic capacitors should be used. A good selection of ceramic capacitors is available from Taiyo Yuden, TDK and Murata. Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the VIN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. Since the ESR of a ceramic capacitor is so low, the input and output capacitor must instead fulfill a charge storage requirement. During a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. The time required for the feedback loop to respond is dependent on the compensation components and the output capacitor size. Typically, 3 to 4 cycles are required to respond to a load step, but only in the first cycle does the output drop linearly. The output droop, VDROOP, is usually about 2 to 3 times the linear drop of the first cycle. Thus, a good place to start is with the output capacitor size of approximately: C OUT ≈ 2.5 ∆IOUT fO • VDROOP More capacitance may be required depending on the duty cycle and load step requirements. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. A 10µF ceramic capacitor is usually enough for these conditions. Setting the Output Voltage The LTC3561 develops a 0.8V reference voltage between the feedback pin, VFB, and the signal ground as shown in Figure 4. The output voltage is set by a resistive divider according to the following formula: ⎛ R2⎞ VOUT ≈ 0.8V ⎜ 1 + ⎟ ⎝ R1⎠ Keeping the current small (<5µA) in these resistors maximizes efficiency, but making them too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. Shutdown and Soft-Start The SHDN/RT pin is a dual purpose pin that sets the oscillator frequency and provides a means to shut down the LTC3561. This pin can be interfaced with control logic in several ways, as shown in Figure 2(a) and Figure 2(b). The ITH pin is primarily for loop compensation, but it can also be used to increase the soft-start time. Soft-start 3561f 8 LTC3561 U U W U APPLICATIO S I FOR ATIO reduces surge currents from VIN by gradually increasing the peak inductor current. Power supply sequencing can also be accomplished using this pin. The LTC3561 has an internal digital soft-start which steps up a clamp on ITH over 1024 clock cycles, as can be seen in Figure 3. The soft-start time can be increased by ramping the voltage on ITH during start-up as shown in Figure 2(c). As the voltage on ITH ramps through its operating range the internal peak current limit is also ramped at a proportional linear rate. Checking Transient Response The OPTI-LOOP compensation allows the transient response to be optimized for a wide range of loads and output capacitors. The availability of the ITH pin not only allows optimization of the control loop behavior but also provides a DC coupled and AC filtered closed loop response test point. The DC step, rise time and settling at this test point truly reflects the closed loop response. Assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. The bandwidth can also be estimated by examining the rise time at the pin. The ITH external components shown in the front page circuit will provide an adequate starting point for most applications. The series R-C filter sets the dominant polezero loop compensation. The values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final PC layout is SHDN/RT SHDN/RT RT RT RUN done and the particular output capacitor type and value have been determined. The output capacitors need to be selected because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD • ESR, where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The initial output voltage step may not be within the bandwidth of the feedback loop, so the standard second order overshoot/DC ratio cannot be used to determine phase margin. The gain of the loop increases with R and the bandwidth of the loop increases with decreasing C. If R is increased by the same factor that C is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. In addition, a feedforward capacitor CF can be added to improve the high frequency response, as shown in Figure 5. Capacitor CF provides phase lead by creating a high frequency zero with R2 which improves the phase margin. SVIN 1M VIN 2V/DIV RUN 3561 F03a 3561 F03b (2a) RUN OR VIN (2b) ITH R1 D1 C1 RC VOUT 2V/DIV IL 500mA/DIV VIN = 3.3V VOUT = 2.5V RL = 1.4Ω CC 3561 F03c (2c) Figure 2. SHDN/RT Pin Interfacing and External Soft-Start 200µs/DIV 3411 F04.eps Figure 3. Digital Soft-Start 3561f 9 LTC3561 U U W U APPLICATIO S I FOR ATIO The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Linear Technology Application Note 76. produce the most improvement. Percent efficiency can be expressed as: Although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage VIN drops toward VOUT, the load step capability does decrease due to the decreasing voltage across the inductor. Applications that require large load step capability near dropout should use a different topology such as SEPIC, Zeta or single inductor, positive buck/ boost. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3561 circuits: 1) LTC3561 VIN current, 2) switching losses, 3) I2R losses, 4) other losses. %Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. 1) The VIN current is the DC supply current given in the electrical characteristics which excludes MOSFET driver and control currents. VIN current results in a small (<0.1%) loss that increases with VIN, even at no load. In some applications, a more severe transient can be caused by switching in loads with large (>1uF) input capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. The solution is to limit the turnon speed of the load switch driver. A hot swap controller is designed specifically for this purpose and usually incorporates current limiting, short-circuit protection, and softstarting. 2) The switching current is the sum of the MOSFET driver and control currents. The MOSFET driver current results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC bias current. In continuous mode, IGATECHG = fO(QT + QB), where QT and QB are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. Efficiency Considerations 3) I2R Losses are calculated from the DC resistances of the internal switches, RSW, and external inductor, RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the internal top and bottom switches. Thus, the series resistance The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would VIN 2.63V TO 5.5V + C6 CIN R6 SVIN PGND SW PVIN L1 D1 OPTIONAL C8 PGND LTC3561 VOUT CF + COUT C5 PGND ITH CITH RC CC SGND PGND VFB PGND SHDN/RT R1 PGND R2 RT 3561 F05 Figure 4. LTC3561 General Schematic 3561f 10 LTC3561 U W U U APPLICATIO S I FOR ATIO looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses: I2R losses = IOUT2(RSW + RL) 4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional efficiency degradations in portable systems. It is very important to include these “system” level losses in the design of a system. The internal battery and fuse resistance losses can be minimized by making sure that CIN has adequate charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In a majority of applications, the LTC3561 does not dissipate much heat due to its high efficiency. However, in applications where the LTC3561 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3561 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TRISE = PD • θJA where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TRISE + TAMBIENT As an example, consider the case when the LTC3561 is in dropout at an input voltage of 3.3V with a load current of 1A. From the Typical Performance Characteristics graph of Switch Resistance, the RDS(ON) resistance of the P-channel switch is 0.11Ω. Therefore, power dissipated by the part is: PD = I2 • RDS(ON) = 110mW The DD8 package junction-to-ambient thermal resistance, θJA, will be in the range of about 43°C/W. Therefore, the junction temperature of the regulator operating in a 70°C ambient temperature is approximately: TJ = 0.11 • 43 + 70 = 74.7°C Remembering that the above junction temperature is obtained from an RDS(ON) at 25°C, we might recalculate the junction temperature based on a higher RDS(ON) since it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125°C. Design Example As a design example, consider using the LTC3561 in a portable application with a Li-Ion battery (refer to Figure 4 for reference designation). The battery provides a VIN = 2.5V to 4.2V. The load requires a maximum of 1A in active mode and 10mA in standby mode. The output voltage is VOUT = 2.5V. First, calculate the timing resistor: RT = 9.78 • 1011(1MHz ) −1.08 = 323.8k Use a standard value of 324k. Next, calculate the inductor value for about 40% ripple current at maximum VIN: L= 2.5V ⎛ 2.5V ⎞ • ⎜ 1− = 2.5µH 1MHz • 400mA ⎝ 4.2V ⎟⎠ Choosing the closest inductor from a vendor of 2.2µH, results in a maximum ripple current of: ∆IL = 2.5V ⎛ 2.5V ⎞ • ⎜ 1− ⎟ = 460mA 1MHz • 2.2µ ⎝ 4.2V ⎠ 3561f 11 LTC3561 U U W U APPLICATIO S I FOR ATIO For cost reasons, a ceramic capacitor will be used. COUT selection is then based on load step droop instead of ESR requirements. For a 5% output droop: C OUT ≈ 2.5 1A = 20µF 1MHz • (5%• 2.5V) The closest standard value is 22µF. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10µF. In noisy environments, decoupling SVIN from PVIN with an R6/C8 filter of 1Ω/0.1µF may help, but is typically not needed. The output voltage can now be programmed by choosing the values of R1 and R2. To maintain high efficiency, the current in these resistors should be kept small. Choosing 2µA with the 0.8V feedback voltage makes R1~400k. A close standard 1% resistor is 412k and R2 is then 887k. The compensation should be optimized for these components by examining the load step response but a good place to start for the LTC3561 is with a 13kΩ and 1000pF filter. The output capacitor may need to be increased depending on the actual undershoot during a load step. The circuit in Figure 6 shows the complete schematic for this design example. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3561. These items are also illustrated graphically in the layout diagram of Figure 5. Check the following in your layout: 1. Does the capacitor CIN connect to the power VIN (Pin 5) and power GND (Pin 4) as close as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers. 2. Are the COUT and L1 closely connected? The (–) plate of COUT returns current to PGND and the (–) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground line terminated near SGND (Pin 2). The feedback signal VFB should be routed away from noisy components and traces, such as the SW line (Pin 3), and its trace should be minimized. 4. Keep sensitive components away from the SW pin. The input capacitor CIN, the compensation capacitor CC and CITH and all the resistors R1, R2, RT, and RC should be routed away from the SW trace and the inductor L1. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the SGND pin at one point which is then connected to the PGND pin. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to one of the input supplies: PVIN, PGND, SVIN or SGND. CIN VIN COUT PGND PVIN L1 SVIN C4 R2 R1 LTC3561 SW VFB SGND ITH SHDN/RT R3 VOUT RT C3 3561 F06 BOLD LINES INDICATE HIGH CURRENT PATHS Figure 5. LTC3561 Layout Diagram (See Board Layout Checklist) 3561f 12 LTC3561 U TYPICAL APPLICATIO S Efficiency vs Load Current C1 10µF L1 2.2µH PVIN SW SVIN R2 887K LTC3561 ITH VFB 3.3V 2.5V 1.8V PGND C4 22pF R3 13k R4 324k C3 1000pF 90 80 SHDN/RT SGND 100 VOUT 1.8V/2.5V/3.3V AT 1A R1A 280k R1B 412k EFFICIENCY (%) VIN 2.63V TO 5.5V C2 22µF R1C 698k 70 60 50 40 30 20 VIN = 3.3V VOUT = 2.5V fO = 1MHz 10 NOTE: IN DROPOUT, THE OUTPUT TRACKS THE INPUT VOLTAGE C1, C2: TAIYO YUDEN JMK325BJ226MM L1: TOKO A914BYW-2R2M (D52LC SERIES) 3561 F07a 0 1 10 100 LOAD CURRENT (mA) 3561 F07b Figure 6. General Purpose Buck Regulator Using Ceramic Capacitors Efficiency and VOUT Ripple Small Footprint Buck C1 10µF VIN 2.63V TO 5.5V 100 LTC3561 VFB SGND ITH SHDN/RT R3 10k L1 2.2µH D1 C4 22pF R2 100k R1 200k R4 324k C3 470pF C2 22µF 1.2V AT 1.0A EFFICIENCY (%) SW 50 80 40 70 30 EFFICIENCY 60 20 50 10 VOUT RIPPLE 40 1 10 100 VOUT RIPPLE (mV) PGND SVIN 60 VIN = 3.3V VOUT = 1.2V 90 PVIN 1000 0 1000 ILOAD (mA) 3561 TA02 3561 TA03 C1: AVX 06034D106M C2: AVX 08054D226M L1: SUMIDA CDRH2D18/HP-2R2 3561f 13 LTC3561 U TYPICAL APPLICATIO S All Ceramic 2-Cell to 3.3V and 1.8V Converters VIN = 2V TO 3V L1 4.7µH D1 VOUT 3.3V 120mA/1A C5 10µF LTC3402 VIN +2 CELLS SHDN 1M VOUT PVIN SVIN MODE/SYNC FB PGOOD C1 10µF SW ITH 604k VC C2 44µF (2 × 22µF) 1000pF RT 49.9k 0 = FIXED FREQ 1 = Burst Mode OPERATION GND 10pF 887k SGND PGND 324k 1000pF C1: TAIYO YUDEN JMK212BJ106MG C2: TAIYO YUDEN JMK325BJ226MM C5, C6: TAIYO YUDEN JMK325BJ226MM SW L2 2.2µH VFB SHDN/RT 13k 47k LTC3561 D1: ON SEMICONDUCTOR MBRM120LT3 L1: TOKO A916CY-4R7M L2: TOKO A914BYW-2R2M (D52LC SERIES) VOUT 1.8V/1A C6 22µF 10pF 412k 3561 TA06 Efficiency and VOUT Ripple 100 VIN = 2.4V 3.3V EFFICIENCY (%) 90 1.8V 80 70 60 50 40 1 10 100 1000 ILOAD (mA) 3561 TA07 3561f 14 LTC3561 U PACKAGE DESCRIPTIO DD Package 8-Lead Plastic DFN (3mm × 3mm) (Reference LTC DWG # 05-08-1698) R = 0.115 TYP 5 0.38 ± 0.10 8 0.675 ±0.05 3.5 ±0.05 1.65 ±0.05 2.15 ±0.05 (2 SIDES) 3.00 ±0.10 (4 SIDES) PACKAGE OUTLINE 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) (DD8) DFN 1203 0.25 ± 0.05 0.200 REF 0.50 BSC 2.38 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 ±0.05 0.00 – 0.05 4 0.25 ± 0.05 1 0.50 BSC 2.38 ±0.10 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 3561f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3561 U TYPICAL APPLICATIO Efficiency vs Load Current 1mm Height, 2MHz, Li-Ion to 1.8V Converter 100 PVIN SW C1 10µF LTC3561 ITH R3 10k C7 47pF L1 1µH SVIN SGND PGND C4 10pF VOUT 1.8V AT 1A C2 2 x 10µF VFB R1 200k SHDN/RT R2 294k 80 3.6V 70 2.7V 60 4.2V R4 154k C3 1000pF VOUT = 1.8V 90 EFFICIENCY (%) VIN 2.63V TO 4.2V 50 3561 TA04 40 1 C1, C2: AVX 08056D106M L1: TDK VLF3010ATIR5NIRZ 10 100 1000 ILOAD (mA) 3561 TA05 RELATED PARTS PART NUMBER LTC1879 DESCRIPTION 1.2A (IOUT) 550kHz Synchronous Step-Down DC/DC Converter LTC3405/LTC3405A 300mA (IOUT) 1.5MHz Synchronous Step-Down DC/DC Converters LTC3406/LTC3406B 600mA (IOUT) 1.5MHz Synchronous Step-Down DC/DC Converters LTC3407 600mA (IOUT) 1.5MHz Dual Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 20µA, ISD: <1µA, ThinSOT 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 40µA, ISD: <1µA, 10-Lead MS or DFN LTC3407-2 800mA (IOUT) 2.25MHz, Dual Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ: 40µA, ISD: <1µA, 10-Lead MS or DFN LTC3410 300mA (IOUT) 2.25MHz Synchronous Step-Down DC/DC Converters 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 26µA, ISD: <1µA, 6-Lead SC70 LTC3411 1.25A (IOUT) 4MHz Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60µA, ISD: <1µA, 10-Lead MS or DFN LTC3412 2.5A (IOUT) 4MHz Synchronous Step-Down DC/DC Converter LTC3413 3A (IOUT Sink/Source) 2MHz Monolithic Synchronous Regulator for DDR/QDR Memory Termination 600mA (IOUT) 2MHz Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.8V, IQ: 60µA, ISD: <1µA, TSSOP16E 90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN): VREF/2, IQ: 280µA, ISD: <1µA, TSSOP16E 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 2.5V, IQ: 25µA, ISD: <1µA, 10-Lead MS LTC3440 COMMENTS 95% Efficiency, VIN: 2.7V to 10V, VOUT(MIN): 0.8V, IQ: 15µA, ISD: <1µA, TSSOP16 95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN): 0.8V, IQ: 20µA, ISD: <1µA, ThinSOTTM ThinSOT is a trademark of Linear Technology Corporation. 3561f 16 Linear Technology Corporation LT 0406 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006