LTC3772 Micropower No RSENSE Constant Frequency Step-Down DC/DC Controller U FEATURES DESCRIPTIO ■ The LTC®3772 is a constant frequency current mode step-down DC/DC controller in a low profile 8-lead SOT-23 (ThinSOTTM) and a 3mm × 2mm DFN package. The No RSENSETM architecture eliminates the need for a current sense resistor, improving efficiency and saving board space. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ No Current Sense Resistor Required 40µA No-Load Quiescent Current High Output Currents Easily Achieved Internal Soft-Start Ramps VOUT Wide VIN Range: 2.75V to 9.8V Low Dropout: 100% Duty Cycle Constant Frequency 550kHz Operation Low Ripple Burst Mode® Operation at Light Load Output Voltage as Low as 0.8V ±1.5% Voltage Reference Accuracy Current Mode Operation for Excellent Line and Load Transient Response Only 8µA Supply Current in Shutdown Low Profile 8-Lead SOT-23 (1mm) and (3mm × 2mm) DFN (0.75mm) Packages The LTC3772 automatically switches into Burst Mode operation at light loads to increase efficiency at low output current. It consumes only 40µA of quiescent current under a no-load condition. The LTC3772 incorporates an undervoltage lockout feature that shuts down the device when the input voltage falls below 2V. To maximize the runtime from a battery source, the external P-channel MOSFET is turned on continuously in dropout (100% duty cycle). High switching frequency of 550kHz allows the use of a small inductor and capacitors. An internal soft-start smoothly ramps the output voltage from zero to its regulation point. U APPLICATIO S ■ ■ ■ 1- or 2-Cell Li-Ion Battery-Powered Applications Wireless Devices Portable Computers Distributed Power Systems , LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT and No RSENSE are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. U ■ TYPICAL APPLICATIO Efficiency and Power Loss vs Load Current 550kHz Micropower Step-Down DC/DC Converter 10 100 20k LTC3772 3.3µH SW 47µF 22pF VIN = 5V 10µF PGATE 82.5k VFB 90 VOUT 2.5V 2A 1 80 0.1 70 VIN = 5V VIN = 3.3V 60 174k POWER LOSS (W) GND VIN = 3.3V VIN 2.75V TO 9.8V VIN ITH/RUN EFFICIENCY (%) 680pF 0.01 3772 TA01 50 FIGURE 5 CIRCUIT 40 1 100 1000 10 LOAD CURRENT (mA) 0.001 10000 3772 TA01b 3772f 1 LTC3772 U W W W ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN)........................ – 0.3V to 10V IPRG, PGATE Voltages ................ – 0.3V to (VIN + 0.3V) VFB, ITH/RUN Voltages ............................. – 0.3V to 2.4V SW Voltage ........... – 2V to (VIN + 1V) or 10V Maximum PGATE Peak Output Current (<10µs) ........................ 1A Operating Temperature Range (Note 2) .. – 40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................. – 65°C to 125°C Lead Temperature (Soldering, 10 sec) TSOT-23 ........................................................... 300°C W U U PACKAGE/ORDER INFORMATION ORDER PART NUMBER TOP VIEW GND 1 8 PGATE VFB 2 7 VIN 6 SW 5 NC ITH/RUN 3 9 IPRG 4 DDB PACKAGE 8-LEAD (3mm × 2mm) PLASTIC DFN TJMAX = 125°C, θJA = 76°C/W EXPOSED PAD (PIN 9) IS GND MUST BE SOLDERED TO PCB ORDER PART NUMBER TOP VIEW LTC3772EDDB DDB8 PART MARKING IPRG 1 ITH/RUN 2 VFB 3 GND 4 LBNR LTC3772ETS8 8 NC 7 SW 6 VIN 5 PGATE TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TS8 PART MARKING LTBNQ TJMAX = 125°C, θJA = 230°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted. (Note 2) PARAMETER CONDITIONS Input DC Supply Current Normal Operation SLEEP Mode Shutdown UVLO MIN ● Input Voltage Range (Note 4) VITH/RUN = 1.3V VITH/RUN = 0V VIN < UVLO Threshold – 100mV Undervoltage Lockout (UVLO) Threshold VIN Rising VIN Falling Start-Up Current Source VITH/RUN = 0V Shutdown Threshold (at ITH/RUN) VITH/RUN Rising Regulated Feedback Voltage 0°C ≤ TA ≤ 85°C (Note 5) –40°C ≤ TA ≤ 85°C (Note 5) TYP MAX UNITS 9.8 V 250 40 8 1 375 60 20 5 µA µA µA µA 2.0 1.85 2.75 2.60 V V 1.2 1.7 µA 2.75 ● ● 0.7 ● 0.3 0.6 0.95 V ● 0.788 0.780 0.800 0.800 0.812 0.812 V V 0.2 Feedback Voltage Line Regulation 2.75V ≤ VIN ≤ 9.8V (Note 5) 0.08 Feedback Voltage Load Regulation ITH/RUN = 1.6V (Note 5) ITH/RUN = 1V (Note 5) 0.2 –0.2 mV/V % % 3772f 2 LTC3772 ELECTRICAL CHARACTERISTICS The ● indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise noted. (Note 2) PARAMETER CONDITIONS VFB Input Current (Note 5) Overvoltage Protect Threshold Measured at VFB MIN TYP MAX UNITS –10 2 10 nA 0.850 0.880 0.910 V Overvoltage Protect Hysteresis 40 Oscillator Frequency Normal Operation Output Short Circuit VFB = 0.8V VFB = 0V Gate Drive Rise Time CLOAD = 3000pF Gate Drive Fall Time CLOAD = 3000pF Peak Current Sense Voltage IPRG = GND (Note 6) IPRG = Floating IPRG = VIN 500 550 200 mV 650 kHz kHz 40 ns 40 ● ● ● 90 160 228 105 175 245 Default Soft-Start Time ns 120 190 262 mV mV mV 0.6 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3772ETS8/LTC3772EDDB are guaranteed to meet specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD • θJA°C/W) ms Note 4: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 5: The LTC3772 are tested in a feedback loop that servos VFB to the output of the error amplifier while maintaining ITH/RUN at the midpoint of the current limit range. Note 6: Peak current sense voltage is reduced dependent on duty cycle as given in Figure 1. U W TYPICAL PERFOR A CE CHARACTERISTICS Quiescent Current (No Load) vs Temperature 55 55 50 50 45 40 35 30 25 45 40 35 30 25 25 20 Quiescent Current (Shutdown) vs Input Voltage QUIESCENT CURRENT (µA) 60 QUIESCENT CURRENT (µA) QUIESCENT CURRENT (µA) Quiescent Current (No Load) vs Input Voltage 2 3 4 6 7 5 8 INPUT VOLTAGE (V) 9 10 3772 G01 20 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 100 3772 G02 20 15 10 5 0 2 3 4 6 5 7 8 INPUT VOLTAGE (V) 9 10 3772 G03 3772f 3 LTC3772 U W TYPICAL PERFOR A CE CHARACTERISTICS Quiescent Current (Shutdown) vs Temperature Shutdown Threshold vs Temperature 14 800 Regulated Feedback Voltage vs Temperature 812 VIN = 4.2V VIN = 4.2V 808 700 8 6 4 804 VFB (mV) 10 VITH/RUN (mV) QUIESCENT CURRENT (µA) 12 600 796 500 792 2 0 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 400 –50 100 80 50 –10 10 30 TEMPERATURE (°C) –30 70 3772 G04 788 –50 –30 90 30 50 –10 10 TEMPERATURE (°C) 3772 G05 Regulated Feedback Voltage vs Input Voltage 600 0.808 90 Oscillator Frequency vs Input Voltage 560 VIN = 4.2V 590 80 3772 G06 Oscillator Frequency vs Temperature 0.812 580 TA = 25°C 555 570 0.800 0.796 560 fOSC (kHz) 0.804 fOSC (kHz) FEEDBACK VOLTAGE (V) 800 550 540 530 550 545 520 0.792 510 0.788 2 3 4 8 7 6 5 INPUT VOLTAGE (V) 500 –50 10 9 540 –30 30 –10 10 50 TEMPERATURE (°C) 70 3772 G07 2.1 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 3772 FG10 7 6 VIN (V) 8 9 10 2.5 ITH/RUN = 0V 2.4 1.9 2.3 1.7 1.5 1.3 1.1 0.9 2.2 2.1 RISING 2.0 1.9 1.8 FALLING 1.7 0.7 0.5 100 5 Undervoltage Lockout Thresholds vs Temperature INPUT VOLTAGE (V) ITH/RUN = 0V 1.3 4 3772 G09 ITH/RUN Start-Up Current vs Input Voltage ITH/RUN PULL-UP CURRENT (µA) ITH/RUN PULL-UP CURRENT (µA) 1.4 3 3772 G08 ITH/RUN Start-Up Current vs Temperature 1.5 2 90 1.6 0 2 4 6 INPUT VOLTAGE (V) 8 10 3772 G11 1.5 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 3772 G12 3772f 4 LTC3772 U W TYPICAL PERFOR A CE CHARACTERISTICS Foldback Frequency vs Temperature Soft-Start Time vs Temperature 1000 300 IPRG = VIN IPRG = FLOAT 150 IPRG = GND 100 210 800 700 600 0 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 80 190 180 160 400 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 100 200 170 500 50 VFB = 0V 220 FREQUENCY (Hz) 200 230 900 SOFT-START TIME (µs) 250 80 100 150 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) 3772 G14 3772 G13 Efficiency vs Load Current 80 100 3772 G15 Efficiency vs Load Current 95 100 FIGURE 5 CIRCUIT VIN = 3.3V VOUT = 3.3V 90 VIN = 4.2V 90 85 VIN = 5V EFFICIENCY (%) EFFICIENCY (%) MAXIMUM CURRENT SENSE THRESHOLD (mV) Maximum Current Sense Threshold vs Temperature VIN = 7V 80 75 VOUT = 2.5V 80 VOUT = 1.8V 70 70 60 65 VOUT = 2.5V FIGURE 5 CIRCUIT 60 1 10 100 1000 LOAD CURRENT (mA) 50 10000 1 10 100 1000 LOAD CURRENT (mA) 3772 G16 3772 G17 Start-Up Load Step VOUT 1V/DIV VOUT 100mV/DIV AC COUPLED ITH/RUN 1V/DIV IL 2A/DIV IL 2A/DIV ILOAD 2A/DIV VIN = 5V 500µs/DIV VOUT = 2.5V FIGURE 5 CIRCUIT 10000 3772 G18 20µs/DIV VIN = 5V VOUT = 2.5V ILOAD = 100mA TO 1.5A FIGURE 5 CIRCUIT 3772 G19 3772f 5 LTC3772 U U U PI FU CTIO S (DDB/TS8) GND (Pin 1/Pin 4): Ground Pin. NC (Pin 5/Pin 8): No Connection Required. VFB (Pin 2/Pin 3): Receives the feedback voltage from an external resistor divider across the output. SW (Pin 6/Pin 7): Switch Node Connection to Inductor and Current Sense Input Pin. Normally, the external P-channel MOSFET’s drain is connected to this pin. ITH/RUN (Pin 3/Pin 2): This pin performs two functions. It serves as the error amplifier compensation point as well as the run control input. Nominal voltage range for this pin is 0.7V to 1.9V. Forcing this pin below 0.6V causes the device to be shut down. In shutdown, all functions are disabled and the PGATE pin is held high. IPRG (Pin 4/Pin 1): Current Sense Limit Pin. Three-state pin selects maximum peak sense voltage threshold. The pin selects the maximum voltage drop across the external P-channel MOSFET. Tie to VIN, GND or float to select 245mV, 105mV or 175mV respectively. VIN (Pin 7/Pin 6): Supply and Current Sense Input Pin. This pin must be closely decoupled to GND (Pin 4). Normally the external P-channel MOSFET’s source is connected to this pin. PGATE (Pin 8/Pin 5): Gate Drive for the External P-Channel MOSFET. This pin swings from 0V to VIN. Exposed Pad (Pin 9, DDB Only): The Exposed Pad is ground and must be soldered to the PCB for electrical connection and optimum thermal performance. 3772f 6 LTC3772 W FU CTIO AL DIAGRA U U SW VIN UNDERVOLTAGE LOCKOUT UV VOLTAGE REFERENCE BURST CLAMP 0.8V SLOPE COMPENSATION – + IPRG 1µA – CURRENT COMPARATOR 75mV + + ILIM ITH BUFFER SHDN – 550kHz OSCILLATOR RS R S LATCH Q – VIN SLEEP COMPARATOR SWITCHING LOGIC AND BLANKING CIRCUIT SLEEP + FREQUENCY FOLDBACK PGATE 0V OVERVOLTAGE COMPARATOR 0.15V 0.225V + 1.2V SHORT-CIRCUIT DETECT – ERROR AMPLIFIER + 0.88V – ITH/RUN SHUTDOWN COMPARATOR + 0.3V – VFB 0.8V SOFT-START RAMP GND 3772 FD 3772f 7 LTC3772 U OPERATIO (Refer to the Functional Diagram) Main Control Loop (Normal Operation) The LTC3772 is a constant frequency current mode stepdown switching regulator controller. During normal operation, the external P-channel MOSFET is turned on each cycle when the oscillator sets the RS latch and turned off when the current comparator resets the latch. The peak inductor current at which the current comparator trips is controlled by the voltage on the ITH/RUN pin, which is the output of the error amplifier. The negative input to the error amplifier is the output feedback voltage VFB, which is generated by an external resistor divider connected between VOUT and ground. When the load current increases, it causes a slight decrease in VFB relative to the 0.8V reference, which in turn causes the ITH/RUN voltage to increase until the average inductor current matches the new load current. The main control loop is shut down by pulling the ITH/RUN pin to ground. Releasing the ITH/RUN pin allows an internal 1µA current source to charge up the external compensation network. When the ITH/RUN pin voltage reaches approximately 0.6V, the main control loop is enabled and the ITH/RUN voltage is pulled up by a clamp to its zero current level of approximately one diode voltage drop (0.7V). As the external compensation network continues to charge up, the corresponding peak inductor current level follows, allowing normal operation. The maximum peak inductor current attainable is set by a clamp on the ITH/RUN pin at 1.2V above the zero current level (approximately 1.9V). Burst Mode Operation The LTC3772 incorporates Burst Mode operation at low load currents (<10% of IMAX). In this mode, an internal clamp sets the peak current of the inductor at a level corresponding to an ITH/RUN voltage 0.925V, even though the actual ITH/RUN voltage is lower. When the inductor’s average current is greater than the load requirement, the voltage at the ITH/RUN pin will drop. When the ITH/RUN voltage falls to 0.85V, the sleep comparator will trip, turning off the external MOSFET. In sleep, the input DC supply current to the IC is reduced to 40µA from 250µA in normal operation. With the switch held off, average inductor current will decay to zero and the load will eventually cause the error amplifier output to start drifting higher. When the error amplifier output rises to 0.87V, the sleep comparator will untrip and normal operation will resume. The next oscillator cycle will turn the external MOSFET on and the switching cycle will repeat. Dropout Operation When the input supply voltage decreases towards the output voltage, the rate of change of inductor current during the on cycle decreases. This reduction means that at some input-output differential, the external P-channel MOSFET will remain on for more than one oscillator cycle (start dropping off-cycles) since the inductor current has not ramped up to the threshold set by the error amplifier. Further reduction in input supply voltage will eventually cause the external P-channel MOSFET to be turned on 100%; i.e., DC. The output voltage will then be determined by the input voltage minus the voltage drop across the sense resistor, the MOSFET and the inductor. Undervoltage Lockout Protection To prevent operation of the external P-channel MOSFET with insufficient gate drive, an undervoltage lockout circuit is incorporated into the LTC3772. When the input supply voltage drops below approximately 2V, the P-channel MOSFET and all internal circuitry other than the undervoltage block itself are turned off. Input supply current in undervoltage is approximately 1µA. Short-Circuit Protection If the output is shorted to ground, the frequency of the oscillator is folded back from 550kHz to approximately 200kHz while maintaining the same minimum on time. This lower frequency allows the inductor current to safely discharge, thereby preventing current runaway. After the short is removed, the oscillator frequency will gradually increase back to 550kHz as VFB rises through 0.3V on its way back to 0.8V. 3772f 8 LTC3772 U OPERATIO (Refer to the Functional Diagram) Overvoltage Protection If VFB exceeds its regulation point of 0.8V by more than 10% for any reason, such as an output short-circuit to a higher voltage, the overvoltage comparator will hold the external P-channel MOSFET off. This comparator has a typical hysteresis of 40mV. Peak Current Sense Voltage Selection and Slope Compensation (IPRG Pins) When a controller is operating below 20% duty cycle, the peak current sense voltage (between the SENSE+ and SW pins) allowed across the external P-channel MOSFET is determined by: ∆VSENSE(MAX) = A( VITH – 0.7 V) – 0.015 10 where A is a constant determined by the state of the IPRG pins. Floating the IPRG pin selects A = 1.58; tying IPRG to VIN selects A = 2.2; tying IPRG to SGND selects A = 0.97. The maximum value of VITH is typically about 1.98V, so the maximum sense voltage allowed across the external P-channel MOSFET is 175mV, 100mV or 250mV for the three respective states of the IPRG pin. However, once the controller’s duty cycle exceeds 20%, slope compensation begins and effectively reduces the peak sense voltage by a scale factor given by the curve in Figure 1. The peak inductor current is determined by the peak sense voltage and the on-resistance of the external P-channel MOSFET: IPEAK = ∆VSENSE(MAX) RDS(ON) Soft-Start The start-up of VOUT is controlled by the LTC3772 internal soft-start. During soft-start, the error amplifier EAMP compares the feedback signal VFB to the internal soft-start ramp (instead of the 0.8V reference), which rises linearly from 0V to 0.8V in about 0.6ms. This allows the output voltage to rise smoothly from 0V to its final value, while maintaining control of the inductor current. After the soft-start is timed out, it is disabled until the part is put in shutdown again or the input supply is cycled. SF = REDUCTION IN SENSE VOLTAGE (mV) 100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100 DUTY CYCLE (%) 3772 F01 Figure 1. Reduction in Sense Voltage Due to Slope Compensation vs Duty Cycle 3772f 9 LTC3772 U W U U APPLICATIO S I FOR ATIO The basic LTC3772 application circuit is shown on the front page of this data sheet. External component selection is driven by the load requirement and begins with the selection of the power MOSFET inductor and the output diode. These are selected followed by the input bypass capacitor CIN and output bypass capacitor COUT. However, for operation above 20% duty cycle, slope compensation has to be taken into consideration to select the appropriate value of RDS(ON) to provide the required amount of load current: RDS(ON)(MAX) = Power MOSFET Selection Since the LTC3772 is designed for operation down to low input voltages, a sublogic level threshold MOSFET (RDS(ON) guaranteed at VGS = 2.5V) is required for applications that work close to this voltage. When these MOSFETs are used, make sure that the input supply to the LTC3772 is less than the absolute maximum VGS rating. The P-channel MOSFET’s on-resistance is chosen based on the required load current. The maximum average output load current IOUT(MAX) is equal to the peak inductor current minus half the peak-to-peak ripple current IRIPPLE. The LTC3772’s current comparator monitors the drain-tosource voltage VDS of the P-channel MOSFET, which is sensed between the VIN and SW pins. The peak inductor current is limited by the current threshold, set by the voltage on the ITH pin of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ∆VSENSE(MAX) to approximately 175mV when IPRG is floating (100mV when IPRG is tied low; 250mV when IPRG is tied high). The output current that the LTC3772 can provide is given by: IOUT (MAX) = ∆VSENSE(MAX) IRIPPLE – RDS(ON) 2 A reasonable starting point is setting ripple current IRIPPLE to be 40% of IOUT(MAX). Rearranging the above equation yields: RDS(ON)(MAX) 5 ∆V = • SENSE(MAX) 6 IOUT (MAX) for Duty Cycle < 20%. where SF is a factor whose value is obtained from the curve in Figure 1. These must be further derated to take into account the significant variation in on-resistance with temperature. The following equation is a good guide for determining the required RDS(ON)MAX at 25°C (manufacturer’s specification), allowing some margin for variations in the LTC3772 and external component values: RDS(ON)(MAX) = ∆VSENSE(MAX) – SF 5 • 0.9 • 6 IOUT(MAX) • ρT The ρT is a normalizing term accounting for the temperature variation in on-resistance, which is typically about 0.4%/°C, as shown in Figure 2. Junction to case temperature TJC is about 10°C in most applications. For a maximum ambient temperature of 70°C, using ρ80°C ~ 1.3 in the above equation is a reasonable choice. The required minimum RDS(ON) of the MOSFET is also governed by its allowable power dissipation. For applications that may operate the LTC3772 in dropout–i.e., 100% 2.0 ρT NORMALIZED ON RESISTANCE An external P-channel power MOSFET must be selected for use with the LTC3772. The main selection criteria for the power MOSFET are the threshold voltage VGS(TH) and the “on” resistance RDS(ON), reverse transfer capacitance CRSS and total gate charge. 5 ∆VSENSE(MAX) – SF • 6 IOUT(MAX) 1.5 1.0 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (ϒC) 150 3772 F02 Figure 2. RDS(ON) vs Temperature 3772f 10 LTC3772 U W U U APPLICATIO S I FOR ATIO duty cycle–at its worst case the required RDS(ON) is given by: PP RDS(ON)(DC =100%) = (IOUT (MAX) )2 (1 + δP ) where PP is the allowable power dissipation and δP is the temperature dependency of RDS(ON). (1 + δP) is generally given for a MOSFET in the form of a normalized RDS(ON) vs temperature curve, but δP = 0.005/°C can be used as an approximation for low voltage MOSFETs. In applications where the maximum duty cycle is less than 100% and the LTC3772 is in continuous mode, the RDS(ON) is governed by: RDS(ON) ≅ PP (DC )IOUT 2 (1 + δP ) where DC is the maximum operating duty cycle of the LTC3772. Inductor Value Calculation The operating frequency and inductor selection are interrelated in that higher operating frequencies permit the use of a smaller inductor for the same amount of inductor ripple current. However, this is at the expense of efficiency due to an increase in MOSFET gate charge losses. The inductance value also has a direct effect on ripple current. The ripple current, IRIPPLE, decreases with higher inductance or frequency and increases with higher VIN or VOUT. The inductor’s peak-to-peak ripple current is given by: IRIPPLE = VIN − VOUT ⎛ VOUT + VD ⎞ ⎜ ⎟ f(L) ⎝ VIN + VD ⎠ where f is the operating frequency. Accepting larger values of IRIPPLE allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is IRIPPLE = 0.4(IOUT(MAX)). Remember, the maximum IRIPPLE occurs at the maximum input voltage. Inductor Core Selection Once the inductance value is determined, the type of inductor must be selected. Actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. As inductance increases, core losses go down. Unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. Ferrite core material saturates “hard,” which means that inductance collapses abruptly when the peak design current is exceeded. This results in an abrupt increase in inductor ripple current and consequent output voltage ripple. Do not allow the core to saturate! Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. The choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/EMI requirements. New designs for surface mount inductors are available from Coiltronics, Coilcraft, Toko and Sumida. Output Diode Selection The catch diode carries load current during the off-time. The average diode current is therefore dependent on the P-channel switch duty cycle. At high input voltages the diode conducts most of the time. As VIN approaches VOUT the diode conducts only a small fraction of the time. The most stressful condition for the diode is when the output is shortcircuited. Under this condition the diode must safely handle IPEAK at close to 100% duty cycle. Therefore, it is important to adequately specify the diode peak current and average power dissipation so as not to exceed the diode ratings. 3772f 11 LTC3772 U W U U APPLICATIO S I FOR ATIO Under normal load conditions, the average current conducted by the diode is: ⎛V −V ⎞ ID = ⎜ IN OUT ⎟ IOUT ⎝ VIN + VD ⎠ The allowable forward voltage drop in the diode is calculated from the maximum short-circuit current as: VF ≈ PD The output ripple, ∆VOUT, is determined by: ⎛ 1 ⎞ ∆VOUT ≤ ∆IL ⎜ ESR + ⎟ ⎝ 8fC OUT ⎠ ISC(MAX) where PD is the allowable power dissipation and will be determined by efficiency and/or thermal requirements. A fast switching diode must also be used to optimize efficiency. Schottky diodes are a good choice for low forward drop and fast switching times. Remember to keep lead length short and observe proper grounding to avoid ringing and increased dissipation. An additional consideration in applications where low noload quiescent current is critical is the reverse leakage current of the diode at the regulated output voltage. A leakage greater than several microamperes can represent a significant percentage of the total input current. CIN and COUT Selection The input capacitance, CIN, is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor sized for the maximum RMS current should be used. RMS current is given by: IRMS = IOUT (MAX) The output filtering capacitor C smooths out current flow from the inductor to the load, help maintain a steady output voltage during transient load changes and reduce output voltage ripple. The capacitors must be selected with sufficiently low ESR to minimize voltage ripple and load step transients and sufficiently bulk capacitance to ensure the control loop stability. VOUT VIN VIN –1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The output ripple is highest at maximum input voltage since DIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. However, care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. 3772f 12 LTC3772 U W U U APPLICATIO S I FOR ATIO For ceramic capacitor, use X7R or X5R types, do not use Y5V. The choices include Murata GRM series, TDK C2012 and Taiyo-Yuden JMK series. Setting Output Voltage The LTC3772 output voltages are each set by an external feedback resistor divider carefully placed across the output as shown in Figure 3. The regulated output voltage is determined by: ⎛ R ⎞ VOUT = 0.8 V • ⎜ 1 + B ⎟ ⎝ RA ⎠ To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. VOUT LTC3772 VFB RB CFF 3 RA 3772 F03 Figure 3. Setting Output Voltage Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (η1 + η2 + η3 + ...) where η1, η2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3772 circuits: 1) LTC3772 DC bias current, 2) MOSFET gate charge current, 3) I2R losses and 4) voltage drop of the output diode. 1. The VIN current is the DC supply current, given in the electrical characteristics, that excludes MOSFET driver and control currents. VIN current results in a small loss which increases with VIN. 2. MOSFET gate charge current results from switching the gate capacitance of the power MOSFET. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from VIN to ground. The resulting dQ/dt is a current out of VIN that is typically much larger than the DC supply current. In continuous mode, IGATECHG = (f)(dQ). 3. I2R losses are predicted from the DC resistances of the MOSFET, inductor and current shunt. In continuous mode the average output current flows through L but is “chopped” between the P-channel MOSFET (in series with RSENSE) and the output diode. The MOSFET RDS(ON) plus RSENSE multiplied by duty cycle can be summed with the resistances of L and RSENSE to obtain I2R losses. 4. The output diode is a major source of power loss at high currents and gets worse at high input voltages. The diode loss is calculated by multiplying the forward voltage times the diode duty cycle multiplied by the load current. For example, assuming a duty cycle of 50% with a Schottky diode forward voltage drop of 0.4V, the loss increases from 0.5% to 8% as the load current increases from 0.5A to 2A. 5. Transition losses apply to the external MOSFET and increase at higher operating frequencies and input voltages. Transition losses can be estimated from: Transition Loss = 2(VIN)2IO(MAX)CRSS(f) Other losses including CIN and COUT ESR dissipative losses, and inductor core losses, generally account for less than 2% total additional loss. Foldback Current Limiting As described in the Output Diode Selection, the worst-case dissipation occurs with a short-circuited output when the diode conducts the current limit value almost continuously. 3772f 13 LTC3772 U W U U APPLICATIO S I FOR ATIO To prevent excessive heating in the diode, foldback current limiting can be added to reduce the current in proportion to the severity of the fault. Foldback current limiting is implemented by adding diodes DFB1 and DFB2 between the output and the ITH/RUN pin as shown in Figure 4. In a hard short (VOUT = 0V), the current will be reduced to approximately 50% of the maximum output current. VOUT LTC3772 RB ITH /RUN VFB DFB1 RA DFB2 3772 F04 Figure 4. Foldback Current Limiting Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD)(ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then returns VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing. OPTI-LOOP compensation allows the transient response to be optimized over a wide range of output capacitance and ESR values. The ITH series RC-CC filter (see Functional Diagram) sets the dominant pole-zero loop compensation. The ITH external components shown in the Figure 5 circuit will provide an adequate starting point for most applications. The values can be modified slightly (from 0.2 to 5 times their suggested values) to optimize transient response once the final PC layout is done and the particular output capacitor type and value have been determined. The output capacitors need to be decided upon because the various types and values determine the loop feedback factor gain and phase. An output current pulse of 20% to 100% of full load current having a rise time of 1µs to 10µs will produce output voltage and ITH pin waveforms that will give a sense of the overall loop stability. The gain of the loop will be increased by increasing RC, and the bandwidth of the loop will be increased by decreasing CC. The output voltage settling behavior is related to the stability of the closedloop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to Application Note 76. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25)(CLOAD). Thus a 10µF capacitor would require a 250µs rise time, limiting the charging current to about 200mA. Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time that the LTC3772 is capable of turning the top MOSFET on and then off. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET. The minimum on-time for the LTC3772 is about 250ns. Low duty cycle and high frequency applications may approach this minimum on-time limit and care should be taken to ensure that: tON(MIN) < VOUT f • VIN If the duty cycle falls below what can be accommodated by the minimum on-time, the LTC3772 will begin to skip cycles. The output voltage will continue to be regulated, but the ripple current and ripple voltage will increase. 3772f 14 LTC3772 U TYPICAL APPLICATIO S 550kHz Micropower, 1A, 2-Cell Li-Ion to 3.3VOUT Step-Down DC/DC Converter 100pF 15k VIN 5V TO 8.4V VIN ITH/RUN LTC3772 GND 22µF Si2341DS PGATE IPRG 56.2k L1 4.7µH VFB SW UPS120 22pF 47µF VOUT 3.3V 1A 174k 3772 TA02a L1: SUMIDA CR43-4R7 Efficiency vs Load Current 100 VIN = 5.5V VIN = 7.2V 90 EFFICIENCY (%) VOUT = 3.3V 80 VIN = 8.4V 70 60 50 40 1 100 1000 10 LOAD CURRENT (mA) 10000 3772 TA02b Start-Up Load Step VOUT 100mV/DIV AC COUPLED VOUT 2V/DIV ITH/RUN 1V/DIV IL 500mA/DIV IL 1A/DIV ILOAD 500mA/DIV VIN = 5.5V VOUT = 3.3V RLOAD = 3Ω 500µs/DIV 3772 TA02c VIN = 5.5V 20µs/DIV VOUT = 3.3V ILOAD = 40mA TO 500mA 3772 TA02d 3772f 15 LTC3772 U TYPICAL APPLICATIO S 550kHz Micropower 4A Step-Down DC/DC Converter 470pF 24.9k VIN 2.75V TO 9.8V VIN ITH/RUN LTC3772 GND 22µF PGATE IPRG 82.5k VFB NTMS5PO2R2 L1 2.2µH B320A 22pF VOUT 2.5V 4A SW 47µF 174k 3772 TA03a L1: VISHAY IHLP-2525CZ-01 Efficiency vs Load Current 100 95 VIN = 3.3V EFFICIENCY (%) 90 85 VIN = 5V 80 75 70 65 60 100 1000 LOAD CURRENT (mA) 10000 3772 TA03b Start-Up Load Step VOUT 2V/DIV VOUT 200mV/DIV AC COUPLED IL 2A/DIV ITH/RUN 1V/DIV ILOAD 2A/DIV IL 1A/DIV VIN = 5V VOUT = 2.5V RLOAD = 3Ω 500µs/DIV 3772 TA03c VIN = 5V VOUT = 2.5V 20µs/DIV 3772 TA03d 3772f 16 LTC3772 U TYPICAL APPLICATIO S 550kHz Micropower 5VIN to 1.8VOUT at 8A DC/DC Converter 470pF 15k VIN 5V VIN ITH/RUN LTC3772 GND 140k VIN PGATE IPRG VFB Si9803 ×2 L1 1µH 22µF SW 100µF ×2 22pF VOUT 1.8V 8A 174k 3772 TA04a 3772f 17 LTC3772 U PACKAGE DESCRIPTIO DDB Package 8-Lead Plastic DFN (3mm × 2mm) (Reference LTC DWG # 05-08-1702) 0.61 ±0.05 (2 SIDES) 0.675 ±0.05 2.50 ±0.05 1.15 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 2.20 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 0.56 ± 0.05 (2 SIDES) 3.00 ±0.10 (2 SIDES) PIN 1 BAR TOP MARK (SEE NOTE 6) 0.200 REF 0.38 ± 0.10 8 2.00 ±0.10 (2 SIDES) 0.75 ±0.05 0 – 0.05 4 0.25 ± 0.05 1 PIN 1 CHAMFER OF EXPOSED PAD (DDB8) DFN 1103 0.50 BSC 2.15 ±0.05 (2 SIDES) BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3772f 18 LTC3772 U PACKAGE DESCRIPTIO TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 0.52 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0802 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 3772f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3772 U TYPICAL APPLICATIO 680pF 20k VIN 3V TO 8V VIN ITH/RUN LTC3772 GND 10µF PGATE FDC638P IPRG 82.5k VFB L1 3.3µH B220A 22pF VOUT 2.5V 2A SW 47µF 174k 3772 F05 L1: TOKO D53LCA915AT-3R3M Figure 5. 550kHz Micropower Step-Down DC/DC Converter RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1624 High Efficiency SO-8 N-Channel Switching Regulator Controller N-Channel Drive, 3.5V ≤ VIN ≤ 36V TM LTC1625 No RSENSE Synchronous Step-Down Regulator 97% Efficiency, No Sense Resistor LT®1765 25V, 2.75A (IOUT), 1.25MHz Step-Down Converter 3V ≤ VIN ≤ 25V, VOUT ≥ 1.2V, SO-8 and TSSOP16 Packages LTC1771 Ultra-Low Supply Current Step-Down DC/DC Controller 10µA Supply Current, 93% Efficiency, 1.23V ≤ VOUT ≤ 18V; 2.8V ≤ VIN ≤ 20V LTC1772/LTC1772B 550kHz ThinSOT Step-Down DC/DC Controllers 2.5V ≤ VIN ≤ 9.8V, VOUT ≥ 0.8V, IOUT ≤ 6A LTC1778/LTC1778-1 No RSENSE Current Mode Synchronous Step-Down Controllers 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN), IOUT Up to 20A LTC1872/LTC1872B 550kHz ThinSOT Step-Up DC/DC Controllers 2.5V ≤ VIN ≤ 9.8V; 90% Efficiency LTC3411/LTC3412 1.25/2.5A Monolithic Synchronous Step-Down Converter 95% Efficiency, 2.5V ≤ VIN ≤ 5.5V, VOUT ≥ 0.8V, TSSOP16 Exposed Pad Package LTC3440 600mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter 2.5V ≤ VIN ≤ 5.5V, Single Inductor LTC3736 Dual, 2-Phase, No RSENSE Synchronous Controller with Output Tracking VIN: 2.75V to 9.8V, IOUT Up to 5A, 4mm × 4mm QFN Package LTC3736-1 Dual, 2-Phase, No RSENSE Synchronous Controller with Spread Spectrum VIN: 2.75V to 9.8V, Spread Spectrum Operation, Output Voltage Tracking, 4mm × 4mm QFN Package LTC3737 Dual, 2-Phase, No RSENSE Controller with Output Tracking VIN: 2.75V to 9.8V, IOUT Up to 5A, 4mm × 4mm QFN Package LTC3776 Dual, 2-Phase, No RSENSE Synchronous Controller for DDR/QDR Memory Termination Provides VDDQ and VTT with one IC, 2.75V ≤ VIN ≤ 9.8V, Adjustable Constant Frequency with PLL Up to 850kHz, Spread Spectrum Operation, 4mm × 4mm QFN and 16-Lead SSOP Packages LTC3808 No RSENSE, Low EMI, Synchronous Step-Down Controller with Output Tracking 2.75V ≤ VIN ≤ 9.8V, Spread Spectrum Operation, 3mm × 4mm DFN and 16-Lead SSOP Packages 3772f 20 Linear Technology Corporation LT/TP 0305 500 • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2005