LTC3543 600mA Synchronous Step Down Buck Regulator with PLL, Soft-Start and Spread Spectrum DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®3543 is a high efficiency monolithic synchronous current mode buck regulator. 600mA Output Current 2.5V to 5.5V Input Voltage Range 2.25MHz Constant Frequency Operation, Spread Spectrum or Synchronized PLL (1MHz to 3MHz) High Efficiency: Up to 95% 1A Peak Inductor Current Very Low Quiescent Current: Only 45µA During Burst Mode Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle Overtemperature Protected Stable with Ceramic Capacitors Shutdown Mode Draws <1µA Supply Current ±2% Output Voltage Accuracy Current Mode Operation for Excellent Line and Load Transient Response Soft-Start Available in a Low Profile (0.75mm) 2mm × 3mm 6-Lead DFN Package The switching frequency is internally set at 2.25MHz, allowing the use of small surface mount inductors and capacitors. In PLL mode, the LTC3543 can acquire frequencies between 1MHz and 3MHz. Also, the LTC3543 has spread spectrum capability providing a lower noise regulated output, as well as low noise at the input. In Burst Mode® 0peration, the supply current is only 45µA, dropping to <1µA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3543 ideally suited for single Li-Ion battery-powered applications. The 100% duty cycle provides a low dropout operation, extending the battery life in portable systems. Burst Mode operation increases efficiency at light loads, further extending battery life. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. U APPLICATIO S ■ ■ , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. Portable Instruments Cellular Phones U TYPICAL APPLICATIO Efficiency and Power Loss vs Load Current VIN 1.5V SW 10µF 300k LTC3543 1000 100 3.3µH 2.5V TO 5.5V 10pF VOUT 1.5V 90 10µF VIN = 2.7V 80 VFB MODE CAP GND 4nF 200k EFFICIENCY (%) MODE RUN 60 VIN = 3.6V 50 40 POWER LOSS AT VIN = 3.6V 30 EXPOSED PAD MODE = VIN → PULSE SKIP MODE = VFB → PULSE SKIP WITH SPREAD SPECTRUM MODE = GND → BURST MODE MODE = EXTERNAL CLOCK → PLL 3543 TA01 10 POWER LOSS (mW) PWR_EN 100 VIN = 4.2V 70 10 20 10 0 0.1 Burst Mode ENABLED 1 10 100 LOAD CURRENT (mA) 0.1 1000 3543 TA01b 3543f 1 LTC3543 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) VIN RUN VFB TOP VIEW VIN Voltage ................................................... –0.3V to 6V RUN, VFB, MODE, CAP Voltages...................–0.3V to VIN SW Voltage ....................................–0.3V to (VIN + 0.3V) Operating Temperature Range (Note 2) ... –40°C to 85°C Junction Temperature (Note 3) ............................. 125°C Storage Temperature Range................... –65°C to 125°C 6 5 4 1 2 3 SW CAP MODE 7 DCB PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN PIN 7 IS GND TJMAX = 125°C, θJA = 64°C/W ORDER PART NUMBER DCB PART MARKING LTC3543EDCB LCCK Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V unless otherwise noted. SYMBOL PARAMETER RUN Run Threshold VFB Regulated Feedback Voltage IVFB Feedback Pin Current IPK Peak Inductor Current VLOADREG Output Voltage Load Regulation VLINEREG Output Voltage Line Regulation VIN Input Voltage Range IS Input DC Bias Current Active Mode Sleep Mode Shutdown fOSC Nominal Oscillator Frequency RPFET RDS(ON) of P-Channel FET RNFET ISW CONDITIONS MIN ● (Note 4) VIN = 3.6V, VFB = 0V TYP MAX 0.3 1 1.5 V 0.588 0.6 0.612 V 1 µA 1.3 A 0.7 1 0.5 (Note 4) ● 2.5 (Note 5) VOUT = 90%, ILOAD = 0A VOUT = 103%, ILOAD = 0A VRUN = 0V, VIN = 5.5V 375 45 0.1 ● UNITS 0.5 %/V 5.5 V 500 70 1 µA µA µA 2.25 MHz ISW = 100mA 0.45 Ω RDS(ON) of N-Channel FET ISW = 100mA 0.35 Ω SW Leakage VRUN = 0V, VSW = 0V or 5.5V, VIN = 5.5V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3543E is guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature ranges are assured by design, characterization and correlation with statistical process controls. 1.80 %/mA ±1 µA Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD)(64°C/W) Note 4: The LTC3543 is tested in a proprietary test mode that connects VFB to the output of the error amplifier. This test mode is equivalent to continuous mode operation. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. 3543f 2 LTC3543 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Input Voltage (VIN) Efficiency vs Load Current 100 100 IOUT = 200mA Burst Mode ENABLED 90 90 Efficiency vs Load Current 100 VIN = 2.7V 80 70 IOUT = 10mA 60 VIN = 4.2V 70 50 60 50 VIN = 3.6V 40 2.5 3.5 4.0 4.5 INPUT VOLTAGE (V) 3.0 5.0 30 1 10 100 LOAD CURRENT (mA) 200 100 Burst Mode ENABLED 10 100 LOAD CURRENT (mA) 90 Burst Mode ENABLED 70 VIN = 4.2V 60 50 VIN = 3.6V 40 50 30 20 VIN = 2.7V 10 VOUT = 1.8V 1 VIN = 3.6V 40 20 VIN = 2.7V VIN = 4.2V 60 30 0 0.1 1000 10 100 LOAD CURRENT (mA) 3543 G04 0 0.1 1000 VOUT = 2.5V 1 10 100 LOAD CURRENT (mA) 3543 G05 Synchronous Switch Resistance vs Temperature 500 500 1000 3543 G06 Main Switch Resistance vs Temperature RDS(ON) vs Input Voltage (VIN) 1000 80 10 10 100 LOAD CURRENT (mA) 1 Efficiency vs Load Current 80 EFFICIENCY (%) POWER LOSS (mW) 90 300 VOUT = 1.5V 3543 G03 100 70 1 1000 Efficiency vs Load Current 100 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 0 0.1 0 0.1 3543 G02 Power Loss vs Load Current 400 VIN = 2.7V 10 VOUT = 1.2V 3543 G01 500 40 20 0 0.1 5.5 VIN = 3.6V 50 20 EFFICIENCY (%) 40 60 30 10 VOUT = 1.8V VIN = 4.2V 70 EFFICIENCY (%) IOUT = 600mA 80 Burst Mode ENABLED 90 80 EFFICIENCY (%) EFFICIENCY (%) TA = 25°C unless otherwise noted. (From Figure 1a) 500 450 450 RDS(ON) (mΩ) RDS(ON) (mΩ) MAIN SWITCH 350 300 250 SYNCHRONOUS SWITCH 200 150 400 450 VIN = 2.7V RDS(ON) (mΩ) 400 VIN = 3.6V 350 300 VIN = 4.2V VIN = 2.7V 400 VIN = 3.6V 350 300 VIN = 4.2V 100 250 250 200 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 200 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 50 0 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5 3543 G07 3543 G08 3543 G09 3543f 3 LTC3543 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted. Switching Frequency vs Temperature 2.8 2.40 2.7 2.35 2.6 2.5 2.4 2.3 2.2 2.1 2.0 VIN = 3.6V 1.54 2.30 2.25 2.20 2.15 1.8 2.00 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5 612 612 610 610 608 602 600 598 596 594 592 800 VIN = 3.6V 700 606 604 602 600 598 596 594 590 588 588 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 5.0 5.5 SUPPLY CURRENT (µA) PULSE SKIP MODE 200 100 300 200 3543 G15 Switch Leakage (ISW) vs Input Voltage (VIN) 400 1000 350 900 250 200 150 100 5.0 5.5 3543 G16 700 600 MAIN SWITCH 500 SYNCHRONOUS SWITCH 400 300 200 50 0 RUN = 0V 800 300 Burst Mode OPERATION 3.5 4.0 4.5 INPUT VOLTAGE (V) SYNCHRONOUS SWITCH 400 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) LEAKAGE CURRENT (pA) ILOAD = 0A VOUT = 1.5V 3.0 500 Dynamic Supply Current vs Temperature Dynamic Supply Current vs Input Voltage (VIN) 2.5 600 3543 G14 3543 G13 300 VIN = 5.5V RUN = 0V 100 590 4.5 4.0 3.5 INPUT VOLTAGE (V) 1000 MAIN SWITCH 592 3.0 600 800 400 OUTPUT VOLTAGE (V) Switch Leakage (ISW) vs Temperature LEAKAGE CURRENT (pA) FEEDBACK VOLTAGE (mV) 604 200 0 3543 G12 608 606 2.5 VIN = 4.2V 1.46 Feedback Voltage (VFB) vs Temperature Feedback Voltage (VFB) vs Input Voltage (VIN) FEEDBACK VOLTAGE (mV) VIN = 2.7V VIN = 3.6V 3543 G11 3543 G10 400 1.50 1.48 2.05 3.0 1.52 2.10 1.9 2.5 SUPPLY CURRENT (µA) Output Voltage vs Load Current 1.56 LOAD CURRENT (mA) SWITCHING FREQUENCY (MHz) SWITCHING FREQUENCY (MHz) Switching Frequency vs Input Voltage (VIN) 100 0 –40 –25 –10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) 3543 G17 0 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5 3543 G18 3543f 4 LTC3543 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted. Startup from Shutdown Pulse Skip Operation RUN 5V/DIV VOUT 1V/DIV INDUCTOR CURRENT 200mA/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 300mA 200µs/DIV Burst Mode Operation VOUT AC COUPLED 50mV/DIV SW 5V/DIV VOUT AC COUPLED 50mV/DIV SW 5V/DIV IL 100mA/DIV IL 100mA/DIV 3543 G19 VIN = 3.6V VOUT = 1.5V ILOAD = 3mA VMODE = 3.6V Load Step 10µs/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA VMODE = 0V 3543 G20 Load Step VOUT AC COUPLED 200mV/DIV IL 200mA/DIV VOUT AC COUPLED 100mV/DIV IL 200mA/DIV ILOAD 200mA/DIV ILOAD 200mA/DIV ILOAD 200mA/DIV 20µs/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA TO 200mA VMODE = 3.6V 3543 G22 Spread Spectrum Load Step 10µs/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 100mA TO 600mA VMODE = 3.6V 3543 G24 PLL Operation 3543 G23 PLL Operation at 3MHz VC1 200mV/DIV VOUT AC COUPLED 100mV/DIV IL 200mA/DIV 3543 G21 Load Step VOUT AC COUPLED 100mV/DIV IL 200mA/DIV 20µs/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA TO 200mA VMODE = 0V 10µs/DIV VMODE 2V/DIV SW 2V/DIV ILOAD 200mA/DIV 10µs/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 100mA TO 200mA VMODE = 0.6V 3543 G25 100µs/DIV C1 = 4µF 3MHz TO 1MHz STEP 3543 G26 100ns/DIV 3543 G27 3543f 5 LTC3543 U U U PI FU CTIO S SW (Pin 1): Switch Node Connector to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. CAP (Pin 2): Capacitor used for smoothing out spread spectrum or for PLL response. Connect to a capacitor whose other plate is connected to GND, or allow the pin to float. Value = 1nF – 10nF. MODE (Pin 3): Mode Selection Pin. Connect as follows to invoke desired operation: MODE = GND → Burst Mode, MODE = VFB → Pulse skip with spread spectrum, MODE = VIN → Pulse skip, MODE = External clock → PLL mode. VFB (Pin 4): Feedback sensing pin for the external feedback resistors. RUN (Pin 5): Run Control Input. Forcing pin above 1.5V enables the part. Forcing the pin below 0.3V shuts down the device. In shutdown, all functions are disabled, drawing <1µA of supply current. Do not leave the RUN pin floating. VIN (Pin 6): Main Supply Pin. Exposed Pad (Pin 7): Exposed Pad connected to ground. W FU CTIO AL DIAGRA U U VOUT VIN R2 VIN 6 VFB 4 0.6V R1 CIN PEAK CURRENT LEVEL REF EA RS ICOMP OSC S Q R QB BP MAIN SW L LOGIC 1 L CAP 2 C1 MODE 3 VOUT COUT SYNCHRONOUS PLL L SPREAD SPECTRUM MODE SELECT BURST IRCMP RUN 5 7 GND 3543 FD 3543f 6 LTC3543 (Refer to Functional Diagram) Main Control Loop The LTC3543 uses current mode step-down architecture with both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches internal. During normal operation, the internal top power MOSFET is turned on each cycle as the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier, EA. When the load current increases, it causes a slight decrease in the feedback voltage, VFB, relative to an internal reference voltage which, in turn, causes the EA amplifier’s output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. Burst Mode Operation The LTC3543 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. Burst Mode operation is enabled by connecting the MODE pin to ground. During Burst Mode operation, the LTC3543’s internal circuits sense when the inductor peak current falls below 100mA. When below this level, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 45µA, and holding the peak current reference level at 100mA. The LTC3543 remains in this sleep state until the feedback voltage falls below its internal reference. Once this occurs, the regulator wakes up and allows the inductor to develop 100mA current pulses. In light loads, this will cause the output voltage to increase and the internal peak current reference to decrease. When the peak current reference falls to below 100mA, the part re-enters sleep mode and the cycle is repeated. This process repeats at a rate dependent on the load demand. Pulse Skip Mode Operation Connecting the MODE pin to VIN places the LTC3543 in pulse skip mode. During light loads, the inductor can reach zero amps or reverse current on each pulse. This is caused by the bottom MOSFET being turned off by the current reversal comparator, IRCMP, at which time the switch voltage will ring. This is discontinuous mode operation, and is normal behavior for a switching regulator. At very light loads, the LTC3543 will automatically skip pulses in order to maintain output regulation. Spread Spectrum Operation Setting the MODE pin from 0.55V to 0.8V will place the part in pulse skip mode with spread spectrum; an easy way to do this is to connect the MODE pin to the VFB pin. In this mode, an external capacitor is required between CAP and GND. The external capacitor assists in smoothing frequency transitions. The spread spectrum architecture randomly varies the LTC3543’s switching frequency from 2MHz to 3MHz, significantly reducing the peak radiated and conducting noise on both the input and output supplies, making it easier to comply with electromagnetic interference (EMI) standards. Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases, the frequency of operation is either fixed or constant, based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics). Figure 1a depicts the output noise spectrum –10 RBW = 3kHz –20 –30 AMPLITUDE (dBm) U OPERATIO –40 –50 –60 –70 –80 –90 –100 –110 2.0 2.2 2.6 2.4 FREQUENCY (MHz) 2.8 3.0 3543 F01a Figure 1a. Output Noise Spectrum of Conventional Buck Switching Converter (LTC3543 with Spread Spectrum Disabled) Showing Fundamental and Harmonic Frequencies 3543f 7 LTC3543 U OPERATIO –10 external clock source whose frequency is between 1MHz and 3MHz. RBW = 3kHz –20 AMPLITUDE (dBm) –30 Selecting the switching frequency is a tradeoff between efficiency and component size. Low frequency operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. –40 –50 –60 –70 –80 –90 –100 –110 2.0 2.2 2.6 2.4 FREQUENCY (MHz) 2.8 3.0 3543 F01b Figure 1b. Output Noise Spectrum of the LTC3543 Spread Spectrum Buck Switching Converter. Note the Reduction in Fundamental and Harmonic Peak Spectral Amplitude Compared to Figure 1a. of a conventional buck switching converter (LTC3543 with spread spectrum operation disabled) with VIN = 3.6V, VOUT = 1.5V and IOUT = 300mA. Unlike conventional buck converters, the LTC3543’s internal oscillator is designed to produce a clock pulse whose frequency is randomly varied between 2MHz and 3MHz. This has the benefit of spreading the switching noise over a range of frequencies, significantly reducing the peak noise. Figure 1b shows the output noise spectrum of the LTC3543 (with spread spectrum operation enabled) with VIN = 3.6V, VOUT = 1.5V and IOUT = 300mA. Note the significant reduction in peak output noise (≅ 20dBm). Phase-Locked Loop Operation A phase-locked loop (PLL) is available on the LTC3543 to synchronize the internal oscillator to an external clock source that is connected to the MODE pin. In this case, an external capacitor should be connected between the CAP pin and GND to serve as part of the PLL’s loop filter. The LTC3543’s phase detector adjusts the voltage on the CAP pin to align the turn-on of the internal P-channel MOSFET to the rising edge of the synchronizing signal. Note that when the MODE pin is not being driven by an external clock source, the MODE pin must be held to one of the following voltage potentials: VIN, GND, or VFB. The typical capture range of the LTC3543 ’s PLL is guaranteed over temperature to be 1MHz to 3MHz. In other words, the LTC3543’s PLL is guaranteed to lock to an Note that the PLL is inhibited during soft-start and uses the internal 2.25MHz frequency until regulation is established. Also the regulator is in pulse skip mode during PLL operation. Short-Circuit Protection When the output is shorted to ground, the LTC3543 senses the high inductor current and disallows the main power FET from turning on. The main FET is held off until the inductor current decays to a normal level. Dropout Operation Depending upon the external feedback resistor ratio, it is possible for VIN to approach the output voltage level. As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3543 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). Low Supply Operation The LTC3543 will operate with input supply voltages as low as 2.5V, but the maximum allowable output current is reduced at this low voltage. Figure 2 shows the reduction in the maximum output current as a function of input voltage for various output voltages. 3543f 8 LTC3543 U OPERATIO 1500 Slope compensation provides stability in constantfrequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles >40%; however, the LTC3543 uses a patent-pending scheme that counteracts this compensating ramp, allowing the maximum inductor peak current to remain unaffected throughout all duty cycles. MAXIMUM OUTPUT CURRENT (mA) Slope Compensation and Inductor Peak Current 1400 1300 1200 VOUT = 1.2V 1100 1000 VOUT = 1.5V 900 800 700 600 500 2.5 3.0 4.0 4.5 3.5 INPUT VOLTAGE (V) 5.0 5.5 3543 F02 Figure 2. Maximum Output Current vs Input Voltage (VIN) U W U U APPLICATIO S I FOR ATIO The basic LTC3543 application circuit is shown on the front page of this datasheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Selection Inductor Core Selection For most applications, the value of the inductor will fall in the range of 1µH to 4.7µH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current, and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current, as shown in Equation 1. A reasonable starting point for setting ripple current is ΔIL = 130mA 20% ILOADMAX. Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements, and any radiated field/EMI requirements, than on what the LTC3543 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3543 applications. ∆IL = VOUT f •L ⎛ ⎞ V • ⎜ 1 − OUT ⎟ VIN ⎠ ⎝ (1) The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 665mA rated inductor should be enough for most applications (600mA + 65mA). For better efficiency, choose a low DC-resistance inductor. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 100mA. Lower inductor values (higher ΔIL) will cause this to occur CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: CIN required IRMS ≅ IOMAX • [VOUT (VIN –VOUT )]1/2 VIN (2) 3543f 9 LTC3543 U W U U APPLICATIO S I FOR ATIO Table 1. Representative Surface Mount Inductors MANUFACTURER TDK Sumida Taiyo Yuden CoEv muRata PART NUMBER VALUE (µH) MAX DC CURRENT (A) DCR (mΩ) HEIGHT (mm) VLF3010AT-2R2M1R0 2.2 1.0 100 1.0 VLF3012AT-2R2M1R0 2.2 1.0 88 1.2 VLCF4020T-2R2N1R7 2.2 1.7 54 2.0 VLCF5020-2R7N1R7 2.7 1.7 58 2.0 VLCF5020-3R3N1R6 3.3 1.6 69 2.0 VLCF5020-4R7N1R4 4.7 1.4 79 2.0 CDRH2D18/HP-2R2NC 2.2 1.6 48 2.0 NR4018T4R7M 4.7 1.7 90 1.8 NP03SB4R7M 4.7 1.2 47 1.8 DN4835-2R2 2.2 2.6 47 3.5 DN4835-3R3 3.3 2.43 58 3.5 DN4835-6R8 6.8 1.41 117 3.5 LQH32CN2R2M33 2.2 0.79 97 3.2 LQH55DN2R2M03 2.2 3.2 29 4.7 LQH55DN3R3M03 3.3 2.9 36 4.7 LQH55DN4R7M03 4.7 2.7 41 4.7 This formula has a maximum of VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there are any questions. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ΔVOUT is determined by: ⎛ 1 ⎞ ∆VOUT ≅ ∆IL ⎜ ESR + 8 fCOUT ⎟⎠ ⎝ (3) where f = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include the Sanyo POSCAP, the Kemet T510 and T495 series, and the Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. C1 Selection When spread spectrum operation is enabled, the frequency of the LTC3543 is randomly varied over the range of frequencies between 2MHz and 3MHz. In this case, a capacitor should be connected between the CAP pin and GND to smooth out the changes in frequency. This not only provides a smoother frequency spectrum but also ensures that the switching regulator remains stable by preventing abrupt changes in frequency. When the PLL mode is enabled, if the external clock frequency is greater than the internal oscillator’s frequency (OSC), then current is sourced continuously, pulling up the voltage on the CAP pin. If the external clock frequency is less than OSC, current is sunk continuously, pulling down the voltage on the CAP pin. When the external and internal 3543f 10 LTC3543 U W U U APPLICATIO S I FOR ATIO Using Ceramic Capacitors for CIN, COUT and C1 High value, low cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3543’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. This ringing can couple to the output and be mistaken as loop instability. Even worse, the sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. 0.6V ≤ VOUT < 5.5V R2 VFB LTC3543 Output Voltage Programming The output voltage is set by a resistor divider according to the following formula: ⎛ R2 ⎞ VOUT = 0 . 6 V • ⎜ 1 + ⎟ ⎝ R1⎠ (4) The external resistor divider is connected to the output allowing remote voltage sensing as shown in Figure 3. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3543 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 4. 500 400 POWER LOSS (mW) frequencies are the same but exhibit a phase difference, current pulses (sourcing or sinking) are used for an amount of time corresponding to the phase difference. The current pulses adjust the voltage on the CAP pin until the phase and frequency of the internal and external oscillators are identical. At the stable operating point, the CAP pin is high impedance and the external capacitor holds the voltage. The external cap is used by the PLL’s loop filter to help smooth out the voltage change and provide a stable input to the voltage-controlled oscillator. The value of C1 will determine how fast the loop acquires lock. Typically C1 is 1nF to 10nF in PLL mode. A value of 2.2nF is suitable in most applications. VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V VOUT = 2.5V 300 200 100 R1 GND 3543 F03 Figure 3. Setting Output Voltage 0 0.1 1 10 100 LOAD CURRENT (mA) 1000 3543 F04 Figure 4. Power Loss vs Load Current 3543f 11 LTC3543 U W U U APPLICATIO S I FOR ATIO 1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. To avoid the LTC3543 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: where TA is the ambient temperature. RSW = (RDS(ON)TOP • DC) + (RDS(ON)BOT • (1 – DC)) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses, including CIN and COUT ESR dissipative losses and inductor core losses, generally account for less than 2% total additional loss. Thermal Considerations In most applications, the LTC3543 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3543 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. TR = θJA • PD where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the temperature. The junction temperature, TJ, is given by: TJ = TA + TR As an example, consider the LTC3543 in dropout at an input voltage of 2.7V, an ambient temperature of 80°C, and a load current of 600mA. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 80°C is approximately 0.41Ω. There, power dissipated by the part is: PD = ILOAD2 • RDS(ON) = 147.6mW For the DFN package, the θJA is 64°C/W. Thus, the junction temperature of the regulator is: TJ = 80°C + 0.1476 • 64 = 89.4°C which is well below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ΔILOAD • ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability 3543f 12 LTC3543 U U W U APPLICATIO S I FOR ATIO problem. For a detailed explanation of the switching control loop theory, see Application Note 76. 5. Keep the (–) plates of CIN and COUT as close as possible. A second, more severe transient is caused by switching in loads with large (>1µF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately 25 • CLOAD. Thus, a 10µF capacitor charging to 3.3V would require a 250µs rise time, limiting the charging current to about 130mA. Design Example PC Board Layout Checklist As a design example, assume the LTC3543 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 600mA, but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 1.5V. With this information we can calculate L using Equation 1, ⎞ ⎛ V V L = OUT • ⎜ 1 − OUT ⎟ f • ∆ IL ⎝ VIN ⎠ When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3543. These items are also illustrated graphically in Figures 5 and 6. Check the following in your layout: A 3.3µH inductor works well for this application, yielding a ripple current of only 130mA. For best efficiency choose a 665mA or greater inductor with less than 0.05Ω series resistance. 1. The power traces, consisting of the GND trace, the SW trace, and the VIN trace should be kept short, direct and wide. In Equation 2, CIN will require an RMS current rating of at least 0.3A at ILOAD(MAX)/2 at temperature. 2. Does the VFB pin connect directly to the feedback voltage reference? Ensure that there is no load current running from the feedback reference voltage and the VFB pin. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 4. Keep the switching node, SW, away from the sensitive VFB node. Using Equation 3, Selecting a 4.7µF capacitor with an ESR of 0.05Ω for COUT yields an 8mV voltage ripple on the regulated output voltage. For feedback resistors, choose R1 = 402k. R2 can then be calculated using Equation 4. ⎛V ⎞ R2 = ⎜ OUT − 1⎟ • R1 = 604k ⎝ 0 . 6V ⎠ Figure 6 shows the complete circuit along with its efficiency curve. GND COUT + VOUT – – CIN + L – 3 5 RUN 2 MODE VFB VIN 1 4 CAP 6 + VIN SW C1 – R1 R2 CFWD + 3543 F07 Figure 5. LTC3543 Layout Diagram 3543f 13 LTC3543 U U W U APPLICATIO S I FOR ATIO GND VIA TO R1 VIA TO R2 VOUT VIN COUT CIN L 3 VIN 5 CAP GND RUN 2 4 SW VFB 6 1 MODE C1 R1 R2 VIA TO GND CFWD VIA TO VOUT 3543 F08 Figure 6. LTC3543 Suggested Layout U TYPICAL APPLICATIO S L 3.3µH* Li-Ion BATTERY 2.7V TO 4.2V VIN 10µF† LTC3543 PWR_EN RUN R2 604k VOUT COUT 1.5V 4.7µF** CFWD 10pF VFB MODE CAP GND EXPOSED PAD 1.5V SW R1 402k † muRata GRM40X5R106K1H520 * TDK VLCF5020-3R3N1R6 ** TDK TDKC2012X5R0J475MT 3543 TA02 100 VOUT AC COUPLED 100mV/DIV IL 200mA/DIV 90 80 VIN = 4.2V EFFICIENCY (%) 70 ILOAD 200mA/DIV 20µs/DIV VIN = 3.6V VOUT = 1.5V ILOAD = 3mA TO 200mA VMODE = 0V 3543 G22 VIN = 3.6V 60 50 40 VIN = 2.7V 30 20 10 0 0.1 VOUT = 1.5V 1 10 100 LOAD CURRENT (mA) 1000 3543 TA04 3543f 14 LTC3543 U TYPICAL APPLICATIO Spread Spectrum Application L 3.3µH* Li-Ion BATTERY 2.7V TO 4.2V Output Noise Spectrum of a Conventional Buck Switching Converter (LTC3543 with Spread Spectrum Disabled) Showing Fundamental and Harmonic Frequencies –10 RBW = 3kHz RUN –40 70 EFFICIENCY (%) 80 –40 –50 –60 –70 60 50 40 –80 30 –90 –90 20 –100 –100 10 –110 –110 0 6 18 12 FREQUENCY (MHz) 24 30 0 6 † muRata GRM40X5R106K1H520 * TDK VLCF5020-3R3N1R6 ** TDK TDKC2012X5R0J475MT 100 RBW = 3kHz 90 –80 R1 402k 3543 TA08 –30 –70 C1 2.2nF EXPOSED PAD –30 –60 VOUT COUT 1.5V 4.7µF** CFWD 10pF VFB MODE CAP GND –20 –50 R2 604k LTC3543 PWR_EN 1.5V SW –20 AMPLITUDE (dBm) AMPLITUDE (dBm) –10 Output Noise Spectrum of the LTC3543 Spread Spectrum Buck Switching Converter. Note the Reduction in Fundamental and Harmonic Peak Spectral Amplitude Compared to Conventional Buck Switching Converter Output Noise VIN 10µF† 18 12 FREQUENCY (MHz) 3543 TA09 24 VIN = 3.6V 0 0.1 30 1 10 100 LOAD CURRENT (mA) 1000 3543 TA11 3543 TA10 U PACKAGE DESCRIPTIO DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715) 3.55 ±0.05 R = 0.115 TYP 2.00 ±0.10 (2 SIDES) 0.70 ±0.05 R = 0.05 TYP 0.40 ± 0.10 4 6 1.65 ±0.05 (2 SIDES) 2.15 ±0.05 3.00 ±0.10 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 1.35 ±0.05 (2 SIDES) 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 × 45° CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 1 (DCB6) DFN 0405 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 1.35 ±0.10 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3543f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC3543 U TYPICAL APPLICATIO PLL Application Li-Ion BATTERY 2.7V TO 4.2V L 6.8µH* VIN 10µF† R2 604k LTC3543 PWR_EN INPUT CLOCK (1MHz) RUN 1.5V SW CFWD 10pF VOUT COUT 1.5V 4.7µF** VFB MODE CAP GND EXPOSED PAD C1 2.2nF R1 402k † muRata GRM40X5R106K1H520 * CoEv DN4835-6R8 ** TDK TDKC2012X5R0J475MT 3543 TA05 100 INPUT CLOCK 2V/DIV 90 80 EFFICIENCY (%) 70 SW 2V/DIV 200ns/DIV 3543 TA06 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000 3543 TA07 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchrounous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20µA, ISD = <1µA, ThinSOT Package LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchrounous Step-Down DC/DC Converter 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20µA, ISD = <1µA, ThinSOT Package LTC3407/LTC3407-2 Dual 600mA/800mA (IOUT), 1.5MHz/2.25MHz, Synchrounous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD = <1µA, MS10E, DFN Packages LTC3409 600mA (IOUT), 1.7MHz/2.6MHz, Synchrounous Step-Down DC/DC Converter 96% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65µA, ISD = <1µA, DFN Package LTC3410/LTC3410B 300mA (IOUT), 2.25MHz, Synchrounous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26µA, DC/DC Converter ISD = <1µA, SC70 Package LTC3411 1.25A (IOUT), 4MHz, Synchrounous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60µA, ISD = <1µA, MS10, DFN Packages LTC3441/LTC3442/ LTC3443 1.2A (IOUT), 2MHz, Synchrounous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 50µA, ISD = <1µA, DFN Package LTC3531/LTC3531-3/ LTC3531-3.3 200mA (IOUT), 1.5MHz, Synchrounous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN): 2V to 5V, IQ = 16µA, ISD = <1µA, ThinSOT, DFN Packages LTC3532 500mA (IOUT), 2MHz, Synchrounous Buck-Boost DC/DC Converter 96% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35µA, ISD = <1µA, MS10, DFN Packages LTC3542 500mA (IOUT), 2.25MHz, Synchrounous Step-Down 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 26µA, DC/DC Converter ISD = <1µA, 2mm × 2mm DFN, ThinSOT Packages LTC3547/LTC3547B Dual 300mA (IOUT), 2.25MHz, Synchrounous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD = <1µA, DFN Package LTC3548/LTC3548-1/ LTC3548-2 Dual 400mA/800mA (IOUT), 2.25MHz, Synchrounous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40µA, ISD = <1µA, MS10E, DFN Packages LTC3561 1.25A (IOUT), 4MHz, Synchrounous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 240µA, ISD = <1µA, DFN Package 3543f 16 Linear Technology Corporation LT 1206 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006