CY23EP05 2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output Zero Delay Buffer Features Functional Description • 10 MHz to 220 MHz maximum operating range The CY23EP05 is a 2.5V or 3.3V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has a higher drive strength than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. • Zero input-output propagation delay, adjustable by loading on CLKOUT pin • Multiple low-skew outputs — 30 ps typical output-output skew — One input drives five outputs • 22 ps typical cycle-to-cycle jitter The CY23EP05 PLL enters a power-down mode when there are no rising edges on the REF input (<~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 µA of current draw. • 13 ps typical period jitter • Standard and High drive strength options • Available in space-saving 150-mil SOIC package The CY23EP05 is available in different configurations, as shown in the Ordering Information table. The CY23EP05-1 is the base part. The CY23EP05-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. • 3.3V or 2.5V operation • Industrial temperature available These parts are not intended for 5V input-tolerant applications Block Diagram Pin Configuration Top View REF CLKOUT PLL REF CLK2 CLK1 GND CLK1 CLK2 1 8 2 7 3 6 4 5 CLKOUT CLK4 VDD CLK3 CLK3 CLK4 Cypress Semiconductor Corporation Document #: 38-07759 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 13, 2005 CY23EP05 Pin Description Pin Signal Description 1 REF[1] Input reference frequency 2 CLK2[2] Buffered clock output 3 CLK1[2] Buffered clock output 4 GND Ground 5 CLK3[2] Buffered clock output 6 VDD 3.3V or 2.5V supply [2] 7 CLK4 Buffered clock output 8 CLKOUT[2,3] Buffered clock output, internal feedback on this pin Zero Delay and Skew Control All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. The output driving the CLKOUT pin will be driving a total load of 5 pF plus any additional load externally connected to this pin. For applications requiring zero input-output delay, the total load on each output pin (including CLKOUT) must be the same. If input-output delay adjustments are required, the CLKOUT load may be changed to vary the delay between the REF input and remaining outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note titled “CY2305 and CY2309 as PCI and SDRAM Buffers”. Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Document #: 38-07759 Rev. *B Page 2 of 12 CY23EP05 Absolute Maximum Conditions Storage Temperature .................................... –65°C to 150°C Supply Voltage to Ground Potential ................. –0.5V to 4.6V DC Input Voltage...................................... VSS – 0.5V to 4.6V Junction Temperature .................................................. 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015.............................. > 2000V Operating Conditions Parameter Description Min. Max. Unit VDD3.3 3.3V Supply Voltage 3.0 3.6 V VDD2.5 2.5V Supply Voltage 2.3 2.7 V TA Operating Temperature (Ambient Temperature)—Commercial Operating Temperature (Ambient Temperature)—Industrial CL[4] 0 70 °C –40 85 °C Load Capacitance, <100 MHz, 3.3V – 30 pF Load Capacitance, <100 MHz, 2.5V with High drive – 30 pF Load Capacitance, <133.3 MHz, 3.3V – 22 pF Load Capacitance, <133.3 MHz, 2.5V with High drive – 22 pF Load Capacitance, <133.3 MHz, 2.5V with Standard drive – 15 pF Load Capacitance, >133.3 MHz, 3.3V – 15 pF Load Capacitance, >133.3 MHz, 2.5V with High drive – 15 pF CIN Input Capacitance[5] – 5 pF BW Closed-loop bandwidth (typical), 3.3V 1–1.5 MHz Closed-loop bandwidth (typical), 2.5V 0.8 MHz Output Impedance (typical), 3.3V High drive 29 Ω Output Impedance (typical), 3.3V Standard drive 41 Ω Output Impedance (typical), 2.5V High drive 37 Ω Output Impedance (typical), 2.5V Standard drive 41 Ω ROUT tPU Power-up time for all VDD’s to reach minimum specified voltage (power ramps must be monotonic) Theta Ja[6] Theta Jc[6] 0.01 50 ms Dissipation, Junction to Ambient, 8-pin SOIC 131 °C/W Dissipation, Junction to Case, 8-pin SOIC 81 °C/W 3.3V DC Electrical Specifications Parameter Description Test Conditions Min. Max. Unit 3.0 3.6 V – 0.8 V VDD Supply Voltage VIL Input LOW Voltage VIH Input HIGH Voltage 2.0 VDD + 0.3 V IIL Input Leakage Current 0 < VIN < VIL – ±10 µA IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage IOL = 8 mA (standard drive) IOL = 12 mA (High drive) – – 0.4 0.4 V V VOH Output HIGH Voltage IOH = –8 mA (standard drive) IOH = –12 mA (High drive) 2.4 2.4 – – V V IDD (PD mode) Power Down Supply Current REF = 0 MHz (Commercial) IDD Supply Current – 12 µA REF = 0 MHz (Industrial) – 25 µA Unloaded outputs, 66-MHz REF – 30 mA Notes: 4. Applies to Test Circuit #1. 5. Applies to both REF Clock and internal feedback path on CLKOUT. 6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1. Document #: 38-07759 Rev. *B Page 3 of 12 CY23EP05 2.5V DC Electrical Specifications Parameter Description VDD Supply Voltage VIL Input LOW Voltage Test Conditions Min. Max. Unit 2.3 2.7 V – 0.7 V 1.7 VDD + 0.3 V – 10 µA VIH Input HIGH Voltage IIL Input Leakage Current 0<VIN < VDD IIH Input HIGH Current VIN = VDD – 100 µA VOL Output LOW Voltage IOL = 8 mA (Standard drive) IOL = 12 mA (High drive) – – 0.5 0.5 V V VOH Output HIGH Voltage IOH = –8 mA (Standard drive) IOH = –12 mA (High drive) VDD – 0.6 VDD – 0.6 – – V V IDD (PD mode) Power Down Supply Current REF = 0 MHz (Commercial) – 12 µA REF = 0 MHz (Industrial) – 25 µA IDD Supply Current Unloaded outputs, 66-MHz REF – 45 mA 3.3V and 2.5V AC Electrical Specifications Parameter 1/t1 Description Maximum Frequency[7] (Input/Output) TIDC Input Duty Cycle t2 ÷ t1 Output Duty Cycle[8] t3,t4 Rise, Fall Time (3.3V)[8] t3, t4 Rise, Fall Time (2.5V)[8] Min. Typ. Max. Unit 3.3V High drive Test Conditions 10 – 220 MHz 3.3V Standard drive 10 – 167 MHz 2.5V High drive 10 – 200 MHz 2.5V Standard drive 10 – 133 MHz <133.3 MHz 25 – 75 % >133.3 MHz 40 – 60 % <133.3 MHz 47 – 53 % >133.3 MHz 45 – 55 % Std drive, CL = 30 pF, <100 MHz – – 1.6 ns Std drive, CL = 22 pF, <133.3 MHz – – 1.6 ns Std drive, CL = 15 pF, <167 MHz – – 0.6 ns High drive, CL = 30 pF, <100 MHz – – 1.2 ns High drive, CL = 22 pF, <133.3 MHz – – 1.2 ns High drive, CL = 15 pF, >133.3 MHz – – 0.5 ns Std drive, CL = 15 pF, <133.33 MHz – – 1.5 ns High drive, CL = 30 pF, <100 MHz – – 2.1 ns High drive, CL = 22 pF, <133.3 MHz – – 1.3 ns High drive, CL = 15 pF, >133.3 MHz – – 1.2 ns All outputs equally loaded – 30 100 ps –100 – 100 ps –200 – 200 ps Measured at VDD/2. Any output to any output, 3.3V supply – – ±150 ps Measured at VDD/2. Any output to any output, 2.5V supply – – ±300 ps t5 Output to Output Skew [8] t6 Delay, REF Rising Edge to PLL enabled @ 3.3V CLKOUT Rising Edge[8] PLL enabled @2.5V t7 Part to Part Skew[8] Notes: 7. For the given maximum loading conditions. See CL in Operating Conditions Table. 8. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07759 Rev. *B Page 4 of 12 CY23EP05 3.3V and 2.5V AC Electrical Specifications (continued) Parameter Description Test Conditions Min. Typ. Max. Unit Stable power supply, valid clocks presented on REF and CLKOUT pins – – 1.0 ms – 22 55 ps 3.3V supply, >66 MHz, <30 pF, standard drive – 45 125 ps 3.3V supply, >66 MHz, <30 pF, high drive – 45 100 ps 2.5V supply, >66 MHz, <15 pF, standard drive – 40 100 ps 2.5V supply, >66 MHz, <15 pF, high drive – 35 80 ps 2.5V supply, >66 MHz, <30 pF, high drive – 52 125 ps 3.3V supply, 66–100 MHz, <15 pF – 18 60 ps tLOCK PLL Lock Time[8] TJCC[8,9] Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF TPER[8,9] Period Jitter, Peak 3.3V supply, >100 MHz, <15 pF – 13 35 ps 3.3V supply, >66 MHz, <30 pF, standard drive – 28 75 ps 3.3V supply, >66 MHz, <30 pF, high drive – 26 70 ps 2.5V supply, >66 MHz, <15 pF, standard drive – 25 60 ps 2.5V supply, 66–100 MHz, <15 pF, high drive – 22 60 ps 2.5V supply, >100 MHz, <15 pF, high drive – 19 45 ps Switching Waveforms Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 All Outputs Rise/Fall Time 2.0V(1.8V) 0.8V(0.6V) OUTPUT 2.0V(1.8V) 0.8V(0.6V) 3.3V(2.5V) 0V t4 t3 Output-Output Skew OUTPUT VDD/2 VDD/2 OUTPUT t5 Note: 9. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be found in the application notes, “Understanding Data Sheet Jitter Specifications for Cypress Products.” Document #: 38-07759 Rev. *B Page 5 of 12 CY23EP05 Switching Waveforms (continued) Input-Output Propagation Delay INPUT VDD/2 VDD/2 CLKOUT t6 Part-Part Skew VDD/2 Any output, Part 1 or 2 VDD/2 Any output, Part 1 or 2 t7 Test Circuits Test Circuit # 1 V DD CLK 0.1 µ F OUTPUTS C LOAD V DD 0.1 µ F GND Document #: 38-07759 Rev. *B GND Page 6 of 12 CY23EP05 Delay REF Input to CLKn (ps) Supplemental Parametric Information 1500 1250 1000 750 500 250 0 -250 -500 -750 -1000 -1250 -1500 2.5V Standard Drive 2.5V High Drive -20 -10 0 10 20 Load CLKOUT- Load CLKn (pF) Figure 1. 2.5V Typical Room Temperature Graph for REF Input to CLKn Delay versus Loading Difference between CLKOUT and CLKn. Data is shown for 66 MHz. Delay is a weak function of frequency. Delay REF Input to CLKn (ps) 1000 3.3V Standard Drive 3.3V High Drive 800 600 400 200 0 -200 -400 -600 -800 -1000 -20 -10 0 10 20 Load CLKOUT- Load CLKn (pF) Figure 2. 3.3V Typical Room Temperature Graph for REF Input to CLKn Delay versus Loading Difference between CLKOUT and CLKn. Data is shown for 66 MHz. Delay is a weak function of frequency. Document #: 38-07759 Rev. *B Page 7 of 12 CY23EP05 70 60 50 40 30 15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 20 15pF, -45C, High Drive 15pF, 90C, High Drive 10 30pF, -45C, High Drive 30pF, 90C, High Drive 0 33 66 100 133 166 200 Frequency (MHz) Figure 3. 2.7V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF. 100 80 60 15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 30pF, -45C, Standard Drive 30pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive 40 20 0 33 66 100 133 166 200 233 Frequency (MHz) Figure 4. 3.6V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF high-drive data above 100 MHz is beyond the data sheet specification of 22 pF. Document #: 38-07759 Rev. *B Page 8 of 12 CY23EP05 350 15 pF, Standard Drive 15 pF, High Drive 30 pF, Standard Drive 30 pF, High Drive 300 250 200 150 100 50 0 0 50 100 150 200 250 Frequency (MHz) Figure 5. Typical 3.3V Measured Cycle-to-cycle Jitter at 29°C, versus Frequency, Drive Strength, and Loading 400 15 pF, Standard Drive 15 pF, High Drive 30 pF, High Drive 350 300 250 200 150 100 50 0 0 20 40 60 80 100 120 140 160 180 200 Frequency (MHz) Figure 6. Typical 2.5V Measured Cycle-to-cycle Jitter at 29°C, versus Frequency, Drive Strength, and Loading 250 15 pF, Standard Drive 15 pF, High Drive 30 pF, Standard Drive 30 pF, High Drive 200 150 100 50 0 0 50 100 150 200 250 Frequency (MHz) Figure 7. Typical 3.3V Measured Period Jitter at 29°C, versus Frequency, Drive Strength, and Loading 250 15 pF, Standard Drive 15 pF, High Drive 30 pF, High Drive 200 150 100 50 0 0 20 40 60 80 100 120 140 160 180 200 Frequency (MHz) Figure 8. Typical 2.5V Measured Period Jitter at 29°C, versus Frequency, Drive Strength, and Loading Document #: 38-07759 Rev. *B Page 9 of 12 CY23EP05 -90 SSB Phase Noise (dBc/Hz) -100 3.3V High Drive 3.3V Standard Drive -110 -120 2.5V High Drive 2.5V Standard Drive -130 100 MHz -140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 Offset Frequency (Hz) -90 SSB Phase Noise (dBc/Hz) -100 3.3V High Drive 3.3V Standard Drive -110 -120 2.5V High Drive -130 2.5V Standard Drive 156.25 MHz -140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 Offset Frequency (Hz) Figure 9. 100 MHz (top) and 156.25 MHz (bottom) Typical Phase-noise Data versus VDD and Drive Strength[9] Document #: 38-07759 Rev. *B Page 10 of 12 CY23EP05 Ordering Information Ordering Code Package Type Operating Range Lead-free CY23EP05SXC-1 8-pin 150-mil SOIC Commercial CY23EP05SXC-1T 8-pin 150-mil SOIC – Tape and Reel Commercial CY23EP05SXI-1 8-pin 150-mil SOIC Industrial CY23EP05SXI-1T 8-pin 150-mil SOIC – Tape and Reel Industrial CY23EP05SXC-1H 8-pin 150-mil SOIC Commercial CY23EP05SXC-1HT 8-pin 150-mil SOIC – Tape and Reel Commercial CY23EP05SXI-1H 8-pin 150-mil SOIC Industrial CY23EP05SXI-1HT 8-pin 150-mil SOIC – Tape and Reel Industrial Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07759 Rev. *B Page 11 of 12 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY23EP05 Document History Page Document Title: CY23EP05 2.5V or 3.3V, 10-220-MHz, Low Jitter, 5 Output Zero Delay Buffer Document Number: 38-07759 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 349620 See ECN RGL New data sheet *A 401073 See ECN RGL Updated Delay vs. Load graph with standard drive data Added Phase-noise graph *B 413826 See ECN RGL Minor Change: typo - changed from CY23EP05SXC-T to CY23EP05SXC-1T Document #: 38-07759 Rev. *B Page 12 of 12