Rev 1; 10/08 I2C Gamma and VCOM Buffer with EEPROM The DS3514 is a programmable gamma and VCOM voltage generator that supports both real-time updating as well as multibyte storage of gamma/VCOM data in onchip EEPROM memory. An independent 10-bit DAC, two 10-bit data registers, and four words of EEPROM memory are provided for each individually addressable gamma or V COM channel. High-performance buffer amplifiers are integrated on-chip, providing rail-to-rail, low-power (400µA/gamma channel) operation. The VCOM channel features a high current drive (> 250mA peak) and a fast-settling buffer amplifier optimized to drive the VCOM node of a wide range of TFT-LCD panels. Programming occurs through an I2C-compatible serial interface. Interface performance and flexibility are enhanced by a pair of independently loaded data latches per channel, as well as support for I2C speeds up to 400kHz. The multitable EEPROM memory enables a rich variety of display system enhancements, including support for temperature or light-level dependent gamma tables, enabling of factory or field automated display adjustment, and support for backlight dimming algorithms to reduce system power. Upon power-up and depending on mode, DAC data is selected from EEPROM by the S0/S1 pins or from a fixed memory address. Features ♦ 10-Bit Gamma Buffers, 14 Channels ♦ 8-Bit VCOM Buffer, 1 Channel ♦ Four 10-Bit EEPROM Words per Channel ♦ Low-Power 400µA/ch Gamma Buffers ♦ I2C-Compatible Serial Interface ♦ Flexible Control from I2C or Pins ♦ 9.0V to 15.0V Analog Supply ♦ 2.7V to 5.5V Digital Supply ♦ 48-Pin TQFN Package (7mm x 7mm) Ordering Information PART TEMP RANGE PIN-PACKAGE DS3514T+ -45°C to +95°C 48 TQFN-EP* DS3514T+T&R -45°C to +95°C 48 TQFN-EP* +Denotes a lead-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad. Applications TFT-LCD Gamma and VCOM Buffer Pin Configuration and Typical Operating Circuit appear at end of data sheet. Adaptive Gamma and VCOM Adjustment (Real Time by I2C, Select EEPROM Through I2C or S0/S1 Pins) Industrial Process Control Gamma or VCOM Channel Functional Diagram SDA, SCL A0 I2C INTERFACE LATCH A MUX IN LATCH B 8-/ 10-BIT* DAC VOUT OUT EEPROM S1/ S0 LOGIC ADDRESS LD * 10 BITS FOR GAMMA CHANNELS, 8 BITS FOR THE VCOM CHANNEL. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS3514 General Description DS3514 I2C Gamma and VCOM Buffer with EEPROM ABSOLUTE MAXIMUM RATINGS Junction Temperature ......................................................+125°C Operating Temperature Range ...........................-45°C to +95°C Programming Temperature Range .........................0°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Voltage Range on VDD Relative to GND ................-0.5V to +16V Voltage Range on VRL, VRH, GHH, GHM, GLM, GLL Relative to GND.........-0.5V to (VDD + 0.5V), not to exceed 16V Voltage Range on VCC Relative to GND ..................-0.5V to +6V Voltage Range on SDA, SCL, A0, LD, S0, S1 Relative to GND .....-0.5V to (VCC + 0.5V), not to exceed 6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -45°C to +95°C.) MAX UNITS Digital Supply Voltage PARAMETER VCC (Notes 1, 2) 2.7 5.5 V Analog Supply Voltage VDD (Note 1) 9.0 15.0 V VVCOM Applies to VCOM output 2.0 VDD - 2.0 V VGM1–14 Applies to GM1–GM14 GND + 0.2 VDD - 0.2 V VRH, VRL Voltage GHH, GHM, GLM, GLL Voltage SYMBOL CONDITIONS MIN TYP Input Logic 1 (SCL, SDA, A0, S0, S1, LD) VIH 0.7 x VCC VCC + 0.3 V Input Logic 0 (SCL, SDA, A0, S0, S1, LD) VIL -0.3 0.3 x VCC V VCOM Load Capacitor VCAP Compensation Capacitor CD 1 μF CCOMP 0.1 μF INPUT ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, unless otherwise noted.) PARAMETER Input Leakage (SDA, SCL, A0, S0, S1, LD) SYMBOL CONDITIONS IL MIN TYP -1 MAX UNITS +1 μA VDD Supply Current IDD (Note 3) 5 10 mA VCC Supply Current, Nonvolatile Read or Write ICC (Note 4) 0.25 0.6 mA VCC Standby Supply Current ICCQ (Note 5) 10 30 μA VDD Standby Supply Current IDDQ (Note 6) 450 850 μA I/O Capacitance (SDA, SCL, LD, S0, S1, A0) CI/O Guaranteed by design 5 10 pF End-to-End Resistance (VRH to VRL) RTOTAL Tolerance 2 RTOTAL 16 TA = +25°C° -20 _______________________________________________________________________________________ k +20 % I2C Gamma and VCOM Buffer with EEPROM (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Input Resistance (GHH, GHM, GLM, GLL) Power-Up Time MAX 75 Input Resistance Tolerance Power-On Recall Voltage TYP UNITS k TA = +25°C -20 +20 VPOR (Note 7) 1.6 2.6 tD (Note 8) 25 % V ms OUTPUT ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, VRL = +2.0V, GLL = +0.2V, GLM = +4.8V, GHM = +10.2V, VRH = +13.0V, GHH = +14.8V, TA = -45°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GM1–GM14 DAC Resolution 10 Bits VCOM DAC Resolution 8 Bits VCOM Integral Nonlinearity Error INL TA = +25°C (Note 9) -0.5 +0.5 LSB VCOM Differential Nonlinearity Error DNL TA = +25°C (Note 10) -0.5 +0.5 LSB GM1–GM14 Integral Nonlinearity Error INL TA = +25°C (Note 9) -1.0 +1.0 LSB GM1–GM14 Differential Nonlinearity Error DNL TA = +25°C (Note 10) -0.35 +0.35 LSB Output Voltage Range (VCOM) 2.0 VDD - 2.0 V Output Voltage Range (GM1–G14) 0.2 VDD - 0.2 V +20 mV VCOM Output Accuracy TA = +25°C GM1–GM14 Offset GM outputs = VDD/2, TA = +25°C GM1–GM14 Output Accuracy GM outputs = VDD/2, TA = +25°C Voltage Gain (GM1–GM14) -20 37 -35 mV +35 0.995 Load Regulation (VCOM, GM1–GM14) V/V 1.0 Short-Circuit Current (VCOM) To VDD or GND mV mV/mA 250 mA S0/S1 to LD Setup Time t SU Figure 2 37.5 ns S0/S1 to LD Hold Time tHD Figure 2 37.5 ns 2.0 μs VCOM Settling Time from LD Low to High (S0/S1 Meet tSU) t SET-V Settling to 0.1% of final VCOM level (Figure 1) (Note 11) GM1–GM14 Settling Time from LD Low to High t SET-G 4tAU settled with ILOAD= ±20mA (Figure 2) (Notes 11, 12, 13) 5.0 μs t SEL 10% settling (Figure 3), LD = VCC (asynchronous) (Notes 11, 13) 600 ns S0, S1 to GM1–GM14 Output 10% Settled _______________________________________________________________________________________ 3 DS3514 INPUT ELECTRICAL CHARACTERISTICS (continued) DS3514 I2C Gamma and VCOM Buffer with EEPROM I2C ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -45°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN). See Figure 4.) PARAMETER SYMBOL CONDITIONS TYP UNITS 400 kHz Bus-Free Time between STOP and START Conditions tBUF 1.3 μs Hold Time (Repeated) START Condition tHD:STA 0.6 μs tLOW 1.3 μs High Period of SCL 0 MAX f SCL Low Period of SCL (Note 14) MIN SCL Clock Frequency tHIGH 0.6 Data Hold Time tHD:DAT 0 Data Setup Time t SU:DAT 100 ns START Setup Time t SU:STA 0.6 μs SDA and SCL Rise Time tR (Note 15) 20 + 0.1CB 300 ns SDA and SCL Fall Time tF (Note 15) 20 + 0.1CB 300 ns STOP Setup Time t SU:STO μs 0.9 0.6 μs μs SDA and SCL Capacitive Loading CB (Note 15) 400 pF EEPROM Write Time tW (Note 16) 20 ms Pulse-Width Suppression Time at SDA and SCL Inputs t IN (Note 17) 50 ns A0 Setup Time t SU:A Before START A0 Hold Time tHD:A After STOP SDA and SCL Input Buffer Hysteresis Input Capacitance on A0, SDA, or SCL 0.6 μs 0.6 μs 0.05 x VCC V 5 CI 10 pF Low-Level Output Voltage (SDA) VOL 4mA sink current 0.4 V SCL Falling Edge to SDA Output Data Valid tAA SCL falling through 0.3 x VCC to SDA exit 0.3 x VCC to 0.7 x VCC window 900 ns Output Data Hold tDH SCL falling through 0.3x VCC until SDA in 0.3 x VCC to 0.7 x VCC window 4 0 _______________________________________________________________________________________ ns I2C Gamma and VCOM Buffer with EEPROM (VCC = +2.7V to +5.5V.) PARAMETER SYMBOL EEPROM Write Cycles Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: CONDITIONS MIN MAX TA = +85°C (Guaranteed by design) 50,000 TA = +25°C (Guaranteed by design) 200,000 UNITS Writes All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative. If VCC is less than +2.7V or is left unconnected, the DS3514 pulls the I2C bus to VCC, preventing communication with other devices on the I2C bus. IDD supply current is specified with VDD = 15.0V and no load on VCOM or GM1–GM14 outputs. ICC is specified with the following conditions: SCL = 400kHz, SDA = VCC = 5.5V, and VCOM and GM1–GM14 floating. ICCQ is specified with the following conditions: SCL = SDA = VCC = 5.5V, and VCOM and GM1–GM14 floating. IDDQ is specified with the following conditions: SCL = SDA = VCC = 5.5V and VCOM and GM1–GM14 floating. This is the minimum VCC voltage that causes EEPROM to be recalled. This is the time from VCC > VPOR and VDD > VDD(MIN) until the device is powered up. Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. INL = [V(RW)i - (V(RW)0]/LSB(measured) - i, for i = 0...N (N = 255 for VCOM, 1023 for GM1–GM14). Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position. DNL = [V(RW)i+1 - (V(RW)i]/LSB(measured) - 1, for i = 0...(N - 1) (N = 255 for VCOM, 1023 for GM1–GM14). Specified with the VCOM and gamma bias currents set to 100% (CR.5 = 1, CR.4 = 0). EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected. Rising transition from 5V to 10V; falling transition from 10V to 5V. I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-mode timing. CB—total capacitance of one bus line in picofarads. EEPROM write time begins after a STOP condition occurs. Pulses narrower than max are suppressed. VRH VDD DS3514 VCOM 80h 8-BIT DAC VCOM 2.2Ω CD = 1μF 0.1μF 0 TO 1.5V 50kHz VRL Figure 1. VCOM Settling Timing Diagram _______________________________________________________________________________________ 5 DS3514 NONVOLATILE MEMORY CHARACTERISTICS DS3514 I2C Gamma and VCOM Buffer with EEPROM VIH S0/S1 VIL tHD tSU tSET-G GM1–GM14 VIH 100pF ILOAD LD VIL 4tAU SETTLED GM1–G14 Figure 2. GM1–GM14 Settling Timing Diagram VIH S0/S1 (LD = VCC) VIL GM1–GM14 tSEL 100pF OUTPUT 10% SETTLED GM1–GM14 Figure 3. Input Pin to Output Change Timing Diagram SDA tBUF tF tHD:STA tLOW tSP SCL tHIGH tHD:STA tHD:DAT STOP tSU:STA tR START tSU:DAT REPEATED START NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure 4. I2C Timing Diagram 6 _______________________________________________________________________________________ tSU:STO I2C Gamma and VCOM Buffer with EEPROM DIGITAL SUPPLY STANDBY CURRENT vs. VCC 20 15 10 450 DS3514 toc03 25 ICCQ CURRENT (μA) 25 SDA = SCL = VCC 400 350 IDDQ CURRENT (μA) SDA = SCL = VCC DS3514 toc02 30 DS3514 toc01 30 ICCQ CURRENT (μA) ANALOG SUPPLY STANDBY CURRENT vs. VDD DIGITAL SUPPLY STANDBY CURRENT vs. TEMPERATURE 20 VCC = 5.0V 15 10 300 250 200 150 100 5 5 50 VCC = 3.3V 0 3 4 6 5 -45 15 35 55 75 9 95 11 15 13 VDD VOLTAGE (V) ANALOG SUPPLY STANDBY CURRENT vs. TEMPERATURE ANALOG SUPPLY CURRENT vs. VDD ANALOG SUPPLY CURRENT vs. TEMPERATURE 200 150 BIAS = 100% 6 5 4 BIAS = 80% 3 2 50 1 0 0 15 35 55 75 BIAS = 80% BIAS = 60% 0 11 13 15 -45 VDD VOLTAGE (V) TEMPERATURE (°C) GAMMA SETTLING DS3514 toc07 15 BIAS = 150% 9 12 GM OUTPUT (V) BIAS = 80% 7 BIAS = 60% 6 5 VDD = 15.0V, GHH = 14.8V, GHM = 10.2V, GLM = 4.8V, GLL = 0.2V -25 -5 15 35 55 75 95 TEMPERATURE (°C) GM DNL GAMMA OUTPUT vs. SETTING 10 BIAS = 100% 4 1 9 95 5 0.25 GM8 TO GM14 9 6 GM1 TO GM7 DS3514 toc09 -5 BIAS = 100% 6 2 0.20 0.15 0.10 GM DNL (LSB) -25 7 3 BIAS = 60% DS3514 toc08 -45 BIAS = 150% 8 7 100 9 IDD CURRENT (mA) 250 BIAS = 150% 8 IDD CURRENT (mA) 300 10 DS3514 toc06 9 DS3514 toc05 DS3514 toc04 10 350 GAMMA VOLTAGE (V) -5 TEMPERATURE (°C) 400 8 -25 VCC VOLTAGE (V) 450 IDDQ CURRENT (μA) 0 0 2 0.05 0 -0.05 -0.10 3 -0.15 0 -0.25 -0.20 4 -1 0 1 2 TIME (μs) 3 4 5 0 128 256 384 512 640 768 896 1024 GAMMA SETTING (DEC) 0 128 256 384 512 640 768 896 1024 GAMMA SETTING (DEC) _______________________________________________________________________________________ 7 DS3514 Typical Operating Characteristics (VCC = +5.0V, VDD = +15V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = +5.0V, VDD = +15V, TA = +25°C, unless otherwise noted.) VCOM INL VCOM DNL 0.40 0.30 0 0.20 0.10 0 -0.20 -0.30 -0.40 -0.40 -0.50 0 32 64 96 128 160 192 224 256 32 120 90 60 30 1.0E-6 LOAD CAPACITANCE (F) 10.0E-6 500 UNITY GAIN BANDWIDTH (kHz) 150 96 128 160 192 224 256 VCOM UNITY GAIN BANDWIDTH vs. LOAD CAPACITANCE DS3514 toc13 180 64 VCOM SETTING (DEC) VCOM PHASE MARGIN vs. LOAD CAPACITANCE PHASE MARGIN (DEGREES) 0 VCOM SETTING (DEC) GAMMA SETTING (DEC) 8 0 -0.30 128 256 384 512 640 768 896 1024 0 100.0E-9 0.10 DS3514 toc14 0 0.20 -0.20 -0.50 -0.50 0.30 -0.10 -0.10 -0.25 0.40 VCOM INL (LSB) VCOM DNL (LSB) 0.25 0.50 DS3514 toc11 DS3514 toc10 0.50 DS3514 toc12 GM INL 0.50 GM INL (LSB) DS3514 I2C Gamma and VCOM Buffer with EEPROM 400 300 200 100 0 100.0E-9 1.0E-6 10.0E-6 LOAD CAPACITANCE (F) _______________________________________________________________________________________ I2C Gamma and VCOM Buffer with EEPROM PIN NAME TYPE 1–5, 9, 10, 46, 48 N.C. — FUNCTION No Connection 6, 23, 43 VDD Power 7 VRH Ref Input High-Voltage Reference for VCOM DAC Analog Supply (9.0V to 15.5V) Low-Voltage Reference for VCOM DAC 8 VRL Ref Input 11, 18, 19, 21, 22, 42 GND Power Ground 12 S1 Input 13 S0 Input Select Inputs. When the Control register [1,0] = 00, S0 and S1 are used to select DAC input data from EEPROM. 14 LD Input 15 SDA Input/Output 16 SCL Input I2C Serial Clock Input 17, 47 VCC Power Digital Supply (2.7V to 5.5V) Compensation Capacitor Input. Connect VCAP to GND through a 0.1μF capacitor. Latch Data Input. When LD is low, Latch B retains existing data (acts as a latch). When LD is high, the input to Latch B data flows through to the output and updates the DACs asynchronously. I2C Serial Data Input/Output 20 VCAP Input 24–30 GM1–GM7 Output Low-Voltage Gamma Analog Outputs 31–37 GM8–GM14 Output High-Voltage Gamma Analog Outputs 38 GLM Ref Input Reference for Low-Voltage Gamma DAC 39 GLL Ref Input Reference for Low-Voltage Gamma DAC 40 GHM Ref Input Reference for High-Voltage Gamma DAC 41 GHH Ref Input 44 VCOM Output 45 A0 Input EP GND — Reference for High-Voltage Gamma DAC VCOM Analog Output. This output requires a 1μF capacitor to GND. Address Input. This pin determines the DS3514’s I2C slave address. Ground. Exposed Pad. Connect to GND. _______________________________________________________________________________________ 9 DS3514 Pin Description I2C Gamma and VCOM Buffer with EEPROM DS3514 Block Diagram GHH BANKS GM14 BANK A GM14 BANK B GM14 BANK C GM14 BANK D DS3514 S0/S1 PINS S0/S1 BITS GHH GHH MUX 0 0 10 BITS LATCH B 10-BIT DAC 1 GM14 LATCH A 1 LD GHM I2C MODE1 BIT MODE0 BIT COMP BANKS GM8 BANK A GM8 BANK B GM8 BANK C GM8 BANK D S0/S1 PINS S0/S1 BITS GHH MUX 0 0 10 BITS LATCH B 10-BIT DAC 1 GM8 LATCH A 1 LD GHM SDA SCL A0 I2C INTERFACE I2C I2C COMP LOGIC AND CONTROL MODE1 BIT GHM MODE0 BIT (CR.0) S0 S1 LD MODE0 BIT MODE1 BIT (CR.1) S0/S1 PINS BANKS VCOM BANK A VCOM BANK B VCOM BANK C VCOM BANK D VRH MUX 0 S0/S1 PINS 0 S0/S1 BITS 1 8 BITS LATCH B 8-BIT DAC 1 VCOM S0/S1 BITS (SOFT S0/S1) LD I2C COMP LATCH A LD VRL MODE1 BIT MODE0 BIT GLM VCAP COMPENSATION COMP BANKS GM7 BANK A GM7 BANK B GM7 BANK C GM7 BANK D GLM GLM MUX 0 S0/S1 PINS 0 S0/S1 BITS 1 10 BITS LATCH B 10-BIT DAC 1 GM7 LATCH A LD GLL VDD I2C COMP VDD GHM MODE0 BIT MODE1 BIT VCC VCC BANKS GM1 BANK A GM1 BANK B GM1 BANK C GM1 BANK D GND S0/S1 PINS S0/S1 BITS GLM MUX 0 0 1 10 BITS LATCH B 10-BIT DAC 1 LATCH A GM1 LD GLL I2C COMP MODE0 BIT MODE1 BIT GLL 10 ______________________________________________________________________________________ GLL I2C Gamma and VCOM Buffer with EEPROM The DS3514 operates in one of three modes that determine how the V COM and gamma DACs are controlled/updated. The first two modes allow “banked” control of the 14 gamma channels and one VCOM channel. Depending on the mode, one of four banks (in EEPROM) can be selected using either the S0/S1 pins or using the SOFT S0/S1 bits in the Soft S0/S1 register. Once a bank is selected, the LD pin can then be used to simultaneously update each channel’s DAC output. The third and final mode is not banked. It allows I2C control of each channel’s Latch A register that is SRAM (volatile), allowing quick and unlimited updates. In this mode, the LD pin can also be used to simultaneously update each channel’s DAC output. A detailed description of the three modes as well as additional features of the DS3514 follows. Mode Selection The DS3514 mode of operation is determined by two bits located in Control register (CR, register 48h), which is nonvolatile (NV) (EEPROM). In particular, the mode is determined by the MODE0 bit (CR.0) and the MODE1 bit (CR.1). Table 1 illustrates how the two control bits are used to select the operating mode. When shipped from the factory, the DS3514 is programmed with both MODE bits set to zero. S0/S1 Pin-Controlled Bank-Updating Mode As shown in the Block Diagram, each channel contains four words of EEPROM that are used to implement the “banking” functionality. Each bank contains unique DAC settings for each channel. When the DS3514 is configured in this operating mode, the desired bank is selected using the S0 and S1 pins as shown in Table 2 where 0 is ground and 1 is VCC. For example, if S0 and S1 are both connected to ground, the first bank (Bank A) is selected. Once a bank is selected, the timing of the DAC update depends on the state of LD pin. When LD is high, Latch B functions as a flow-through latch, so the amplifier responds asynchronously to changes in Table 1. Operating Modes MODE1 BIT (CR.1) MODE0 BIT (CR.0) 0 0 0 1 the state of S0/S1 to meet the t SEL specification. Conversely, when LD is low, Latch B functions as a latch, holding its previous data. A low-to-high transition on LD allows the Latch B input data to flow through and update the DACs with the EEPROM bank selected by S0/S1. A high-to-low transition on LD latches the selected DAC data into Latch B. SOFT S0/S1 Bit-Controlled Bank-Updating Mode This mode also features banked operation with the only difference being how the desired bank is selected. In particular, the bank is selected using the SOFT S0 (bit 0) and SOFT S1 (bit 1) bits contained in the Soft S0/S1 register (40h). The S0 and S1 pins are ignored in this mode. Table 2 illustrates the relationship between the bit settings and the selected bank. For example, if SOFT S0 and SOFT S1 are written to zero, the first bank (Bank A) is selected. Once a bank is selected, the timing of the DAC update depends on the state of the LD pin. When LD is high, Latch B functions as a flowthrough latch, so the amplifier responds asynchronously to changes in the state of the SOFT S0/S1 bits. These are changed by an I2C write. Conversely, when LD is low, Latch B functions as a latch, holding its previous data. A low-to-high transition on LD allows the Latch B input data to flow through and update the DACs with the EEPROM bank selected by the SOFT S0/S1 bits. A high-to-low transition on LD latches the selected DAC data into Latch B. Because the Soft S0/S1 register is SRAM, subsequent power ups result in the SOFT S0 and SOFT S1 bits being cleared to 0 and, hence, powering up to Bank A. I2C Individual Channel-Control Mode In this mode the I2C master writes directly to individual channel Latch A registers to update a single DAC (i.e., not banked). The Latch A registers are SRAM and not EEPROM. This allows an unlimited number of write cycles as well as quicker write times since t W only applies to EEPROM writes. As shown in the Memory Table 2. Bank Selection Table BIT OR PIN S1 S0 VCOM CHANNEL GAMMA CHANNELS S0/S1 Pin-Controlled Bank Updating (Factory Default) 0 0 VCOM Bank A GM1–GM14 Bank A 0 1 VCOM Bank B GM1–GM14 Bank B 1 S0/S1 Bit-Controlled Bank Updating 1 0 VCOM Bank C GM1–GM14 Bank C 1 1 VCOM Bank D GM1–GM14 Bank D X I2C Individual Channel Control MODE ______________________________________________________________________________________ 11 DS3514 Detailed Description DS3514 I2C Gamma and VCOM Buffer with EEPROM Map , the Latch A registers for each channel are accessed through memory addresses 00–1Ch. Then, like the other modes, the LD pin determines when the DACs are updated. If the LD signal is high, Latch B is flow-through and the DAC is updated immediately. If LD is low, Latch B is loaded from Latch A after a low-tohigh transition on the LD pin. This latter method allows the timing of the DAC update to be controlled by an external signal pulse. VCOM/Gamma Channel Outputs As illustrated in the Block Diagram, the gamma channel outputs are equivalent to a 10-bit digital potentiometer (DAC) with a buffered output. The VCOM channel is equivalent to an 8-bit digital potentiometer (DAC) with a Table 3a. VCOM DAC Voltage/Data Relationship for Selected Codes SETTING (HEX) VCOM OUTPUT VOLTAGE 00h VRL 01h VRL + (1/255) x (VRH - VRL) 02h VRL + (2/255) x (VRH - VRL) 03h VRL + (3/255) x (VRH - VRL) 0Fh VRL + (15/255) x (VRH - VRL) 3Fh VRL + (63/255) x (VRH - VRL) 7Fh VRL + (127/255) x (VRH - VRL) FDh VRL + (253/255) x (VRH - VRL) FEh VRL + (254/255) x (VRH - VRL) FFh VRH buffered output. The V COM channel’s digital potentiometer is composed of 255 equal resistive elements. The relationship between output voltage and DAC setting is illustrated in Table 3a. Unlike the gamma channels, the V COM channel is capable of outputting a range of voltages including both references (VRH and VRL). Each of the gamma channel digital potentiometers, on the other hand, are composed of 1024 equal resistive elements. The extra resistive element prohibits one of the rails from being reached. In particular, gamma channel outputs GM1–GM7 can span from (and including) GLL to 1 LSB away from GLM. Likewise, gamma channel outputs GM8–GM14 span from (and including) GHM to 1 LSB away from GHH. The relationship between output voltage and DAC setting for the gamma channels are also illustrated in Table 3b. Standby Mode Standby mode (not to be confused with the three DS3514 operating modes) can be used to minimize current consumption. Standby mode is entered by setting the STANDBY bit, which is the MSB of register 41h. The VCOM and gamma outputs are placed in a highimpedance state. Current drawn from the VDD supply in this state is specified as IDDQ. The DS3514 continues to respond to I2C commands, and thus draws some current from VCC when I2C activity is occurring. When the I2C interface is inactive, current drawn from the VCC supply is specified as ICCQ. Thermal Shutdown As a safety feature, the DS3514 goes into a thermal shutdown state if the junction temperature ever reaches Table 3b. Gamma DAC Voltage/Data Relationship for Selected Codes 12 SETTING (HEX) GM1–GM7 OUTPUT VOLTAGE GM8–GM14 OUTPUT VOLTAGE 000h GLM + (0 + 1) x ((GLL - GLM)/1024) GHM + (0 + 1) x ((GHH - GHM)/1024) 001h GLM + (1 + 1) x ((GLL - GLM)/1024) GHM + (1 + 1) x ((GHH - GHM)/1024) 002h GLM + (2 + 1) x ((GLL - GLM)/1024) GHM + (2 + 1) x ((GHH - GHM)/1024) 003h GLM + (3 + 1) x ((GLL - GLM)/1024) GHM + (3 + 1) x ((GHH - GHM)/1024) 00Fh GLM + (15 + 1) x ((GLL - GLM)/1024) GHM + (15 + 1) x ((GHH - GHM)/1024) 03Fh GLM + (63 + 1) x ((GLL - GLM)/1024) GHM + (63 + 1) x ((GHH - GHM)/1024) 07Fh GLM + (127 + 1) x ((GLL - GLM)/1024) GHM + (127 + 1) x ((GHH - GHM)/1024) 0FFh GLM + (255 + 1) x ((GLL - GLM)/1024) GHM + (255 + 1) x ((GHH - GHM)/1024) 3FDh GLM + (1021 + 1) x ((GLL - GLM)/1024) GHM + (1021 + 1) x ((GHH - GHM)/1024) 3FEh GLM + (1022 + 1) x ((GLL - GLM)/1024) GHM + (1022 + 1) x ((GHH - GHM)/1024) 3FFh GLL GHH ______________________________________________________________________________________ I2C Gamma and VCOM Buffer with EEPROM Slave Address Byte and Address Pin The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 5). The DS3514’s slave address is determined by the state of the A0 pin. This pin allows up to two devices to reside on the same I2C bus. Connecting A0 to GND results in a 0 in the corresponding bit position in the slave address. Conversely, connecting A0 to VCC results in a 1 in the corresponding bit position. For example, the DS3514’s slave address byte is C0h when A0 is grounded. I2C communication is described in detail in the I2C Serial Interface Description section. Memory Organization Memory Description The list of registers/memory contained in the DS3514 is shown in the Memory Map section. Also shown for each of the registers is the memory type, accessibility, LSB MSB 1 DS3514 or exceeds +150°C. In this state, the VCOM buffer is disabled (output goes high impedance) until the junction temperature falls below +150°C. 1 0 0 0 0 A0 R/W SLAVE ADDRESS* *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0. Figure 5. DS3514 Slave Address Byte as well as the power-up default values for volatile locations and factory-programmed defaults for the nonvolatile locations. Additional information regarding reading and writing the memory is located in the I2C Serial Interface Description section. Memory Map ADDRESS NAME DESCRIPTION TYPE MEMORY OR COMMAND I2C ACCESS (HEX) (DEC) Latch A for VCOM Ch 0h 0 8-Bit I2C Data for VCOM DAC Volatile R/W Latch A for GM1 Ch 2h, 3h 2, 3 10-Bit I2C Data for GM1 DAC Volatile R/W Latch A for GM2 Ch 4h, 5h 4, 5 10-Bit I2C Data for GM2 DAC Volatile R/W Latch A for GM3 Ch 6h, 7h 6, 7 10-Bit I2C Data for GM3 DAC Volatile R/W Latch A for GM4 Ch 8h, 9h 8, 9 10-Bit I2C Data for GM4 DAC Volatile R/W Latch A for GM5 Ch Ah, Bh 10, 11 10-Bit I2C Data for GM5 DAC Volatile R/W Latch A for GM6 Ch Ch, Dh 12, 13 10-Bit I2C Data for GM6 DAC Volatile R/W Latch A for GM7 Ch Eh, Fh 14, 15 10-Bit I2C Data for GM7 DAC Volatile R/W Latch A for GM8 Ch 10h, 11h 16, 17 10-Bit I2C Data for GM8 DAC Volatile R/W Latch A for GM9 Ch 12h, 13h 18, 19 10-Bit I2C Data for GM9 DAC Volatile R/W Latch A for GM10 Ch 14h, 15h 20, 21 10-Bit I2C Data for GM10 DAC Volatile R/W Volatile R/W Volatile R/W Latch A for GM11 Ch 16h, 17h 22, 23 10-Bit I2C Data for GM11 DAC Latch A for GM12 Ch 18h, 19h 24, 25 10-Bit I2C Data for GM12 DAC ______________________________________________________________________________________ 13 I2C Gamma and VCOM Buffer with EEPROM DS3514 Memory Map (continued) ADDRESS NAME 14 DESCRIPTION TYPE MEMORY OR COMMAND I2C ACCESS (HEX) (DEC) Latch A for GM13 Ch 1Ah, 1Bh 26, 27 10-Bit I2C Data for GM13 DAC Volatile R/W Latch A for GM14 Ch 1Ch, 1Dh 28, 29 10-Bit I2C Data for GM14 DAC Volatile R/W Reserved 1Eh–3Fh 30–63 — — — Soft S1/S0 40h 64 Software Bank Select Byte (Bits 1:0) Volatile R/W Standby 41h 65 Shutdown Byte Volatile R/W Reserved 42h–47h 66–71 — — — Control 48h 72 Control Register (see Table 1) NV R/W Reserved 49h 73 — — — Status Bits Status Bits 4Ah 74 Reserved 4Bh–4Fh 75–79 VCOM1–VCOM4 50h, 52h, 54h, 56h GM1 GDAT1–GDAT4 58h–5Fh 88–95 GM1 EEPROM Data (Four 10-Bit Words) NV R/W GM2 GDAT1–GDAT4 60h–67h 96–103 GM2 EEPROM Data (Four 10-Bit Words) NV R/W GM3 GDAT1–GDAT4 68h–6Fh 104–111 GM3 EEPROM Data (Four 10-Bit Words) NV R/W GM4 GDAT1–GDAT4 70h–77h 112–119 GM4 EEPROM Data (Four 10-Bit Words) NV R/W GM5 GDAT1–GDAT4 78h–7Fh 120–127 GM5 EEPROM Data (Four 10-Bit Words) NV R/W GM6 GDAT1–GDAT4 80h–87h 128–135 GM6 EEPROM Data (Four 10-Bit Words) NV R/W GM7 GDAT1–GDAT4 88h–8Fh 136–143 GM7 EEPROM Data (Four 10-Bit Words) NV R/W GM8 GDAT1–GDAT4 90h–97h 144–151 GM8 EEPROM Data (Four 10-Bit Words) NV R/W — 80, 82, 84, VCOM EEPROM Data (Four 8-Bit Words) 86 Status R — — NV R/W GM9 GDAT1–GDAT4 98h–9Fh 152–159 GM9 EEPROM Data (Four 10-Bit Words) NV R/W GM10 GDAT1–GDAT4 A0h–A7h 160–167 GM10 EEPROM Data (Four 10-Bit Words) NV R/W GM11 GDAT1–GDAT4 A8h–AFh 168–175 GM11 EEPROM Data (Four 10-Bit Words) NV R/W GM12 GDAT1–GDAT4 B0h–B7h 176–183 GM12 EEPROM Data (Four 10-Bit Words) NV R/W GM13 GDAT1–GDAT4 B8h–BFh 184–191 GM13 EEPROM Data (Four 10-Bit Words) NV R/W GM14 GDAT1–GDAT4 C0h–C7h 192–198 GM14 EEPROM Data (Four 10-Bit Words) NV R/W Reserved C8h–FFh 200–255 — — — ______________________________________________________________________________________ I2C Gamma and VCOM Buffer with EEPROM FACTORY DEFAULT 00h MEMORY TYPE Volatile 40h x x x x x x SOFT S1 BIT 7 SOFT S0 BIT 0 Bits 7:2 Reserved Bits 1:0 These bits are used when in SOFT S0/S1 Bit-Controlled Bank-Updating mode (MODE1 = 0, MODE0 = 1) SOFT S1, SOFT S0: 00 = Selects VCOM and GM1–GM14 Bank A 01 = Selects VCOM and GM1–GM14 Bank B 10 = Selects VCOM and GM1–GM14 Bank C 11 = Selects VCOM and GM1–GM14 Bank D Standby Register 41h: Standby Mode Enable FACTORY DEFAULT 00h MEMORY TYPE Volatile 41h STANDBY x BIT 7 Bit 7 STANDBY: 0 = Standby mode disabled 1 = Standby mode enabled Bits 6:1 Reserved x x x x x x BIT 0 ______________________________________________________________________________________ 15 DS3514 Detailed Register Descriptions Soft S0/S1 Register 40h: SOFT S1/S0 Bits DS3514 I2C Gamma and VCOM Buffer with EEPROM Control Register 48h: Control Register (CR) FACTORY DEFAULT 20h MEMORY TYPE NV 48h x x BIAS1 BIAS0 x x MODE1 BIT 7 MODE0 BIT 0 Bits 7:6 Reserved Bits 5:4 VCOM and Gamma Bias Current Control Bits (BIAS[1:0]): 00 = 60% 01 = 80% 10 = 100% (default) 11 = 150% Bits 3:2 Reserved Bits 1:0 DS3514 Mode (MODE[1:0]): 00 = S0/S1 pins are used to select the desired bank (A–D) (default). 01 = SOFT S0/S1 (bits) are used to select the desired bank (A–D). 1X = Latch A is used to control the DACs. Status Bits Register 4Ah: Real-Time Indicator of Logic State on LD, S1, and S0 Pins FACTORY DEFAULT — MEMORY TYPE Read Only 4Ah LD x x x x x S1 BIT 7 S0 BIT 0 GDATx Register: EEPROM Data for the Gamma Channels This is an example of how the bits are arranged for a typical GDATx memory location. GDATx has 10 bits that are arranged in two consecutive bytes. The following example shows the arrangement for GM1 GDAT1 (58h–59h). This arrangement is applicable for all the EEPROM data for all gamma channels. FACTORY DEFAULT 8000h MEMORY TYPE NV 58h GDAT[9] GDAT[8] GDAT[7] GDAT[6] GDAT[5] GDAT[4] GDAT[3] GDAT[2] 59h GDAT[1] GDAT[0] x x x x x x BIT 7 16 ______________________________________________________________________________________ BIT 0 I2C Gamma and VCOM Buffer with EEPROM I2C Definitions The following terminology is commonly used to describe I2C data transfers. (See Figure 4 and the I2C Electrical Characteristics for additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave devices: Slave devices send and receive data at the master’s request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. STOP condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by transmitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgment is read using the bit-read definition. Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave will return control of SDA to the master. Slave address byte: Each slave on the I 2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS3514’s slave address is determined by the state of the A0 address pin as shown in Figure 5. An address pin connected to GND results in a 0 in the corresponding bit position in the slave address. Conversely, an address pin connected to V CC results in a 1 in the corresponding bit position. When the R/W bit is 0 (such as in C0h), the master is indicating it will write data to the slave. If R/W is set to a 1 (C1h in this case), the master is indicating that it wants to read from the slave. If an incorrect (nonmatching) slave address is written, the DS3514 assumes the master is communicating with another I 2 C device and ignores the communication until the next START condition is sent. Memory address: During an I2C write operation to the DS3514, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. ______________________________________________________________________________________ 17 DS3514 I2C Serial Interface Description DS3514 I2C Gamma and VCOM Buffer with EEPROM I2C Communication Writing a single byte to a slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave’s acknowledgment during all byte-write operations. When writing to the DS3514 (and if LD = 1), the DAC adjusts to the new setting once it has acknowledged the new data that is being written, and the EEPROM (used to make the setting nonvolatile) is written following the STOP condition at the end of the write command. Writing multiple bytes to a slave: To write multiple bytes to a slave in one transaction, the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a STOP condition. The DS3514 can write 1 to 8 bytes (one page or row) in a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). The first page begins at address 00h and subsequent pages begin at multiples of 8 (08h, 10h, 18h, etc). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrapping around to the beginning of the present row. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM write time to elapse. Then the master can generate a new START condition and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM byte is written, the DS3514 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of 18 this phenomenon by repeatedly addressing the DS3514, which allows communication to continue as soon as the DS3514 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. EEPROM write cycles: The DS3514’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case temperature (hot) as well as at room temperature. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, because requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. Recall that the master must NACK the last byte to inform the slave that no additional bytes will be read. See Figure 6 for I2C communication examples. Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and generates a STOP condition. ______________________________________________________________________________________ I2C Gamma and VCOM Buffer with EEPROM DS3514 TYPICAL I2C WRITE TRANSACTION MSB START 1 LSB 1 0 0 SLAVE ADDRESS* 0 0 A0 R/W MSB SLAVE ACK b7 LSB b6 READ/ WRITE b5 b4 b3 b2 b1 b0 MSB SLAVE ACK b7 LSB b6 b5 b4 REGISTER ADDRESS b3 b2 b1 b0 SLAVE ACK STOP DATA *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0. EXAMPLE I2C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND). C0h 08h OOh A) SINGLE-BYTE WRITE -WRITE LATCH A GM8 TO 00h START 1 1 0 0 0 0 0 0 SLAVE 0 0 0 0 1 0 0 0 ACK B) SINGLE-BYTE READ -READ LATCH A GM2 START 1 1 0 0 0 0 0 0 SLAVE 0 0 0 0 0 0 1 0 SLAVE ACK ACK C) SINGLE-BYTE WRITE -ENTER STANDBY MODE START 1 1 0 0 0 0 0 0 D) TWO-BYTE WRITE - WRITE 10h AND 11h TO 80h START 1 1 0 0 0 0 0 0 E) TWO-BYTE READ - READ 10h AND 11h START 1 1 0 0 0 0 0 0 C0h SLAVE 0 0 0 0 0 0 0 0 ACK 02h C0h 01000 001 SLAVE ACK 00010 000 SLAVE ACK 00010 000 C0h REPEATED START DATA 1 1 0 0 0 0 0 1 SLAVE ACK I/O STATUS MASTER NACK STOP 80h SLAVE ACK 1000 0 0 0 0 SLAVE ACK 1000 0 0 0 0 SLAVE ACK REPEATED START 10h C0h STOP C1h 41h SLAVE ACK SLAVE ACK SLAVE ACK STOP 80h 80h SLAVE ACK 1000 0 0 0 0 C1h 10h 1100 0 0 0 1 SLAVE ACK STOP DATA SLAVE ACK DATA MASTER ACK MASTER NACK STOP Figure 6. I2C Communication Examples Applications Information Power-Supply Decoupling To achieve the best results when using the DS3514, decouple all the power-supply pins (VCC and VDD) with a 0.01µF or 0.1µF capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. SDA and SCL Pullup Resistors SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I 2 C Electrical Characteristics are within specification. A typical value for the pullup resistors is 4.7kΩ. ______________________________________________________________________________________ 19 I2C Gamma and VCOM Buffer with EEPROM DS3514 Typical Operating Circuit 15V 14.8V 8V 7V 0.2V VDD GHH GHM GLM GLL 14 5V VCC SCL SDA I2C MASTER SOURCE DRIVER GM1 GM2 GM3 GM4 GM5 GM6 GM7 DS3514 S0 S1 LD GM8 GM9 GM10 GM11 GM12 GM13 GM14 A0 GND VRH VRL 13V 2V VCOM 36 35 34 33 32 31 30 29 28 27 26 25 GM1 GM14 37 24 GLM 38 23 VDD GLL 39 22 GND GHM 40 21 GND GHH 41 20 VCAP GND 42 19 GND VDD 43 18 GND VCOM 44 17 VCC A0 45 16 SCL N.C. 46 15 SDA VCC 47 14 LD N.C. 48 13 S0 DS3514 *EP 9 10 11 12 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFN-EP T4877M+6 21-0144 S1 8 GND N.C. 7 N.C. N.C. 6 N.C. N.C. 5 VRL 4 VRH 3 VDD 2 N.C. 1 N.C. + Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. GM2 GM3 GM4 GM5 GM6 GM7 GM8 GM9 GM10 GM12 GM13 GM11 Pin Configuration TOP VIEW LCD THIN QFN (7mm × 7mm) *EXPOSED PAD. 20 ______________________________________________________________________________________ I2C Gamma and VCOM Buffer with EEPROM REVISION NUMBER REVISION DATE 0 9/08 1 10/08 DESCRIPTION PAGES CHANGED Initial release. — Changed the maximum VCC supply current (lCC) specification from 0.5mA to 0.6mA. 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. DS3514 Revision History