19-2626; Rev 0; 10/02 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP Features ♦ -3dB Bandwidth: >300MHz ♦ Low 15pF On-Channel Capacitance ♦ Single-Supply Operation from +1.8V to +5.5V ♦ 20Ω RON (max) Switch 0.4Ω (max) RON Match (+3.0V Supply) 1.2Ω (max) RON Flatness (+3.0V Supply) ♦ Rail-to-Rail® Signal Handling ♦ High Off-Isolation: -55dB (10MHz) ♦ Low Crosstalk: -80dB (10MHz) ♦ Low Distortion: 0.03% ♦ +1.8V CMOS-Logic Compatible Applications ♦ <0.5nA Leakage Current at +25°C Cell Phones Battery-Operated Equipment Ordering Information Audio/Video-Signal Routing Low-Voltage Data-Acquisition Systems TEMP RANGE PIN/BUMPPACKAGE MAX4719EUB -40°C to +85°C 10 µMAX MAX4719EBC-T* -40°C to +85°C 12 UCSP-12 PART Sample-and-Hold Circuits PDAs TOP MARK — ABJ Note: UCSP package requires special solder temperature profile described in the Absolute Maximum Ratings section. *UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and environment. See the UCSP reliability notice in the UCSP Reliability section of this data sheet for more information. UCSP is a trademark of Maxim Integrated Products, Inc. Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd. Pin Configurations/Functional Diagrams/Truth Table TOP VIEW MAX4719 (BUMP SIDE DOWN) MAX4719 GND NC1 C1 B1 A1 IN1 C2 A2 IN2 COM1 C3 A3 COM2 NO1 C4 B4 V+ UCSP A4 MAX4719 NC2 NO2 V+ 1 IN_ NO_ NC_ 0 OFF ON 1 ON OFF SWITCHES SHOWN FOR LOGIC "0" INPUT 10 NO2 NO1 2 9 COM2 COM1 3 8 IN2 IN1 4 7 NC2 NC1 5 6 GND µMAX ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX4719 General Description The MAX4719 low-voltage, low on-resistance (RON), dual single-pole/double throw (SPDT) analog switch operates from a single +1.8V to +5.5V supply. The MAX4719 features 20Ω RON (max) with 1.2Ω flatness and 0.4Ω matching between channels. The switch offers break-before-make switching (1ns) with tON <80ns and tOFF <40ns at +2.7V. The digital logic inputs are +1.8V logic compatible with a +2.7V to +3.6V supply. The switch is packaged in a chip-scale package (UCSP™), significantly reducing the required PC board area. The chip occupies only a 2.0mm ✕ 1.50mm area and has a 4 ✕ 3 bump array with a bump pitch of 0.5mm. The MAX4719 is also available in a 10-pin µMAX package. MAX4719 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP ABSOLUTE MAXIMUM RATINGS (All Voltages Referenced to GND) V+, IN_...................................................................-0.3V to +6.0V COM_, NO_, NC_ (Note 1) ...........................-0.3V to (V+ + 0.3V) Continuous Current COM_, NO_, NC_ ...........................±100mA Peak Current COM_, NO_, NC_ (pulsed at 1ms, 10% duty cycle)................................±200mA Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW 12-Bump UCSP (derate 11.4mW/°C above +70°C) ....909mW ESD Method 3015.7 ...............................................................2kV Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Bump Temperature (soldering) (Note 2) Infrared (15s) ...............................................................+220°C Vapor Phase (60s) .......................................................+215°C Note 1: Signals on COM_, NO_, or NC_ exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating. Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recommended in the industry standard specification, JEDEC 020A, paragraph 7.6, table 3 for IR/VPR and convection reflow. Preheating is required. Hand or wave soldering is not allowed. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS—Single +3V Supply (V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V, TA = +25°C, unless otherwise noted.) (Notes 3, 4) PARAMETER Analog Signal Range SYMBOL CONDITIONS VCOM_, VNO_, VNC_ TA MIN TMIN to TMAX 0 TYP MAX UNITS V+ V ANALOG SWITCH +25°C On-Resistance (Note 5) RON V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.5V ∆RON V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.5V 14 TMIN to TMAX 25 +25°C On-Resistance Match Between Channels (Notes 5, 6) 0.15 TMIN to TMAX RFLAT(ON) V+ = 2.7V, ICOM_ = 10mA; VNO_ or VNC_ = 1.0V, 1.5V, 2.0V NO_, NC_ Off-Leakage Current (Note 8) INO_(OFF), INC_(OFF) V+ = 3.6V, VCOM_ = 0.3V, 3.3V; VNO_ or VNC_ = 3.3V, 0.3V COM_ On-Leakage Current (Note 8) ICOM_(ON) V+ = 3.6V, VCOM_ = 0.3V, 3.3V; VNO_ or VNC_ = 0.3V, 3.3V, or floating tON VNO_, VNC_ = 1.5V; RL = 300Ω, CL = 35pF, Figure 1 0.6 TMIN to TMAX +25°C -0.5 -1 +25°C -1 TMIN to TMAX -2 0.01 Ω +0.5 +1 0.01 Ω 1.2 1.5 TMIN to TMAX Ω 0.4 0.5 +25°C On-Resistance Flatness (Note 7) 20 nA +1 +2 nA DYNAMIC CHARACTERISTICS +25°C Turn-On Time 2 40 TMIN to TMAX _______________________________________________________________________________________ 80 100 ns 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP (V+ = +2.7V to +3.6V, VIH = +1.4V, VIL = +0.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +3.0V, TA = +25°C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN +25°C Turn-Off Time tOFF VNO_, VNC_ = 1.5V; RL = 300Ω, CL = 35pF, Figure 1 tBBM VNO_, VNC_ = 1.5V; RL = 300Ω, CL = 35pF, Figure 2 Charge Injection Q Off-Isolation VISO Crosstalk (Note 9) VCT VGEN = 2V, RGEN = 0Ω; CL = 1.0nF, Figure 3 f = 10MHz; VNO_, VNC_ = 1VP-P; RL = 50Ω, CL = 5pF, Figure 4 40 50 TMIN to TMAX UNITS ns 8 ns 1 +25°C 18 pC -55 +25°C dB f = 1MHz; VNO_, VNC_ = 1VP-P; RL = 50Ω, CL = 5pF, Figure 4 f = 10MHz; VNO_, VNC_ = 1VP-P; RL = 50Ω, CL = 5pF, Figure 4 MAX 20 TMIN to TMAX +25°C Break-Before-Make Time Delay (Note 8) TYP -80 -80 +25°C dB f = 1MHz; VNO_, VNC_ = 1VP-P; RL = 50Ω, CL = 5pF, Figure 4 -110 On-Channel -3dB Bandwidth BW Signal = 0dBm, RL = 50Ω; CL = 5pF, Figure 4 +25°C 300 MHz Total Harmonic Distortion THD VCOM = 2VP-P, RL = 600Ω +25°C 0.03 % +25°C 9 pF +25°C 20 pF NO_, NC_ Off-Capacitance Switch On-Capacitance CNO_(OFF) f = 1MHz, Figure 5 CNC_(OFF) CON f = 1MHz, Figure 5 DIGITAL I/O Input Logic High Voltage VIH TMIN to TMAX Input Logic Low Voltage VIL TMIN to TMAX Input Leakage Current IIN V+ = +3.6V, VIN_ = 0V or 5.5V 1.4 V 0.5 V TMIN to TMAX -100 +100 nA TMIN to TMAX 1.8 5.5 V 1 µA POWER SUPPLY Power-Supply Range V+ Supply Current I+ V+ = +5.5V, VIN_ = 0V or V+ TMIN to TMAX _______________________________________________________________________________________ 3 MAX4719 ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued) MAX4719 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP ELECTRICAL CHARACTERISTICS—Single +5V Supply (V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V, TA = +25°C, unless otherwise noted.) (Notes 3, 4) PARAMETER Analog Signal Range SYMBOL CONDITIONS VCOM_, VNO_, VNC_ TA MIN TMIN to TMAX 0 TYP MAX UNITS V+ V ANALOG SWITCH +25°C On-Resistance (Note 5) RON V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 3.5V ∆RON V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 3.5V 12 TMIN to TMAX 25 +25°C On-Resistance Match Between Channels (Notes 5, 6) 0.15 TMIN to TMAX RFLAT(ON) V+ = 4.2V, ICOM_ = 10mA; VNO_ or VNC_ = 1.0V, 2.0V, 4.5V NO_, NC_ Off-Leakage Current (Note 8) INO_(OFF), INC_(OFF) V+ = 5.5V; VCOM_ = 1.0V, 4.5V; VNO_ or VNC_ = 4.5V, 1.0V COM_ On-Leakage Current (Note 8) ICOM_(ON) V+ = 5.5V, VCOM_ = 1.0V, 4.5V; VNO_ or VNC_ = 1.0V, 4.5V, or floating tON VNO_, VNC_ = 3.0V; RL = 300Ω, CL = 35pF, Figure 1 tOFF VNO_, VNC_ = 3.0V; RL = 300Ω, CL = 35pF, Figure 1 tBBM VNO_, VNC_ = 3.0V; RL = 300Ω, CL = 35pF, Figure 2 0.4 TMIN to TMAX -0.5 TMIN to TMAX -1 +25°C -1 TMIN to TMAX -2 +0.01 Ω +0.5 +1 +0.01 Ω 1 1.2 +25°C Ω 0.4 0.5 +25°C On-Resistance Flatness (Note 7) 20 nA +1 +2 nA DYNAMIC CHARACTERISTICS +25°C Turn-On Time 30 TMIN to TMAX 100 +25°C Turn-Off Time 20 TMIN to TMAX ns 40 50 +25°C Break-Before-Make Time Delay (Note 8) 80 ns 8 TMIN to TMAX 1 2.0 ns DIGITAL I/O Input Logic High Voltage VIH TMIN to TMAX Input Logic Low Voltage VIL TMIN to TMAX Input Leakage Current IIN 4 V+ = 5.5V, VIN_ = 0V or V+ TMIN to TMAX -0.1 _______________________________________________________________________________________ V 0.8 V +0.1 µA 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP (V+ = +4.2V to +5.5V, VIH = +2.0V, VIL = +0.8V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at V+ = +5.0V, TA = +25°C, unless otherwise noted.) (Notes 3, 4) PARAMETER SYMBOL CONDITIONS TA MIN TMIN to TMAX 1.8 TYP MAX UNITS 5.5 V 1 µA POWER SUPPLY Power-Supply Range V+ Supply Current I+ Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: TMIN to TMAX V+ = 5.5V, VIN_ = 0V or V+ UCSP parts are 100% tested at +25°C only, and guaranteed by design over the specified temperature range. µMAX parts are 100% tested at TMAX and guaranteed by design over the specified temperature range. The algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive value is a maximum. Guaranteed by design for UCSP parts. ∆RON = RON(MAX) - RON(MIN). Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. Guaranteed by design. Between any two switches. Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) ON-RESISTANCE vs. VCOM 14 13 12 V+ = 4.2V 12 TA = -40°C 1 2 3 VCOM (V) 4 11 TA = +25°C TA = +25°C TA = -40°C V+ = 5V 0 TA = +85°C 13 12 11 10 V+ = 5V 14 RON (Ω) V+ = 2.5V TA = +85°C 14 RON (Ω) RON (Ω) 18 V+ = 3V ON-RESISTANCE vs. VCOM 15 MAX4719 toc02 MAX4719 toc01 V+ = 1.8V 16 15 MAX4719 toc03 ON-RESISTANCE vs. VCOM 20 10 5 10 0 0.5 1.0 1.5 VCOM (V) 2.0 2.5 3.0 0 1 2 3 4 5 VCOM (V) _______________________________________________________________________________________ 5 MAX4719 ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) LEAKAGE CURRENT vs. TEMPERATURE 500 V+ = 5V 600 300 LEAKAGE CURRENT (pA) COM ON-LEAKAGE COM OFF-LEAKAGE 100 40 CHARGE INJECTION (pC) V+ = 3V CHARGE INJECTION vs. VCOM 50 MAX4719 toc05 MAX4719 toc04 800 COM ON-LEAKAGE 400 COM OFF-LEAKAGE 200 0 -40 -15 10 35 10 35 60 85 0 1 2 SUPPLY CURRENT vs. LOGIC LEVEL 80 SUPPLY CURRENT (µA) 4 V+ = 5V 3 2 V+ = 3V 1 MAX4719 toc08 100 MAX4719 toc07 5 3 VCOM (V) SUPPLY CURRENT vs. TEMPERATURE 6 V+ = 5V 60 40 V+ = 3V 20 0 0 -40 -15 10 35 85 60 0 1 2 3 LOGIC LEVEL (V) LOGIC THRESHOLD vs. SUPPLY VOLTAGE TURN-ON/OFF TIME vs. SUPPLY VOLTAGE 100 MAX4719 toc09 2.0 1.6 5 4 TEMPERATURE (°C) MAX4719 toc10 SUPPLY CURRENT (nA) CL = 1nF V+ = 3V 20 TEMPERATURE (°C) TEMPERATURE (°C) 80 VTH+ tON/tOFF (ns) LOGIC THRESHOLD (V) 30 0 -15 -40 85 60 CL = 1nF V+ = 5V 10 -200 -100 MAX4719 toc06 LEAKAGE CURRENT vs. TEMPERATURE 700 LEAKAGE CURRENT (pA) MAX4719 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP 1.2 VTH0.8 60 tON 40 20 0.4 tOFF 0 0 1.5 2.0 2.5 3.0 3.5 4.0 SUPPLY VOLTAGE (V) 6 4.5 5.0 5.5 1.5 2.5 3.5 4.5 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 5.5 4 5 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP V+ = 3V/5V 0 ON-LOSS (dB) tON/tOFF (ns) -20 40 30 20 -60 V+ = 3V RL = 600Ω ON-LOSS -40 THD (%) tON, V+ = 5.0V 1 MAX4719 toc12 tON, V+ = 3.0V 20 MAX4719 toc11 60 50 TOTAL HARMONIC DISTORTION vs. FREQUENCY FREQUENCY RESPONSE MAX4719 toc13 TURN-ON/OFF TIME vs. TEMPERATURE OFF-ISOLATION 0.1 -80 -100 10 tOFF, V+ = 3.0V tOFF, V+ = 5.0V 0 -40 -15 10 35 85 60 CROSSTALK -120 -140 0.0001 0.01 0.01 TEMPERATURE (°C) FREQUENCY (MHz) Pin Description PIN 1 NAME FUNCTION UCSP µMAX A1 7 NC2 Analog Switch 2—Normally Closed Terminal A2 8 IN2 Digital Control Input for Analog Switch 2 A3 9 COM2 A4 10 NO2 B1 6 GND B4 1 V+ C1 5 NC1 Analog Switch 1—Normally Closed Terminal C2 4 IN1 Digital Control Input for Analog Switch 1 C3 3 COM1 C4 2 NO1 Analog Switch 2—Common Terminal Analog Switch 2—Normally Open Terminal Ground Positive-Supply Voltage Input Analog Switch 1—Common Terminal Analog Switch 1—Normally Open Terminal 100 10 100 1k 10k 100k FREQUENCY (Hz) Detailed Description The MAX4719 high-speed, low-voltage, 20Ω RON, dual SPDT analog switch operates from a single +1.8V to +5.5V supply. The switch features break-before-make switching operation and fast switching speeds (tON = 80ns (max), tOFF = 40ns (max)). Applications Information Digital Control Inputs The MAX4719 logic inputs accept up to +5.5V regardless of supply voltage. For example, with a +3.3V supply, IN_ can be driven low to GND and high to +5.5V allowing for mixing of logic levels in a system. Driving the control logic inputs rail-to-rail minimizes power consumption. For a +3V supply voltage, the logic thresholds are 0.5V (low) and 1.4V (high); for a +5V supply voltage, the logic thresholds are 0.8V (low) and 2.0V (high). Analog Signal Levels The on-resistance of the MAX4719 changes very little for analog input signals across the entire supply voltage range (see the Typical Operating Characteristics). The switches are bidirectional, so the NO_, NC_, and COM_ pins can be either inputs or outputs. _______________________________________________________________________________________ 7 MAX4719 Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MAX4719 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP Power-Supply Sequencing and Overvoltage Protection Caution: Do not exceed the absolute maximum ratings because stresses beyond the listed ratings may cause permanent damage to the device. Proper power-supply sequencing is recommended for all CMOS devices. Always apply V+ before applying analog signals, especially if the analog signal is not current-limited. UCSP Package Considerations For general UCSP package information and PC layout considerations, please refer to the Maxim Application Note (Wafer-Level Chip-Scale Package). usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Information on Maxim’s qualification plan, test data, and recommendations are detailed in the UCSP application note, which can be found on Maxim’s website at www.maxim-ic.com. UCSP Reliability The chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and Chip Information TRANSISTOR COUNT: 235 PROCESS: BiCMOS Test Circuits/Timing Diagrams MAX4719 V+ VN_ LOGIC INPUT V+ COM_ NO_ OR NC_ 50% VIL VOUT RL 300Ω CL 35pF t OFF IN_ VOUT GND LOGIC INPUT SWITCH OUTPUT ( 0.9 x V0UT 0.9 x VOUT 0V t ON CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL RL + RON VOUT = VN_ t r < 5ns t f < 5ns VIH LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES THAT HAVE THE OPPOSITE LOGIC SENSE. ) Figure 1. Switching Time V+ MAX4719 LOGIC INPUT V+ VN_ NC_ RL 300Ω IN_ LOGIC INPUT 50% VIL VOUT COM_ NO_ VIH CL 35pF GND 0.9 x VOUT VOUT tBBM CL INCLUDES FIXTURE AND STRAY CAPACITANCE. Figure 2. Break-Before-Make Interval 8 _______________________________________________________________________________________ 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP V+ ∆VOUT MAX4719 V+ RGEN VOUT COM_ NC_ OR NO_ VOUT IN OFF CL V GEN GND OFF ON IN_ IN VIL TO VIH ON OFF OFF Q = (∆V OUT )(C L ) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 3. Charge Injection +5V 10nF V OFF-ISOLATION = 20log OUT VIN NETWORK ANALYZER 0V OR V+ V+ IN_ 50Ω VIN COM1 V ON-LOSS = 20log OUT VIN 50Ω MAX4719 NC1 VOUT NO1* 50Ω GND MEAS 50Ω MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED. REF V CROSSTALK = 20log OUT VIN 50Ω *FOR CROSSTALK THIS PIN IS NO2. NC2 AND COM2 ARE OPEN. Figure 4. On-Loss, Off-Isolation, and Crosstalk 10nF V+ V+ COM_ MAX4719 IN CAPACITANCE METER f = 1MHz NC_ or NO_ VIL OR VIH GND Figure 5. Channel Off/On-Capacitance _______________________________________________________________________________________ 9 MAX4719 Test Circuits/Timing Diagrams (continued) Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 12L, UCSP 4x3.EPS MAX4719 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP 10 ______________________________________________________________________________________ 20Ω, 300MHz Bandwidth, Dual SPDT Analog Switch in UCSP 10LUMAX.EPS e 4X S 10 INCHES 10 H ÿ 0.50±0.1 0.6±0.1 1 1 0.6±0.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 0.114 D2 0.116 0.120 E1 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0∞ 6∞ MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0∞ 6∞ E2 GAGE PLANE A2 c A b D1 A1 α E1 L L1 FRONT VIEW SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 REV. I 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX4719 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)