RENESAS M35075

M35075-XXXFP
REJ03B0180-0110
Rev.1.10
Feb 13, 2006
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M35075-XXXFP is a character pattern display control IC can
display on the CRT display the liquid crystal display and the
plasma display. It uses a silicon gate CMOS process and it
housed in a 24-pin shrink SOP package (M35075-XXXFP).
For M35075-001FP that is a standard ROM version of M35075XXXFP respectively, the character pattern is also mentioned.
CPOUT ← 1
VSS2
SIN/SDA ↔ 6
TCK → 7
P6 ← 8
• Screen composition ................................ 24 characters ✕ 12 lines
• Number of characters displayed ................................... 288 (Max.)
• Character composition ..................................... 12 ✕ 18 dot matrix
• Characters available ..................... ROM character:255 characters
•
•
•
•
•
•
RAM character:8 characters
Character sizes available .................... 4 (vertical) ✕ 2 (horizontal)
Display locations available
Horizontal direction .............................................. 2007 locations
Vertical direction .................................................. 2047 locations
Blinking .................................................................. Character units
Cycle : division of vertical synchronization signal into 32 or 64
Duty : 25%, 50%, or 75%
Data input ............................. By the I2C-BUS serial input function
Coloring for ROM character
Character color ..................................... 8 colors (Character unit)
Background coloring ............................. 8 colors (Character unit)
Border (shadow) coloring ..................... 8 colors (unit of screen /
character unit)
Raster coloring.......................................8 colors (unit of screen)
Blanking for ROM character
Character size blanking
Border size blanking
Matrix-outline blanking
All blanking (all raster area)
• Coloring for RAM character................................8 colors (dot by dot)
• Blanking for RAM character
Character size blanking
Matrix-outline blanking
All blanking (all raster area)
• Output ports
4 shared output ports (toggled between RGB output)
4 dedicated output ports
Display RAM erase function
Display input frequency range ....... FOSC = 20.0MHz to 110.0MHz
Horizontal synchronous input frequency
........................................................ H.sync = 15 kHz to 130 kHz
Display oscillation stop function
<VDD=5V>
Display input frequency range
External clock mode 1 ..................... FOSC = 6.3 MHz to 80.0 MHz
External clock mode 2 ................. FOSC = 20.0 MHz to 110.0 MHz
Internal clock mode ..................... FOSC = 20.0 MHz to 110.0 MHz
Horizontal synchronous input frequency
........................................................ H.sync = 15 kHz to 130 kHz
•
•
•
•
•
•
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 1 of 44
P7 ← 9
VDD1
10
NC
11
NC
12
M35075 - XXXFP
AC → 3
CS → 4
SCK/SCL → 5
FEATURES
24
2
NC
VDD2
23
22 → P5/B
21 → P4
20 → P3/G
19 → P2
18 → P1/R
17 → P0/BLNK0
16 ← BIN
15
VSS1
14 ← VERT
13 ← HOR
Outline 24P2Q
<VDD=3V>
Display input frequency range
External clock mode 1 ........................ FOSC = 6.3 MHz to 40 MHz
Horizontal synchronous input frequency
.......................................................... H.sync = 15 kHz to 60 kHz
•
•
APPLICATION
CRT display, Liquid crystal display, Plasma display
M35075-XXXFP
PIN DESCRIPTION
Pin
Number
Symbol
Input/
Output
Pin name
1
CPOUT
Filter output
Output
2
VSS2
Earthing pin
–
Function
Filter output. Connect loop filter to this pin.
Please connect to GND using circuit earthing pin.
__
3
4
AC
__
CS
Auto-clear input
Input
When “L”, this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor.
Chip select input
Input
<at the 16-bit serial communication>
Chip select pin. Set this pin to "L" level at serial data transfer. Hysteresis input. Built-in
pull-up resistor.
<at the I2C-BUS serial communication>
Set this pin to “H” level.
5
SCK/SCL
Clock input
Input
<at the 16-bit serial communication>
_____
SIN pin serial data is taken in when SCK rises at CS pin "L" level. Hysteresis input.
<at the I2C-BUS serial communication>
SDA pin serial data is taken in synchronized with SCL.
6
SIN/SDA
Data input
Input
Data I/O
I/O
<at the 16-bit serial communication>
This is the pin for serial input of display control register and display RAM data. Hysteresis
input.
<at the I2C-BUS serial communication>
Hysteresis input. This is the pin for serial input of display control register and display
RAM data. Also this pin output acknowledge signal.
7
TCK
External clock
Input
8
P6
Port P6 output
Output
This is the output port.
9
P7
Port P7 output
Output
This is the output port.
10
VDD1
Power pin
–
Please connect to +5V with the power pin.
11
NC
–
–
This is NC pin. Please open this pin.
12
NC
–
–
This is NC pin. Please open this pin.
13
HOR
Horizontal synchronous signal input
Input
This pin inputs the horizontal synchronous signal. Hysteresis input.
14
VERT
Vertical synchronous signal input
Input
This pin inputs the vertical synchronous signal. Hysteresis input.
15
VSS1
Earthing pin
16
BIN
Test pin
17
P0/BLNK0
Port P0 output
Output
This pin can be toggled between port pin output and BLNK0 signal output.
18
P1/R
Port P1 output
Output
This pin can be toggled between port pin output and R signal output.
19
P2
Port P2 output
Output
This is the output port.
20
P3/G
Port P3 output
Output
This pin can be toggled between port pin output and G signal output.
21
P4
Port P4 output
Output
This is the output port.
22
P5/B
Port P5 output
Output
This pin can be toggled between port pin output and B signal output.
23
VDD2
Power pin
–
Please connect to +5V with the power pin.
24
NC
–
–
This is NC pin. Please open this pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
–
Input
page 2 of 44
This is the pin for external clock input.
Please connect to GND using circuit earthing pin.
Test pin. Connect to 0V.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
6
SIN/SDA
page 3 of 44
3
AC
TEST 16
2
VSS2
VSS1 15
VDD2 23
Address control
circuit
Display character
ROM
1
7
Shift register
Reading address
control circuit
Timing generator
Clock oscillation
circuit display
CPOUT
TCK
Blinking circuit
Display control
circuit
Display location
detection circuit
H counter
Synchronous signal
switching circuit
Port output
control circuit
14
VERT
Polarity switching circuit
13
HOR
Polarity switching circuit
Display character
RAM
Display RAM
Display control
register
Data control
circuit
Input control circuit
VDD1 10
5
4
SCK/SCL
CS
BLOCK DIAGRAM
9
8
P7
P6
21 P4
19 P2
22 P5/B
20 P3/G
18 P1/R
17 P0/BLNK0
M35075-XXXFP
M35075-XXXFP
MEMORY CONSTITUTION
then, RAM is not erased and be undefinited. For detail, see "DATA
INPUT EXAMPLE". Memory constitution is shown in Figure 1 to 9.
Address 00016 to 11F16 are assigned to the display RAM, address
12016 to 12916 are assigned to the display control registers and
address 20016 to 2F116 are assigned to the RAM characters. The
internal circuit is reset and all display control registers (address
12016 to 12916 ) are set to "0" when the AC pin level is "L". And
DAE
DAD
DAC
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
00016
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
00116
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
Blinking
Character color
………
DAF
………
Addresses
Background
coloring
Character code
11E16
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
11F16
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
12016
0
SPACE2 SPACE1 SPACE0 TEST10 DIV10
DIV9
DIV8
DIV7
DIV6
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
12116
0
EXCK1 EXCK0 RSEL1 RSEL0
DIVS1
DIVS0
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
12216
0
TEST17 TEST16 TEST15 TEST14 TEST13 TEST12 TEST11 PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
12316
0
TEST3 TEST2 TEST1 TEST0
HP10
HP9
HP8
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
12416
0
TEST20 RBLK0 TEST19 TEST18 VP10
VP9
VP8
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
12516
0
TEST23 TEST22 TEST21 DSP11 DSP10
DSP9
DSP8
DSP7
DSP6
DSP5
DSP4
DSP3
DSP2
DSP1
DSP0
12616
0
TEST24 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0
LIN9
LIN8
LIN7
LIN6
LIN5
LIN4
LIN3
LIN2
12716
0
TEST25 VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17
LIN16
LIN15
LIN14
LIN13
LIN12
LIN11
LIN10
12816
0
TEST29 TEST32 HSZ20 TEST31 HSZ10 BETA14 TEST28 TEST27 TEST26
FB
FG
FR
RB
RG
RR
12916
0
TEST30 BLINK2 BLINK1 BLINK0 DSPON
BLK0
POLH
POLV
VMASK
B/F
BCOL
DIVS2
STOP RAMERS SYAD
Fig.1 Memory constitution (Display RAM, Display Control register)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 4 of 44
BLK1
M35075-XXXFP
Address
DAF
DAE
DAD
DAC
20016
0
BS
GS
RS
FR000B FR000A FR0009 FR0008 FR0007 FR0009 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000
20116
0
BS
GS
RS
FR001B FR001A FR0019 FR0018 FR0017 FR0019 FR0015 FR0014 FR0013 FR0012 FR0011 FR0010
20216
0
BS
GS
RS
FR002B FR002A FR0029 FR0028 FR0027 FR0026 FR0025 FR0024 FR0023 FR0022 FR0021 FR0020
20316
0
BS
GS
RS
FR003B FR003A FR0039 FR0038 FR0037 FR0036 FR0035 FR0034 FR0033 FR0032 FR0031 FR0030
20416
0
BS
GS
RS
FR004B FR004A FR0049 FR0048 FR0047 FR0046 FR0045 FR0044 FR0043 FR0042 FR0041 FR0040
20516
0
BS
GS
RS
FR005B FR005A FR0059 FR0058 FR0057 FR0056 FR0055 FR0054 FR0053 FR0052 FR0051 FR0050
20616
0
BS
GS
RS
FR006B FR006A FR0069 FR0068 FR0067 FR0066 FR0065 FR0064 FR0063 FR0062 FR0061 FR0060
20716
0
BS
GS
RS
FR007B FR007A FR0079 FR0078 FR0077 FR0076 FR0075 FR0074 FR0073 FR0072 FR0071 FR0070
20816
0
BS
GS
RS
FR008B FR008A FR0089 FR0088 FR0087 FR0086 FR0085 FR0084 FR0083 FR0082 FR0081 FR0080
20916
0
BS
GS
RS
FR009B FR009A FR0099 FR0098 FR0097 FR0096 FR0095 FR0094 FR0093 FR0092 FR0091 FR0090
20A16
0
BS
GS
RS
FR00AB FR00AA FR00A9 FR00A8 FR00A7 FR00A6 FR00A5 FR00A4 FR00A3 FR00A2 FR00A1 FR00A0
20B16
0
BS
GS
RS
FR00BB FR00BA FR00B9 FR00B8 FR00B7 FR00B6 FR00B5 FR00B4 FR00B3 FR00B2 FR00B1 FR00B0
20C16
0
BS
GS
RS
FR00CB FR00CA FR00C9 FR00C8 FR00C7 FR00C6 FR00C5 FR00C4 FR00C3 FR00C2 FR00C1 FR00C0
20D16
0
BS
GS
RS
FR00DB FR00DA FR00D9 FR00D8 FR00D7 FR00D6 FR00D5 FR00D4 FR00D3 FR00D2 FR00D1 FR00D0
20E16
0
BS
GS
RS
FR00EB FR00EA FR00E9 FR00E8 FR00E7 FR00E6 FR00E5 FR00E4 FR00E3 FR00E2 FR00E1 FR00E0
20F16
0
BS
GS
RS
FR00FB FR00FA FR00F9 FR00F8 FR00F7 FR00F6 FR00F5 FR00F4 FR00F3 FR00F2 FR00F1 FR00F0
21016
0
BS
GS
RS
FR010B FR010A FR0109 FR0108 FR0107 FR0106 FR0105 FR0104 FR0103 FR0102 FR0101 FR0100
21116
0
BS
GS
RS
FR011B FR011A FR0119 FR0118 FR0117 FR0116 FR0115 FR0114 FR0113 FR0112 FR0111 FR0110
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
........
21216
Can not be used
21F16
Fig.2 Memory constitution (RAM character 0)
Address
DAF
DAE
DAD
DAC
22016
0
BS
GS
RS
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
FR100B FR100A FR1009 FR1008 FR1007 FR1006 FR1005 FR1004 FR1003 FR1002 FR1001 FR1000
........
22116
RAM character 1 data
23016
23116
0
BS
GS
RS
FR111B FR111A FR1119 FR1118 FR1117 FR1116 FR1115 FR1114 FR1113 FR1112 FR1111 FR1110
........
23216
Can not be used
23F16
Fig.3 Memory constitution (RAM character 1)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 5 of 44
M35075-XXXFP
Address
DAF
DAE
DAD
DAC
24016
0
BS
GS
RS
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
FR200B FR200A FR2009 FR2008 FR2007 FR2006 FR2005 FR2004 FR2003 FR2002 FR2001 FR2000
........
24116
RAM character 2 data
25016
25116
0
BS
GS
RS
FR211B FR211A FR2119 FR2118 FR2117 FR2116 FR2115 FR2114 FR2113 FR2112 FR2111 FR2110
........
25216
Can not be used
25F16
Fig.4 Memory constitution (RAM character 2)
Address
DAF
DAE
DAD
DAC
26016
0
BS
GS
RS
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
FR300B FR300A FR3009 FR3008 FR3007 FR3006 FR3005 FR3004 FR3003 FR3002 FR3001 FR3000
........
26116
RAM character 3 data
27016
27116
0
BS
GS
RS
FR311B FR311A FR3119 FR3118 FR3117 FR3116 FR3115 FR3114 FR3113 FR3112 FR3111 FR3110
........
27216
Can not be used
27F16
Fig.5 Memory constitution (RAM character 3)
Address
DAF
DAE
DAD
DAC
28016
0
BS
GS
RS
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
FR400B FR400A FR4009 FR4008 FR4007 FR4006 FR4005 FR4004 FR4003 FR4002 FR4001 FR4000
........
28116
RAM character 4 data
29016
29116
0
BS
GS
RS
FR411B FR411A FR4119 FR4118 FR4117 FR4116 FR4115 FR4114 FR4113 FR4112 FR4111 FR4510
........
29216
Can not be used
29F16
Fig.6 Memory constitution (RAM character 4)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 6 of 44
M35075-XXXFP
Address
DAF
DAE
DAD
DAC
2A016
0
BS
GS
RS
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
D00
FR500B FR500A FR5009 FR5008 FR5007 FR5006 FR5005 FR5004 FR5003 FR5002 FR5001 FR5000
........
2A116
RAM character 5 data
2B016
2B116
0
BS
GS
RS
FR511B FR511A FR5119 FR5118 FR5117 FR5116 FR5115 FR5114 FR5113 FR5112 FR5111 FR5110
........
2B216
Can not be used
2BF16
Fig.7 Memory constitution (RAM character 5)
Address
DAF
DAE
DAD
DAC
2C016
0
BS
GS
RS
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
FR600B FR600A FR6009 FR6008 FR6007 FR6006 FR6005 FR6004 FR6003 FR6002 FR6001 FR6000
........
2C116
RAM character 6 data
2D016
2D116
0
BS
GS
RS
FR611B FR611A FR6119 FR6118 FR6117 FR6116 FR6115 FR6114 FR6113 FR6112 FR6111 FR6110
........
2D216
Can not be used
2DF16
Fig.8 Memory constitution (RAM character 6)
Address
DAF
DAE
DAD
DAC
2E016
0
BS
GS
RS
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
FR700B FR700A FR7009 FR7008 FR7007 FR7006 FR7005 FR7004 FR7003 FR7002 FR7001 FR7000
........
2E116
RAM character 7 data
2F016
2F116
0
BS
GS
RS
FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110
Fig.9 Memory constitution (RAM character 7)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 7 of 44
M35075-XXXFP
SCREEN CONSTITUTION
The screen lines and rows are determined from each address of
the display RAM . The screen constitution is shown in Figure 10.
Row
Line
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
00016 00116 00216 00316 00416 00516 00616 00716 00816 00916 00A16 00B16 00C16 00D16 00E16 00F16 01016 01116 01216 01316 01416 01516 01616 01716
01816 01916 01A16 01B16 01C16 01D16 01E16 01F16 02016 02116 02216 02316 02416 02516 02616 02716 02816 02916 02A16 02B16 02C16 02D16 02E16 02F16
03016 03116 03216 03316 03416 03516 03616 03716 03816 03916 03A16 03B16 03C16 03D16 03E16 03F16 04016 04116 04216 04316 04416 04516 04616 04716
04816 04916 04A16 04B16 04C16 04D16 04E16 04F16 05016 05116 05216 05316 05416 05516 05616 05716 05816 05916 05A16 05B16 05C16 05D16 05E16 05F16
06016 06116 06216 06316 06416 06516 06616 06716 06816 06916 06A16 06B16 06C16 06D16 06E16 06F16 07016 07116 07216 07316 07416 07516 07616 07716
07816 07916 07A16 07B16 07C16 07D16 07E16 07F16 08016 08116 08216 08316 08416 08516 08616 08716 08816 08916 08A16 08B16 08C16 08D16 08E16 08F16
09016 09116 09216 09316 09416 09516 09616 09716 09816 09916 09A16 09B16 09C16 09D16 09E16 09F16 0A016 0A116 0A216 0A316 0A416 0A516 0A616 0A716
0A816 0A916 0AA16 0AB16 0AC16 0AD16 0AE16 0AF16 0B016 0B116 0B216 0B316 0B416 0B516 0B616 0B716 0B816 0B916 0BA16 0BB16 0BC16 0BD16 0BE16 0BF16
0C016 0C116 0C216 0C316 0C416 0C516 0C616 0C716 0C816 0C916 0CA16 0CB16 0CC16 0CD16 0CE16 0CF16 0D016 0D116 0D216 0D316 0D416 0D516 0D616 0D716
0D816 0D916 0DA16 0DB16 0DC16 0DD16 0DE16 0DF16 0E016 0E116 0E216 0E316 0E416 0E516 0E616 0E716 0E816 0E916 0EA16 0EB16 0EC16 0ED16 0EE16 0EF16
0F016 0F116 0F216 0F316 0F416 0F516 0F616 0F716 0F816 0F916 0FA16 0FB16 0FC16 0FD16 0FE16 0FF16 10016 10116 10216 10316 10416 10516 10616 10716
10816 10916 10A16 10B16 10C16 10D16 10E16 10F16 11016 11116 11216 11316 11416 11516 11616 11716 11816 11916 11A16 11B16 11C16 11D16 11E16 11F16
✽ The hexadecimal numbers in the boxes show the display RAM address.
Fig.10 Screen constitution
RAM Character CONSTITUTION
The dot lines and dot rows of the character RAM are determined
from each address and bit of the character RAM . The RAM character constitution is shown in Figure 11.
Dot
Dot
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
FRn00B
FRn00A FRn009 FRn008 FRn007 FRn006 FRn005 FRn004 FRn003 FRn002 FRn001 FRn000
FRn01B
FRn01A FRn019 FRn018 FRn017 FRn016 FRn015 FRn014 FRn013 FRn012 FRn011 FRn010
FRn02B
FRn02A FRn029 FRn028 FRn027 FRn026 FRn025 FRn024 FRn023 FRn022 FRn021 FRn020
FRn03B
FRn03A FRn039 FRn038 FRn037 FRn036 FRn035 FRn034 FRn033 FRn032 FRn031 FRn030
FRn04B
FRn04A FRn049 FRn048 FRn047 FRn046 FRn045 FRn044 FRn043 FRn042 FRn041 FRn040
FRn05B
FRn05A FRn059 FRn058 FRn057 FRn056 FRn055 FRn054 FRn053 FRn052 FRn051 FRn050
FRn06B
FRn06A FRn069 FRn068 FRn067 FRn066 FRn065 FRn064 FRn063 FRn062 FRn061 FRn060
FRn07B
FRn07A FRn079 FRn078 FRn077 FRn076 FRn075 FRn074 FRn073 FRn072 FRn071 FRn070
FRn08B
FRn08A FRn089 FRn088 FRn087 FRn086 FRn085 FRn084 FRn083 FRn082 FRn081 FRn080
FRn09B
FRn09A FRn099 FRn098 FRn097 FRn096 FRn095 FRn094 FRn093 FRn092 FRn091 FRn090
FRn0AB FRn0AA FRn0A9 FRn0A8 FRn0A7 FRn0A6 FRn0A5 FRn0A4 FRn0A3 FRn0A2 FRn0A1 FRn0A0
FRn0BB FRn0BA FRn0B9 FRn0B8 FRn0B7 FRn0B6 FRn0B5 FRn0B4 FRn0B3 FRn0B2 FRn0B1 FRn0B0
FRn0CB FRn0CA FRn0C9 FRn0C8 FRn0C7 FRn0C6 FRn0C5 FRn0C4 FRn0C3 FRn0C2 FRn0C1 FRn0C0
FRn0DB FRn0DA FRn0D9 FRn0D8 FRn0D7 FRn0D6 FRn0D5 FRn0D4 FRn0D3 FRn0D2 FRn0D1 FRn0D0
FRn0EB FRn0EA FRn0E9 FRn0E8 FRn0E7 FRn0E6 FRn0E5 FRn0E4 FRn0E3 FRn0E2 FRn0E1 FRn0E0
FRn0FB FRn0FA FRn0F9 FRn0F8 FRn0F7 FRn0F6 FRn0F5 FRn0F4 FRn0F3 FRn0F2 FRn0F1 FRn0F0
FRn10B
FRn10A FRn109 FRn108 FRn107 FRn106 FRn105 FRn104 FRn103 FRn102 FRn101 FRn100
FRn11B
FRn11A FRn119 FRn118 FRn117 FRn116 FRn115 FRn114 FRn113 FRn112 FRn111 FRn110
✽ The number in the boxes show the bit address of the RAM character :n. ("n" is RAM number : 0 to 7)
Fig.11 RAM charcter consititution
Note. When the RAM character is used, it is necessary to clear all areas of the RAM character first.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 8 of 44
M35075-XXXFP
DISPLAY RAM
Address 00016 to 11F16
Contents
DA
Register
Remarks
Status
Function
0
0
Set the displayed ROM character code.
C0
Set display character
1
0
1
C1
1
*RAM character is selected using the 8 bits from C7 to C0.
When C7 to C0=(111111102) is set. And, RAM character code
is set to R, G and B.
0
2
C2
1
0
3
C3
1
0
4
C4
1
0
5
B
0
0
0
0
1
1
1
1
G
0
0
1
1
0
0
1
1
R
0
1
0
1
0
1
0
1
RAM character code
RAM character 0
RAM character 1
RAM character 2
RAM character 3
RAM character 4
RAM character 5
RAM character 6
RAM character 7
C5
1
0
6
C6
1
0
7
C7
1
0
8
R
1
0
9
G
1
0
A
B
1
B
C
0
Do not blink.
1
Blinking
0
BB
0
0
0
0
1
1
1
1
BR
0
BG
1
0
E
G
0
0
1
1
0
0
1
1
R
0
1
0
1
0
1
0
1
Color
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
BB
1
BG
0
0
1
1
0
0
1
1
____
Note. The display RAM is undefined state at the AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 9 of 44
Set character color (character unit)
* When set C7 to C0= (111111102), can
be set RAM character code.
Set blinking
See register BLINK2 to BLINK0 (address12916)
BLINK
1
D
B
0
0
0
0
1
1
1
1
BR
0
1
0
1
0
1
0
1
Color
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
Set character background color.
(character unit)
* When set C7 to C0=(111111102)
and register RBLK0
(address 12416)= “1”, set coloring
prohibition color.
Moreover, when the blink is set, the
parts other than the color set by this
register are blinks.
See DISPLAY FORM 2.
M35075-XXXFP
REGISTERS DESCRIPTION
(1) Address 12016
Contents
DA
Register
Remarks
Status
0
DIV0
0
Function
Set division value (multiply value) of horizontal oscillation frequency.
1
0
DIV1
1
10
Σ
(DIVn ✕ 2n)
1
N1 =
0
N1 : division value (multiply value)
n=0
DIV2
2
Set display frequency by division value
(multiply value) setting.
For details, see REGISTER
SUPPLEMENTARY DESCRIPTION
(1).
1
Also, set the display frequency range by
registers DIVS0, DIVS1, DIVS2, RSEL0
and RSEL1(address 12116) in accordance with the display frequency.
0
DIV3
3
Any of this settings above is required
only when EXCK1 = 0, EXCK0 = 1 and
EXCK1 = 1, EXCK0 = 1.
1
0
DIV4
4
1
0
DIV5
5
1
0
DIV6
6
1
0
DIV7
7
1
0
DIV8
8
1
0
DIV9
9
1
0
A
DIV10
1
B
0
It should be fixed to "0".
1
Can not be used.
TEST10
0
C
SPACE0
1
0
D
SPACE1
1
0
E
SPACE2
1
Note. The mark
2
0
0
0
0
1
1
1
1
SPACE
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Number of Lines and Space
<(S) represents space>
12
1 (S) 10 (S) 1
2 (S) 8 (S) 2
3 (S) 6 (S) 3
4 (S) 4 (S) 4
5 (S) 2 (S) 5
6 (S) 6
6 (S)(S) 6
(S) represents one line worth of space
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 10 of 44
Leave one line worth of space in the vertical direction.
For example, 6 (S) 6 indicates two sets
of 6 lines with a line of spaces between
lines 6 and 7.
A line is 18 ✕ N horizontal scan lines.
N is determined by the character size in
the vertical direction
M35075-XXXFP
(2) Address 12116
Contents
DA
Register
Status
0
1
2
3
4
5
6
7
8
Function
0
P0 output (port P0).
1
BLNK0 output.
0
P1 output (port P1).
1
R signal output.
0
P2 output (port P2).
1
Can not be used.
0
P3 output (port P3).
1
G signal output.
0
P4 output (port P4).
1
Can not be used.
0
P5 output (port P5).
1
B signal output.
0
P6 output (port P6).
1
Can not be used.
0
P7 output (port P7).
1
Can not be used.
0
For setting, see REGISTER SUPPLEMENTARY DESCRIPTION
(2).
Remarks
P0 pin output control.
PTC0
PTC1
P1 pin output control.
PTC2
P2 pin output control.
PTC3
P3 pin output control.
PTC4
P4 pin output control.
PTC5
P5 pin output control.
PTC6
P6 pin output control.
PTC7
P7 pin output control.
DIVS0
Set display frequency range.
1
0
9
DIVS1
1
0
A
DIVS2
1
0
B
RSEL0
1
0
C
RSEL1
1
0
D
EXCK0
E
EXCK1
1
0
Note. The mark
Display clock input
EXCK1 EXCK0
0
External synchronous (external clock)
0
1
Internal synchronous
0
0
Do not set
1
1
External synchronous (internal clock)
1
1
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 11 of 44
Display clock setting
See REGISTER SUPPLEMENTARY
DESCRIPTION (1)
M35075-XXXFP
(3) Address 12216
DA
Register
0
PTD0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
Contents
Function
Status
0
"L" output or negative polarity output (BLNK0 output).
1
"H" output or positive polarity output (BLNK0 output).
0
"L" output or negative polarity output (R signal output).
1
"H" output or positive polarity output (R signal output).
0
"L" output.
1
"H" output.
0
"L" output or negative polarity output (G signal output).
1
"H" output or positive polarity output (G signal output).
0
"L" output.
1
"H" output.
0
"L" output or negative polarity output (B signal output).
1
"H" output or positive polarity output (B signal output).
0
"L" output.
1
"H" output.
0
"L" output.
1
"H" output.
0
Can not be used.
1
It should be fixed to "1".
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
P0 pin data control.
PTD1
P1 pin data control.
PTD2
P2 pin data control.
PTD3
P3 pin data control.
PTD4
P4 pin data control.
PTD5
P5 pin data control.
PTD6
P6 pin data control.
PTD7
P7 pin data control.
TEST11
TEST12
TEST13
TEST14
TEST15
TEST16
TEST17
Note. The mark
Remarks
1
Can not be used.
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 12 of 44
M35075-XXXFP
(4) Address 12316
DA
Register
0
HP0
Contents
Remarks
Function
Status
0
If HS is the horizontal display start location,
1
0
1
HP1
1
0
2
HP2
1
10
HS = T ✕ ( Σ 2nNPn+m)
n=0
Horizontal display start location is specified using the 11 bits from HP10 to HP0.
HP10 to HP0 = (00000000000 2) and
(000001001112) setting is forbidden.
T: Period of display frequency
2007 settings are possible.
m : offset value differ for the setting of the register EXCK0 and
EXCK1. It shown below.
0
3
HP3
1
EXCK1
EXCK0
m
0
0
13
0
1
13
1
0
Do not set
1
1
19
0
4
HP4
1
HOR
HS*(shown left) shows horizontal display start location this is register B/F
(address 12916) = "0" is set.
0
5
HP5
1
0
VS
HP6
Note 2
1
VERT
6
0
7
HS
HP7
Note 2
OSD Display area
Note 2
1
0
8
Note 2
HP8
1
Monitor Screen
0
9
HP9
1
0
A
HP10
1
B
C
D
E
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
TEST0
TEST1
TEST2
TEST3
_____
Notes 1. The mark
around the status value means the reset status by the "L" level is input to AC pin.
2. Set up the horizontal and vertical display start location so that display range may not exceed it.
Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 13 of 44
M35075-XXXFP
(5) Address 12416
DA
Contents
Register
0
0
VP0
1
1
0
VP1
1
2
Remarks
Function
Status
If VS is the vertical display start location,
The vertical start location is specified
using the 11 bits from VP10 to VP0.
VP10 to VP0 = (000000000002) setting
is forbidden.
10
VS = H ✕
Σ
n=0
2nVPn
T: Cycle with the horizonal synchronizing pulse
2047 settings are possible.
0
VP2
1
HS*(shown left) shows horizontal display start location this is register B/F
(address 12916) = "0" is set.
HOR
3
0
VP3
1
0
1
5
VS
VP4
0
Note 2
VERT
4
HS
VP5
Note 2
OSD Display area
Note 2
1
6
0
Note 2
VP6
1
Monitor Screen
7
0
VP7
1
8
0
VP8
1
9
0
VP9
1
A
0
.
VP10
1
B
C
D
E
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
Matrix-outline size.
1
Charcter size. (Note 3)
0
It should be fixed to "0".
1
Can not be used.
TEST18
TEST19
RBLK0
Sets the blanking mode of RAM character.
See DISPLAY FORM 2.
TEST20
_____
Notes 1. The mark
around the status value means the reset status by the "L" level is input to AC pin.
2. Set up the horizontal and vertical display start location so that display range may not exceed it.
Set the character code "FF16" (blank without background) for the display RAM of the part which the display range exceeds.
3. The part of the appointed color by BR, BG and BB of the display RAM changes that the blanking is "OFF".
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 14 of 44
M35075-XXXFP
(6) Address 12516
DA
0
Contents
Register
Function
0
The display modes of display screen inside n+1 line by DSPn (n=0
to 11)
DSP0
1
1
0
DSP1
1
2
The display mode decided by the combination with registers BLK1
and BLK0 (address 12916).
Settings are given below.
Sets the display mode of line 1.
Sets the display mode of line 2.
0
DSP2
1
3
Remarks
Status
0
DSP3
BLK1
0
0
1
1
BLK0
0
1
0
1
DSPn="0"
Matrix-outline border
Character
Border
Matrix-outline
DSPn="1"
Matrix-outline
Border
Matrix-outline
Charcter
Sets the display mode of line 3.
Sets the display mode of line 4.
1
(At register BCOL="0")
4
0
DSP4
Sets the display mode of line 5.
1
5
For detail, see DISPLAY FORM 1 (1).
0
DSP5
Sets the display mode of line 6.
1
6
0
DSP6
Sets the display mode of line 7.
1
7
0
DSP7
Sets the display mode of line 8.
1
8
0
DSP8
Sets the display mode of line 9.
1
9
0
DSP9
Sets the display mode of line 10.
1
A
0
DSP10
Sets the display mode of line 11.
1
B
0
DSP11
Sets the display mode of line 12.
1
C
D
E
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
TEST21
TEST22
TEST23
Note. The mark
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 15 of 44
M35075-XXXFP
(7) Address 12616
DA
Contents
Register
Function
Status
0
LIN2
0
1
1
0
LIN3
The vertical dot size for line n in the character dot lines (18 vertical
lines) is set using LINn (n = 2 to 17).
Dot size can be selected between 2 types for each dot line.
Remarks
Character size setting in the vertical
direction for the 2nd line.
Character size setting in the vertical
direction for the 3rd line.
1
2
LIN4
0
For dot size, see the below registers. Line 1 and lines 2 to 12 can
be set independent of one another.
Character size setting in the vertical
direction for the 4th line.
1
3
LIN5
0
1
4
1st line
LINn = "0"
LINn = "1"
Refer to VSZ1L0
and VSZ1L1
Refer to VSZ1H0
and VSZ1H1
Character size setting in the vertical
direction for the 5th line.
2nd to 12th Refer to VSZ2L0 Refer to VSZ2H0
and VSZ2L1
and VSZ2H1
line
Character size setting in the vertical
direction for the 6th line.
0
LIN6
1
5
LIN7
Character size setting in the vertical
direction for the 7th line.
0
1
6
LIN8
Character size setting in the vertical
direction for the 8th line.
0
1
7
LIN9
Character size setting in the vertical
direction for the 9th line.
0
1
8
0
V1SZ0
1
9
V1SZ1
0
1
A
VSZ1L0
0
1
B
0
VSZ1L1
1
C
VSZ1H0
0
1
0
D
VSZ1H1
1
E
TEST24
Note. The mark
H: Cycle with the horizontal synchronizing pulse
V1SZ1 V1SZ0
0
0
0
1
1
0
1
1
Vertical direction size
1H/dot
2H/dot
3H/dot
4H/dot
H: Cycle with the horizontal synchronizing pulse
VSZ1L1 VSZ1L0 Vertical direction size
0
0
1H/dot
0
1
2H/dot
1
0
3H/dot
1
1
4H/dot
H: Cycle with the horizontal synchronizing pulse
VSZ1H1 VSZ1H0 Vertical direction size
0
0
1H/dot
0
1
2H/dot
1
0
3H/dot
1
1
4H/dot
0
It should be fixed to "0".
1
Can not be used.
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 16 of 44
Character size setting in the vertical
direction for the 1st line.
(display monitor 1 to 12 line)
Character size setting in the vertical
direction (display monitor 1 line) at "0"
state in register LIN2 to LIN17
(address 12616, 12716).
Character size setting in the vertical
direction (display monitor 1 line) at "1"
state in register LIN2 to LIN17
(address 12616, 12716).
M35075-XXXFP
(8) Address 12716
DA
Contents
Register
Function
Status
0
0
LIN10
1
0
1
LIN11
The vertical dot size for line n in the character dot lines (18 vertical
lines) is set using LINn (n = 2 to 17).
Dot size can be selected between 2 types for each dot line.
Remarks
Character size setting in the vertical
direction for the 10th line.
Character size setting in the vertical
direction for the 11th line.
1
0
2
LIN12
For dot size, see the below registers. Line 1 and lines 2 to 12 can
be set independent of one another.
Character size setting in the vertical
direction for the 12th line.
1
LINn = "0"
LINn = "1"
Refer to VSZ1L0
and VSZ1L1
Refer to VSZ1H0
and VSZ1H1
0
3
LIN13
1st line
1
0
4
2nd to 12th Refer to VSZ2L0 Refer to VSZ2H0
and VSZ2L1
and VSZ2H1
line
LIN14
Character size setting in the vertical
direction for the 13th line.
Character size setting in the vertical
direction for the 14th line.
1
Character size setting in the vertical
direction for the 15th line.
0
5
LIN15
1
Character size setting in the vertical
direction for the 16th line.
0
6
LIN16
1
Character size setting in the vertical
direction for the 17th line.
0
7
LIN17
1
0
8
V18SZ0
1
0
9
V18SZ1
1
0
A
VSZ2L0
1
0
B
VSZ2L1
1
0
C
VSZ2H0
1
0
D
VSZ2H1
1
E
TEST25
Note. The mark
H: Cycle with the horizontal synchronizing pulse
V18SZ1 V18SZ0 Vertical direction size
0
0
1H/dot
0
1
2H/dot
1
0
3H/dot
1
1
4H/dot
H: Cycle with the horizontal synchronizing pulse
VSZ2L1 VSZ2L0 Vertical direction size
1H/dot
0
0
2H/dot
0
1
3H/dot
1
0
4H/dot
1
1
H: Cycle with the horizontal synchronizing pulse
VSZ2H1 VSZ2H0 Vertical direction size
0
1H/dot
0
2H/dot
1
1
0
3H/dot
0
1
4H/dot
1
0
It should be fixed to "0".
1
Can not be used.
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 17 of 44
Character size setting in the vertical
direction for the 18th line.
(display monitor 1 to 12 line)
Character size setting in the vertical
direction (display monitor for 2 to 12
line) at "0" state in register LIN2 to
LIN17 (address 12616, 12716).
Character size setting in the vertical
direction (display monitor for 2 to12
line) at "1" state in register LIN2 to
LIN17(address 12616, 12716).
M35075-XXXFP
(9) Address 12816
DA
Contents
Register
Function
Status
0
0
RR
1
0
1
RG
1
0
2
RB
1
FR
1
0
4
FG
1
0
5
FB
1
7
8
9
A
C
E
Color
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
FB
0
0
0
0
1
1
1
1
FG
0
0
1
1
0
0
1
1
FR
0
1
0
1
0
1
0
1
Color
Black
Red
Green
Yellow
Blue
Magenta
Cyan
White
It should be fixed to “0”.
1
Can not be used.
0
It should be fixed to “0”.
1
Can not be used.
0
It should be fixed to “0”.
1
Can not be used.
0
Matrix-outline display (12 ✕ 18 dot)
1
Matrix-outline display (14 ✕ 18 dot)
TEST27
TEST28
BETA14
0
HSZ10
HSZ10
0
1
Horizontal direction size
1T/dot
2T/dot
0
It should be fixed to “0”.
1
Can not be used.
0
HSZ20
0
1
Sets the raster color of all blankings.
Set the blanking color of the Border
size, or the shadow size.
Charcter size setting in the horizontal
direction for the first line.
T: Display frequency cycle
TEST31
HSZ20
1
D
RR
0
1
0
1
0
1
0
1
0
TEST26
1
B
RG
0
0
1
1
0
0
1
1
0
3
6
RB
0
0
0
0
1
1
1
1
Remarks
Horizontal direction size
1T/dot
2T/dot
0
It should be fixed to "0".
1
Can not be used.
0
It should be fixed to "0".
1
Can not be used.
TEST32
TEST29
Note. The mark
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 18 of 44
Charcter size setting in the horizontal
direction for the 2nd line to 12th line.
T: Display frequency cycle
M35075-XXXFP
(10) Address 12916
DA
Contents
Register
Function
Status
0
3
4
Blanking of BLK0, BLK1
1
All raster blanking
0
Synchronize with the leading edge of horizontal synchronization.
1
Synchronize with the trailing edge of horizontal synchronization.
0
Do not mask by VERT input signal
1
Mask by VERT input signal
0
VERT pin is negative polarity
1
VERT pin is positive polarity
0
HOR pin is negative polarity
1
HOR pin is positive polarity
B/F
VMASK
0
BLK0
0
6
9
A
B
BLK1
BLK1
0
0
1
1
BLK0
0
1
0
1
Blanking mode
Matrix-outline size
Character size
Border size
Matrix-outline size
1
( When DSPn (address 12516) = "0" )
Set VERT pin polarity.
Set HOR pin polarity.
0
Border display of character
1
Shadow display of character
0
RAM not erased
1
RAM erased
0
Oscillation of clock for display
1
Stop the oscillation of clock for display
0
Display OFF
1
Display ON
Set blanking mode.
See DISPLAY FORM 1 (1).
See DISPLAY FORM 1 (2).
SYAD
When register RAMERS is set to "1", do
not stop the display clock. There is no
need to reset because there is no
register for this bit.
RAMERS
STOP
DSPON
0
BLINK0
1
C
Set mask at phase comparison
operating.
POLH
1
8
Synchronize with the front porch or
back porch of the horizontal
synchronization signal.
POLV
5
7
Sets all raster blanking
BCOL
1
2
0
Remarks
0
BLINK1
BLINK1 BLINK0
0
0
1
0
0
1
1
1
Duty
Blinking OFF
25%
50%
75%
Set blinking duty ratio.
1
D
E
0
Divided into 64 of vertical synchronous signal
1
Divided into 32 of vertical synchronous signal
0
It should be fixed to "0".
1
Can not be used.
BLINK2
TEST30
Note. The mark
around the status value means the reset status by the "L" level is input to AC pin.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 19 of 44
Set blinking frequency.
M35075-XXXFP
REGISTER SUPPLEMENTARY DESCRIPTION
(1) Setting external clock input and display frequency mode
Setting external clock input and display frequency mode (by
use of EXCK0, EXCK1 (12116), and DIV10 to DIV0 (12016) as
explained here following.
(a) When (EXCK1, EXCK0) = (0, 0) ......External clock mode 1
Fosc = 6.3 to 80 MHz (VDD = 4.75 to 5.25 V)
Fosc = 6.3 to 40 MHz (VDD = 2.50 to 3.50 V)
Input from the TCK pin a constant-period continuous
external clock that synchronizes with the horizontal
synchronous signal. And input from HOR pin a constant
period continuous horizontal synchronous signal.
Never stop inputting the clock while displaying.
Do not have to set a display frequency because the clock
just as it is entered from outside is used as the display
clock.
(c) When (EXCK1, EXCK0) = (1, 0) ......… Setting disabled
(d) When (EXCK1, EXCK0) = (1, 1) ......External clock mode 2
Fosc = 20 to 110 MHz (VDD = 4.75 to 5.25 V)
Input from the TCK pin a constant-period continuous external
clock that synchronizes with the horizontal synchronous
signal. And input from HOR pin a constant-period continuous
horizontal synchronous signal.
Never stop inputting the clock while displaying.
An internal clock which is in sync with the external input clock
is used as the display clock.
Because the display frequency equals the external clock
frequency, set N1 (division value) that satisfies the below
expressions to DIV10 to DIV0 (address 12016) for make the
display frequency is equal to the external clock frequency.
N1 = external clock frequency / horizontal synchronous
frequency
(b) When (EXCK1, EXCK0) = (0, 1) ......Internal clock mode
Fosc = 20 to 110 MHz (VDD = 4.75 to 5.25 V)
Clock input from the TCK pin is unnecessary. The multiply
clock of the internally generated horizontal synchronous
signal is used as the display clock.
The display frequency is set by setting the multiply value of
the horizontal synchronous frequency (of the display
frequency) in DIV10 to DIV0 (address 12016). Also, set the
display frequency range. (See the next page.)
Display frequency is calculated using the below expression.
10
N1 =
Σ
n=0
Also, set the display frequency range. (See the next page.)
Display frequency = Horizontal synchronous frequency x
Multiply value
Horizontal synchronous signal
1H
External clock
Number of clock (N1)
Fig. 12 Example of external clock input
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 20 of 44
2nDIVn
M35075-XXXFP
(2) To set display frequency range
Whenever setting display frequency (when EXCK1 = "0",
EXCK0 = "1", or EXCK1 = "1", EXCK0 = "1"), always set the
display frequency range in accordance with the display
frequency. This range is set from DIVS0, DIVS1, DIVS2,
RSEL0 and RSEL1 (address 12116). Frequency ranges are
given here below.
RSEL1
RSEL0
DIVS2
DIVS1
DIVS0
Display frequency range MHz
1
1
0
0
0
100.0 to 110.0
1
0
0
0
0
–
0
1
0
0
0
92.0 to 100.0
0
0
0
0
0
73.0 to 92.0
1
1
0
0
1
66.5 to 73.0
1
0
0
0
1
–
0
1
0
0
1
61.0 to 66.5
0
0
0
0
1
49.0 to 61.0
1
1
0
1
0
–
1
0
0
1
0
–
0
1
0
1
0
45.5 to 49.0
0
0
0
1
0
36.5 to 45.5
1
1
0
1
1
33.5 to 36.5
1
0
0
1
1
–
0
1
0
1
1
30.5 to 33.5
0
0
0
1
1
24.5 to 30.5
1
1
1
0
0
–
1
0
1
0
0
–
0
1
1
0
0
23.0 to 24.5
0
0
1
0
0
20.0 to 23.0
(3) Notes on setting display frequency
To change external clock (display) frequency or horizontal synchronization frequency, always use the following procedures.
To set EXCK1 = "0", EXCK0 = "1"
(a) Turn the display OFF. … DSPON (address 12916) = "0"
(b) Set the display frequency. … Set from DIV10 to
DIV0(address 12016) , DIVS0, DIVS1, DIVS2, RSEL0
and RSEL1 (address 12116).
(c) Wait 20 ms while the horizontal synchronization signal is
being input.
(d) Turn the display ON. … DSPON (address 12916) = "1"
To set EXCK1 = "1", EXCK0 = "1"
(a) Turn the display OFF. … DSPON (address 12916) = "0"
(b) Set the display frequency. … Set from DIV10 to
DIV0(address 12016) , DIVS0, DIVS1, DIVS2, RSEL0
and RSEL1 (address 12116).
(c) Wait 20 ms while the horizontal synchronization signal
and external clock are being input.
(d) Turn the display ON. … DSPON (address 12916) = "1"
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 21 of 44
M35075-XXXFP
DISPLAY FORM 1
Matrix-outline size
: Blanking the background 12 ✕ 18 dot.
All blanking size
: When set register BCOL to "1", all raster area is blanking.
M35075-XXXFP has the following four display forms.
(1) ROM character blanking mode
Character size
: Blanking same as the character size.
Border size
: Blanking the background as a size from character.
BCOL
0
1
BLK1
BLK0
0
The display mode and blanking mode can be set line-by-line, as
follows, from registers BCOL, BLK1, BLK0 (address 12916), DSP0
to DSP11 (address 12516).
Line of DSPn = "0"
Line of DSPn = "1"
Display mode
Blanking mode
Display mode
Blanking mode
0
Matrix-outline border display
Matrix-outline size
Matrix-outline display
Matrix-outline size
0
1
Character display
Character size
Border display
Border size
1
0
Border display
Border size
Matrix-outline display
Matrix-outlinesize
1
1
Matrix-outline display
Matrix-outline size
Character display
Character size
0
0
Matrix-outline border display
0
1
Character display
1
0
Border display
1
1
Matrix-outline display
<Register BCOL=“0”>
Matrix-outline display
Border display
All blanking size
Matrix-outline display
All blanking size
Character display
(Note 1)
12 dots (Note 2)
12 dots
12 dots
12 dots (Note 2)
18 dots
Scanning
R,GorB output
BLNK0 output
color setting
Character color
: R,G,B of display RAM
Character color : R,G,B of display RAM
(Character unit)
(Character unit)
:Register FR,FG,FB
(Display unit)
Matrix-outline color :BR,BG,BB of display RAM
(Character unit)
Border color
(a) Matrix-outline and border
display (Matrix-outline size)
(b) Character display
(Character size)
Character color : R,G,B of display RAM
(Character unit)
Border color :BR,BG,BB of display
RAM (Character unit)
(c) Border display
(Border size)
Character color : R,G,B of display RAM
(Character unit)
Matrix-outline color :BR,BG,BB of display
RAM (Character unit)
(d) Matrix-outline display
(Matrix-outline size)
( ) is blanking mode.
Note 1. When register BCOL is set to "1", the raster range of the display modes set respectively by BLK1 and BLK0 are colored by registers RR, RG, and RB
(address 12816). And the blanking mode is set all blanking size (all raster size) regardless of the BLK1 and BLK0 settings.
Note 2. The horizontal size of the full matrix-outline size can be set to 14 dots by register BETA14 (address 12816). BLNK0 can also be output at 14 dots.
Fig. 13 Display form
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 22 of 44
M35075-XXXFP
(2) Shadow display
When border display mode, if set SYAD (address 12916) = "0"
to "1", it change to shadow display mode.
Border and shadow display are shown below.
Set shadow display color by BR, BG and BB of display RAM or
by register FR, FG and FB.
Register SYAD(12916 address) = “0”
Border display
Register SYAD(12916 address) = “1”
Shadow display
Note : Border display is invalid in RAM characters.
Fig.14 Border and shadow display
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 23 of 44
M35075-XXXFP
DISPLAY FORM 2
This IC can display both ROM character and RAM character at
the same time. The display form is shown in Figure 15 and 16.
(1) RAM character blanking mode
BCOL
RBLK0
0
1
Display mode
Blanking mode
0
Matrix-outline display
Matrix-outline size
1
Character display (Note1)
Character size (Note2)
0
Matrix-outline display
All blanking size
1
Character display (Note1)
All blanking size
Note1: The part of the appointed color by BR, BG and BB of the display RAM changes that is not coloring.
Note2: The part of the appointed color by BR, BG and BB of the display RAM changes that the blanking is "OFF"
< Regiser BCOL = “0”, RBLK0 = “0”> (Note 1)
RAM Character
ROM Character
RAM Character
12dots (Note 2)
ROM Character
12dots (Note 2)
Scanning
Scanning
R,GorB output
BLNK0 output
Color setting
R, G, B of display RAM
(Character unit)
BR, BG, BB of display RAM
(Character unit)
Display mode
(RAM character setting) (ROM character setting)
: RAM character code No. Character color
:
: Matrix-outline display
(Matrix- outline size)
RAM Character
(b)
Color setting
R, G, B of display RAM
(Character unit)
BR, BG, BB of display RAM
(Character unit)
Display mode
(RAM character setting) (ROM character setting)
: RAM character code No. Character color
:
Border color
: Matrix-outline display
(Matrix- outline size)
RAM Character
ROM Character
(c)
ROM Character
12dots (Note 2)
12dots (Note 2)
Scanning
Scanning
R,GorB output
BLNK0 output
Color setting
R, G, B of display RAM
(Character unit)
BR, BG, BB of display RAM
(Character unit)
Display mode
(RAM character setting) (ROM character setting)
: RAM character code No. Character color
:
Matrix-outline color
: Matrix-outline display
(Matrix- outline size)
(d)
Color setting
R, G, B of display RAM
(Character unit)
BR, BG, BB of display RAM
(Character unit)
FR, FG, FB of register
(Display unit)
Display mode
(RAM character setting) (ROM character setting)
: RAM character code No. Character color
:
Matrix-outline color
:
Border color
: Matrix-outline display
(Matrix- outline size)
(a)
( ) is blanking mode.
Refer to DISPLAY FORM 1 about (a)-(d).
Fig.15 Display form1
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
Continue to Next
page 24 of 44
M35075-XXXFP
< Register BCOL = “0”, RBLK0 = “1”> (Note 1)
RAM Character
ROM Character
RAM Character
12dots (Note 2)
ROM Character
12dots (Note 2)
Scanning
Scanning
R,GorB output
BLNK0 output
Color setting
R, G, B of display RAM
(Character unit)
BR, BG, BB of display RAM
(Character unit)
Display mode
(RAM character setting) (ROM character setting)
: RAM character code No. Character color
.
: Coloring prohibition
color
: Character display
(Character size)
RAM Character
(b)
Color setting
R, G, B of display RAM
(Character unit)
BR, BG, BB of display RAM
(Character unit)
Display mode
ROM Character
(RAM character setting) (ROM character setting)
: RAM character code No. Character color
: Coloring prohibition
: Character display
(Character size)
RAM Character
12dots (Note 2)
Border color
color
(c)
ROM Character
12dots (Note 2)
Scanning
Scanning
R,GorB output
BLNK0 output
Color setting
(RAM character setting) (ROM character setting)
R, G, B of display RAM
: RAM character code No. Character color
(Character unit)
Matrix-outline color
BR, BG, BB of display RAM :
(Note 3)
(Character unit)
Display mode
: Matrix-outline display
(Matrix-outline size)
(Note 3)
(d)
Color setting
(RAM character setting) (ROM character setting)
R, G, B of display RAM
: RAM character code No. Character color
(Character unit)
(Note 3) Matrix-outline color
BR, BG, BB of display RAM :
(Character unit)
FR, FG, FB of register
(Display unit)
Display mode
:
Border color
: Matrix-outline display
(Matrix-outline size)
(Note 3)
(a)
( ) is blanking mode.
Refer to DISPLAY FORM 1 about (a)-(d).
Note 1 : When register BCOL = "1", the raster range of the display modes set respectively by RBLK0 is colored by register RR, RG and RB
(address 12816) . And the blanking mode is set all blanking size (all raster size) independent of the RBLK0 settings.
Note 2 : The horizontal size of the full matrix-outline size can be set to 14 dots by register BETA14 (address 12816). BLNK0 can also be output at 14 dots.
Note 3 : When display mode (setting by register BLK1, BLK0, DSPn) is Matrix-outline display or Matrix-outline border display, register
RBLK0= "1" setting (coloring prohibition color setting) is invalid.
Fig. 16 Display form2
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 25 of 44
M35075-XXXFP
Example of setting RAM character data
For example : RAM character 0
Example of setting the RED bit code data
Address
DAF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAE DAD DAC DAB DAA DA9 DA8
(BS) (GS) (RS) (1)
(2)
(3)
(4)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.......
(1)20016
(2)20116
(3)20216
(4)20316
(5)20416
(6)20516
(7)20616
(8)20716
(9)20816
(10)20916
(11)20A16
(12)20B16
(13)20C16
(14)20D16
(15)20E16
(16)20F16
(17)21016
(18)21116
21216
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
DA7 DA6 DA5 DA4 DA3
(5)
(6) (7)
(8)
(9)
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
DA2 DA1 DA0
(10) (11) (12)
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RED
(Dot)
1 2 3 4 5 6 7 8 9 101112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
(Dot)
Can not used
21F16
+
Example of setting the GREEN bit code data
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAE DAD DAC
(BS) (GS) (RS)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAB DAA DA9 DA8 DA7 DA6
(1)
(2) (3)
(4)
(5)
(6)
DA5 DA4 DA3 DA2 DA1 DA0
(7)
(8) (9)
(10) (11) (12)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
.......
(1)20016
(2)20116
(3)20216
(4)20316
(5)20416
(6)20516
(7)20616
(8)20716
(9)20816
(10)20916
(11)20A16
(12)20B16
(13)20C16
(14)20D16
(15)20E16
(16)20F16
(17)21016
(18)21116
21216
DAF
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
1
0
1
1
1
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GREEN
(R+G+B display image)
(Dot)
(Dot)
1 2 3 4 5 6 7 8 9 101112
1 2 3 4 5 6 7 8 9 101112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
(Dot)
(Dot)
Can not used
21F16
+
Example of setting the GREEN bit code data
Address
DAE DAD DAC
(BS) (GS) (RS)
DAB DAA DA9 DA8 DA7
(1)
(2) (3)
(4)
(5)
DA6 DA5
(6)
(7)
DA4 DA3 DA2 DA1 DA0
(8)
(9) (10) (11) (12)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
.......
(1)20016
(2)20116
(3)20216
(4)20316
(5)20416
(6)20516
(7)20616
(8)20716
(9)20816
(10)20916
(11)20A16
(12)20B16
(13)20C16
(14)20D16
(15)20E16
(16)20F16
(17)21016
(18)21116
21216
DAF
Can not used
21F16
Note 1 : After clearing or setting all character RAM areas, and use the
RAM characters.
Note 2 : The RAM character's dots are set RED, GREEN and BLUE data,
which are controlled by BS, GS and RS bit. (Can be set at same
time)
Fig.17 Setting of the data of RAM character
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 26 of 44
BLUE
(Dot)
1 2 3 4 5 6 7 8 9 101112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
(Dot)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
M35075-XXXFP
CHARACTER FONT
Images are composed on a 12 ✕ 18 dot matrix, and characters
can be linked vertically and horizontally with other characters to allow the display the continuous symbols.
Character code FF 16 is fixed as a blank without background.
Therefore, cannot register a character font in this code.
18 dots
12 dots
Note:
Border
When the character extends
to the top line of the matrix,
no border is left at the top.
When the character extends
to the bottom (18th) line of the
matrix, no border is left at the
bottom.
Note: Hatching represents border.
Fig.18 Example of border display
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 27 of 44
M35075-XXXFP
DATA INPUT EXAMPLE
Data of display RAM and display control registers can be set by
the I 2C-BUS serial input function. Example of data setting is
shown in Figure 19 (at EXCK0 = "1", EXCK1 = "0" setting).
Address/data
DAF DAE DAD DAC DAB DAA DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
200 m sec hold
Address 12016
Data
12016
Data
12116
Data
12216
Data
12316
Data
12416
Data
12516
Data
12616
Data
12716
Data
12816
Data
12916
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIV10 DIV9
System set up (Note 3)
1
0
0
1
0
0
0
0
0
DIV8
DIV7
DIV6
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
Frequency value setting
1
1
1
0
1
0
1
1
Frequency range setting
Output setting
RSEL1RSEL0 DIVS2 DIVS1 DIVS0
Data
20016
2F116
Data
20016
0
1
1
1
1
0
1
0
1
1
HP10
HP9
HP8
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
Horizontal display location setting
0
0
0
VP10
VP9
VP8
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
Vertical display location setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Display form setting
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Character size setting
2F116
0
0
0
0
0
0
1
0
0
0
0
0
POLH POLV
0
0
0
0
0
1
1
0
0
1
0
0
0
Data
0
1
0
0
Data
00016
0
0
0
……
……
Data
……
……
2F116
11F16
0
Address 12916
0
0
Data
12916
0
0
0
0
0
1
0
RED•bit code setting
0
0
0
0
0
0
0
0
Address setting
GREEN•bit code setting
FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110
0
0
1
0
0
0
0
0
0
0
0
0
Address setting
FR000B FR000A FR0009 FR0008 FR0007 FR0006 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000
BLUE•bit code setting
FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110
Background
coloring
Blink
-ing
BB BG BR
BLINK
B
G
R
0
0
0
1
0
0
1
0
0
0
Address setting
FR000B FR000A FR0009 FR0008 FR0007 FR0006 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000
BLINK
0
0
Display OFF
FR711B FR711A FR7119 FR7118 FR7117 FR7116 FR7115 FR7114 FR7113 FR7112 FR7111 FR7110
0
0
0
BB BG BR
0
0
0
Bit code/BLUE
0
Color, character size setting
FR000B FR000A FR0009 FR0008 FR0007 FR0006 FR0005 FR0004 FR0003 FR0002 FR0001 FR0000
Bit color
1
Character size setting
Be stable/Waiting time
0
Bit code/GREEN
0
0
Address00016
1
Bit color
0
0
Data
0
Bit code/RED
Address 20016
20016
0
Bit color
……
……
Data
0
0
……
……
Data
Address 20016
0
0
Address setting
0
20 m sec hold
Address 20016
Remarks
0
0
B
0
G
0
R
0
0
C7 C6
0
0
0
0
0
0
C5 C4 C3 C2 C1 C0
Character
color
Character setting
Character code
C7 C6
0
0
0
1
Address setting
C5 C4 C3 C2 C1 C0
1
1
0
1
POLH POLV
0
0
0
0
1
0
Address setting
Display ON (Note 2)
Notes 1 : Input a continuous clock of constant period from the TCK pin. Also, input a horizontal synchronous signal into the HOR pin and a vertical
synchronous signal into the VERT pin.
2 : Matrix-outline display in this data.
____
3 : Secure the waiting time of 200ms after releasing AC, and set data from setting the display frequency (setting of the register).
4 : Set data to Display RAM and Display character RAM at internal clock (display clock) is stabilized.
Fig. 19 Example of data setting
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 28 of 44
M35075-XXXFP
Horizontal synchronors signal (3V or 5V)
Synchronous
signal
generator
+3V or +5V
Vertical synchronors signal (3V or 5V)
24
1
CPOUT
2
3
4
P5/B
SIN/SDA
7
TCK
8
9
10
P4
P3/G
P2
P1/R
P6
P0/BLNK0
P7
BIN
VDD1
11
12
+3V or +5V
AC
SCK/SCL
6
External clock
VDD2
CS
5
Microcomputer
VSS2
M35075-XXXFP
1µF
– +
NC
VSS1
NC
VERT
NC
HOR
23
22
B
21
20
G
19
18
R
17
BLNK0
16
15
14
13
100µF
+ –
100µF
– +
1µF
1µF
0.01µF
0.01µF
Notes 1: CPOUT pin can be opened when use only EXCK1= “0” and EXCK= “0.”
2: Connect CS pin to VDD at the time of I2C-Bus communication use.
Fig.20 Example of the M35075-XXXFP peripheral circuit (Internal synchronous. At EXCK1 = "0", EXCK0 = "0")
Horizontal synchronors signal (5V)
Synchronous
signal
generator
+5V
Vertical synchronors signal (5V)
1
1.0kΩ (note 1)
0.1µF (note 2)
2
3
4
5
Microcomputer
6
7
8
9
10
24
CPOUT
NC
VSS2
VDD2
AC
P5/B
CS
SCK/SCL
SIN/SDA
TCK
M35075-XXXFP
470PF (note 2)
1µF
– +
P4
P3/G
P2
P1/R
P6
P0/BLNK0
P7
BIN
VDD1
11
12
+5V
VSS1
NC
VERT
NC
HOR
23
22
B
21
20
G
19
18
R
17
BLNK0
16
15
14
13
100µF
+ –
100µF
– +
1µF
1µF
0.01µF
0.01µF
Note : Connect CS pin to VDD at the time of I2C-Bus communication use.
Note 1: Use this 1% precision element
Note 2: Use this 10% precision element
Fig.21 Example of the M35075-XXXFP peripheral circuit (External synchronous. At EXCK1 = "0", EXCK0 = "1")
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 29 of 44
M35075-XXXFP
Horizontal synchronors signal (5V)
Synchronous
signal
generator
+5V
Vertical synchronors signal (5V)
1
1.0kΩ (note 1)
0.01µF (note 2)
2
3
4
5
Microcomputer
6
7
8
9
External clock
10
24
CPOUT
NC
VSS2
VDD2
AC
P5/B
CS
SCK/SCL
SIN/SDA
TCK
M35075-XXXFP
47PF (note 2)
1µF
– +
P4
P3/G
P2
P1/R
P6
P0/BLNK0
P7
BIN
VDD1
11
12
+5V
VSS1
NC
VERT
NC
HOR
23
22
B
21
20
G
19
18
R
17
BLNK0
16
15
14
13
100µF
+ –
100µF
– +
1µF
1µF
0.01µF
0.01µF
Note : Connect CS pin to VDD at the time of I2C-Bus communication use.
Note 1: Use this 1% precision element
Note 2: Use this 10% precision element
Fig.22 Example of the M35075-XXXFP peripheral circuit (External clock mode 2. At EXCK1 = "1", EXCK0 = "1")
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 30 of 44
M35075-XXXFP
DATA INPUT 1
__
(d)The 16 bits in the SCK after the CS signal has fallen are the
address, and for succeeding input data, the address is
incremented every 16 bits. Therefore, it is not necessary to in
put the address from the second data.
__
Note. Stop the input to SCK pin and fix it to “H” at CS pin
“H” level.
(1) The16-bit communication function
(a)Serial data should be input with the LSB first.
(b)The address consists of 16 bits.
(c)The data consists of 16 bits.
CS
SCK
SIN
LSB
MSB LSB
Address(16 bits)
MSB
Data(16 bits)
N
LSB
MSB
Data(16 bits)
N+1
N = 1,2,3………
Fig.23 Serial input timing
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 31 of 44
M35075-XXXFP
(2)Timing requirements
Data input
Parameter
Symbol
tw(SCK)
__
tsu(CS)
__
th(CS)
tsu(SIN)
th(SIN)
tword
Min.
200
200
2
200
200
10
SCK width
__
CS setup time
__
CS hold time
SIN setup time
SIN hold time
1 word writing time
Limits
Typ.
—
—
—
—
—
—
Max.
—
—
—
—
—
—
Unit
Remarks
ns
ns
µs
ns
ns
µs
See Figure 24
tw(CS)
1µs(min.)
CS
tsu(CS)
tw(SCK)
tw(SCK)
tsu(SIN)
th(SIN)
th(CS)
SCK
SIN
CS
tword
more than 2 µs
SCK
1
2
… 12
13
Fig. 24 Serial input timing requirements
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 32 of 44
14
15
16
1
… 12
13
14
15
16
M35075-XXXFP
DATA INPUT 2
(1) I2C-Bus communication function
This IC has a built-in data transmission interface which utilizes
2 unidirectional buses. In communications, this IC functions as
a slave reception
device.
_____
Must connect CS pin to “H” at the time of I2C-Bus communication use.
The IC is synchronized with the serial clock (SCL) sent from
the master device and receives the data (SDA).
Communications are controlled from the start/stop states.
Also, always in put the control byte after attaining the start
state.
The below chart shows the start/stop state and control byte
configuration.
SCL
SDA
Start state
Data receive
Data modify
enable
Stop state
Fig.25 Start state / Stop state
Control byte: 7C16(Fixed)
Slave address
0
1
1
1
1
R/W
1
0
0
(0: Written)
Fig.26 Control byte configuration
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 33 of 44
M35075-XXXFP
(2) Data input (Sequence)
(a) Addresses are consists of 16 bits.
(b) Data is consists of 16 bits.
(c) Addresses and data are communicated in 8-bit units. Input
the lower 8 bits before the upper 8 bits. Make input from
the MSB side.
(d) After the start state has been attained and the control byte
(7CH) received, the next 16 bits (2 bytes) are for inputting
the address. Addresses are increased in increments for
every 16 bits (2 bytes) of data input thereafter. As a result,
it is not necessary to input the address from the second
data.
Note:During external synchronous , do not stop the external clock
input from the TCK pin while inputting data.
S
T
A
R
T
SDA
Control byte
(7 CH)
S
Lower address
(N)
M
S
B
A*
C
K
Upper address
(N)
L
S
B
M
S
B
A
C
K
Upper data
(N)
Lower data
(N)
L
S
B
M
S
B
A
C
K
L
S
B
M
S
B
A
C
K
S
T
O
P
lower data
(N + 1)
L
S
B
M
S
B
A
C
K
L
S
B
P
A
C
K
ACK* (Acknowledge) : Output the acknowledge signal whenever one byte input after the start state.
Output the acknowledge signal and recieve the data thereafter when match the
slave address (7CH).
Fig.27 Data input sequence
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 34 of 44
M35075-XXXFP
(2) Timing requirements
Data input
Limits
Symbol
Parameter
Max.
Min.
Max.
100
0
400
KHz
HIGH period of Clock
4000
–
600
–
ns
LOW period of Clock
4700
–
1300
–
ns
300
ns
300
ns
tHIGH
tF
Remarks
Unit
0
Clock frequency
tR
High-speed mode
Min.
fCLK
tLOW
Typ. mode
SDA & SCL rise time
–
1000
SDA & SCL fall time
–
300
20+(Note)
0.1CB
20+(Note)
0.1CB
tHD : STA
Hold time at START status
4000
–
600
–
ns
tSU : STA
Set up time at START status
4700
–
600
–
ns
tHD : DAT
Data input hold time
0
–
0
–
ns
tSU : DAT
Data input setup time
250
–
100
–
ns
600
–
ns
tSU : STO
Set up time at STOP state
4000
–
tBUF
Bus release time
4700
–
1300
–
ns
tSP
Input filter / spike suppress (SDA & SCL pin)
N/A
N/A
0
50
ns
Only at START state
repeating generation
Time must be released bus before
next transmission
Note. CB = total capacitance of 1 bus line.
tF
tR
tHIGH
tLOW
SCL
tHD : DAT
tsu : STA
tSU : DAT
tSU : STO
tHD : STA
SDA
tSP
tBUF
Fig.28 Data input timing
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 35 of 44
M35075-XXXFP
ABSOLUTE MAXIMUM RATINGS (VDD = 5.00V, Ta = –20 to +85°C, unless otherwise noted)
Symbol
Parameter
Ratings
Unit
–0.3 to +6.0
V
VSS –0.3 ≤ VI ≤ VDD +0.3
V
VSS ≤ VO ≤ VDD
V
+300
mW
–20 to +85
°C
Conditions
VDD
Supply voltage
VI
Input voltage
VO
Output voltage
Pd
Power dissipation
Topr
Operating temperature
Tstg
Storage temperature
–40 to +125
°C
With respect to VSS.
Ta = +25 °C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VDD
Min.
4.75
2.50
3.0
3.50
V
0.8VDD
VDD
VDD
V
SCK/SCL, SIN/SDA
0.7VDD
VDD
VDD
V
AC, CS, HOR, VERT
0
0
0.2VDD
V
SCK/SCL, SIN/SDA
0
0
0.3VDD
V
VDD = 4.75 to 5.25 V
6.3
—
80.0
MHz
VDD = 2.50 to 3.50 V
6.3
—
40.0
MHz
External clock mode 2
VDD = 4.75 to 5.25 V
20.0
—
110.0
MHz
Internal clock mode
VDD = 4.75 to 5.25 V
20.0
—
110.0
MHz
VDD = 4.75 to 5.25 V
15.0
—
130.0
kHz
VDD = 2.50 to 3.50 V
15.0
—
60.0
kHz
Min.
Limits
Typ.
Max.
4.75
5.0
5.25
Oscillating frequency
__
__
__
External clock mode 1
for display
Horizontal synchronous signal input frequeney
ELECTRICAL CHARACTERISTICS 1
Symbol
VOH
VOL
VTCK
(VDD = 5.00V, Ta = 25°C, unless otherwise noted)
Parameter
Supply voltage
Test conditions
Ta = –20 to +85°C
Supply current
VDD = 5.00V
"H" level output voltage
"L" level output voltage
__
RI
V
AC, CS, HOR, VERT
"L" level input voltage
IDD
Unit
"H" level input voltage
VIL
VDD
Max.
5.25
5V
3V
VIH
H.sync
Limits
Typ.
5.0
Supply voltage
__
FOSC
(VDD = 5.00V, Ta = –20 to +85°C, unless otherwise noted)
P0 to P7 (Note1)
VDD = 4.75V, IOH = -0.4mA
CPOUT
VDD = 4.75V, IOH = -0.05mA
P0 to P7 (Note2)
VDD = 4.75V, IOL = 0.4mA
CPOUT
VDD = 4.75V, IOL = 0.05mA
SIN/SDA
VDD = 4.75V, IOL = 3.0mA
__
Pull-up resistance AC, CS
VDD = 5.00V
External clock input width
4.75V ≤ VDD ≤ 5.25V
Notes 1. The current from the IC must not exceed – 0.4 mA/port at any of the port pins (P0 to P7).
2. The current flowing into the IC must not exceed 0.4 mA/port at any of port pins (P0 to P7).
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 36 of 44
60
Unit
V
mA
—
40
3.5
—
—
V
—
—
0.4
V
10
30
100
kΩ
0.6VDD
—
0.9VDD
V
M35075-XXXFP
ELECTRICAL CHARACTERISTICS 2 VDD=3V (VDD = 3.00V, Ta = 25°C, unless otherwise noted)
Symbol
Parameter
Test conditions
Min.
Limits
Typ.
Max.
2.50
3.00
3.50
V
—
20
30
mA
VDD
Supply voltage
Ta = –20 to +85°C
IDD
Supply current
VDD = 3.00V
VOH
“H” level output voltage
VDD = 2.70V, IOH = -0.1mA
2.30
VOL
RI
P0 to P7 (Note2)
“L” level output voltage
__ __
Pull-up resistance AC, CS
VDD = 2.70V, IOH = 0.1mA
—
—
—
VDD = 3.00V
30
VTCK
External clock input width
2.50V ≤ VDD ≤ 3.50V
0.9VDD
P0 to P7 (Note1)
Notes 1. The current from the IC must not exceed – 0.1 mA/port at any of the port pins (P0 to P7).
2. The current flowing into the IC must not exceed 0.1 mA/port at any of port pins (P0 to P7).
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 37 of 44
Unit
—
V
—
0.4
150
V
kΩ
—
VDD
V
M35075-XXXFP
After supplying the power (VDD and VSS) to M35075-XXXFP
and the supply voltage becomes
more than 0.8 ✕ VDD, it needs
__
to keep VIL time; tw of the AC pin for more
than 1ms.
__
Start inputting from microcomputer after AC pin supply voltage
becomes more than 0.8 ✕ VDD and keeping 200ms wait time.
NOTE FOR SUPPLYING
POWER
__
(1)Timing of power supplying to AC pin
The internal circuit of M35075-XXXFP
is reset when the level of
__
the auto clear input pin AC is "L". This pin in hysteresis input
with the pull-up resistor.
__
The timing about power supplying of AC pin is shown in Figure 29.
(2)Timing of power supplying to VDD1 and VDD2.
Supply power to VDD1 and VDD2 at the same time.
Voltage [V]
Data input disable
VDD
Supply voltage
VAC
(AC pin input voltage)
0.8 x VDD
0.2 x VDD
Time t [s]
tW
tS
more than 1ms
__
Fig.29 Timing of power supplying to AC pin
PRECAUTION FOR USE
DATA REQUIRED FOR MASK ROM
ORDERING
Notes on noise and latch-up
In order to avoid noise and latch-up, connect a bypass capacitor
(≈0.1µF) directly between the V DD1 pin and V SS1 pin, and the
VDD2 pin and VSS2 pin using a heavy wire.
Please send the following data for mask orders.
(1) M35075-XXXFP mask ROM order confirmation form
(2) 24P2Q mark specification form
(3) ROM data : EPROMs or floppy disks
*In the case of EPROMs, thres sets of EPROMs are required
per pattern.
*In the case of floppy disks, 3.5-inch 2HD disk (1BM format) is
required per pattern.
Note for waveform timing of the horizontal signals to the HOR pin
Set horizontal synchronous signal edge* waveform timing to under
5ns and input to HOR pin.
_
Set only the side which set by B/F register waveform timing under
5ns and input to HOR pin.
_
*: Set front porch edge or back porch edge by B/F register.
tf
90%
Horizontal synchronous signal
10%
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 38 of 44
tr
M35075-XXXFP
STANDARD ROM TYPE : M35075-001FP
M35075-001FP is a standard ROM type of M35075-XXXFP.
The character patterns are fixed to the contents of Figure 30 to 33.
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 39 of 44
M35075-XXXFP
0016
0116
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
0E16
0F16
1016
1116
1216
1316
1416
1516
1616
1716
1816
1916
1A16
1B16
1C16
1D16
1E16
1F16
2016
2116
2216
2316
2416
2516
2616
2716
2816
2916
2A16
2B16
2C16
2D16
2E16
2F16
3016
3116
3216
3316
3416
3516
3616
3716
3816
3916
3A16
3B16
3C16
3D16
3E16
3F16
Fig.30 M35075-001FP character patterns (1)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 40 of 44
M35075-XXXFP
4016
4116
4216
4316
4416
4516
4616
4716
4816
4916
4A16
4B16
4C16
4D16
4E16
4F16
5016
5116
5216
5316
5416
5516
5616
5716
5816
5916
5A16
5B16
5C16
5D16
5E16
5F16
6016
6116
6216
6316
6416
6516
6616
6716
6816
6916
6A16
6B16
6C16
6D16
6E16
6F16
7016
7116
7216
7316
7416
7516
7616
7716
7816
7916
7A16
7B16
7C16
7D16
7E16
7F16
Fig.31 M35075-001FP character patterns (2)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 41 of 44
M35075-XXXFP
8016
8116
8216
8316
8416
8516
8616
8716
8816
8916
8A16
8B16
8C16
8D16
8E16
8F16
9016
9116
9216
9316
9416
9516
9616
9716
9816
9916
9A16
9B16
9C16
9D16
9E16
9F16
A016
A116
A216
A316
A416
A516
A616
A716
A816
A916
AA16
AB16
AC16
AD16
AE16
AF16
B016
B116
B216
B316
B416
B516
B616
B716
B816
B916
BA16
BB16
BC16
BD16
BE16
BF16
Fig.32 M35075-001FP character patterns (3)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 42 of 44
M35075-XXXFP
C016
C116
C216
C316
C416
C516
C616
C716
C816
C916
CA16
CB16
CC16
CD16
CE16
CF16
D016
D116
D216
D316
D416
D516
D616
D716
D816
D916
DA16
DB16
DC16
DD16
DE16
DF16
E016
E116
E216
E316
E416
E516
E616
E716
E816
E916
EA16
EB16
EC16
ED16
EE16
EF16
F016
F116
F216
F316
F416
F516
F616
F716
F816
F916
FA16
FB16
FC16
FD16
FE16
FF16blank
Fig.33 M35075-001FP character patterns (4)
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
page 43 of 44
M35075-XXXFP
PACKAGE OUTLINE
MMP
24P2Q-A
EIAJ Package Code
SSOP24-P-300-0.80
Plastic 24pin 300mil SSOP
JEDEC Code
–
Weight(g)
0.2
24
Lead Material
Cu Alloy
e
b2
E
HE
e1
I2
13
F
Recommended Mount Pad
Symbol
1
12
A
D
G
A2
e
b
L
L1
y
A1
c
z
Z1
Rev.1.10 Feb 13, 2006
REJ03B0180-0110
Detail G
page 44 of 44
Detail F
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
2.1
–
–
0.2
0.1
0
–
1.8
–
0.45
0.35
0.3
0.25
0.2
0.18
10.2
10.1
10.0
5.4
5.3
5.2
–
0.8
–
8.1
7.8
7.5
0.8
0.6
0.4
–
1.25
–
–
0.65
–
–
–
0.8
0.1
–
–
0°
–
8°
–
0. 5
–
–
7.62
–
–
1.27
–
REVISION HISTORY
Rev.
M35075-XXXFP
Date
Description
Summary
Page
1.00 Mar 01, 2002
-
First edition issued
1.10 Feb 13, 2006
P36
"RECOMMENDED OPERATING CONDITIONS" and
P37
"ELECTRICAL CHARACTERISTICS 1" are changed.
"ELECTRICAL CHARACTERISTICS 2" is changed.
A- 1