19-4736; Rev 0; 7/09 Integrated Powerline Communication Analog Front-End Transceiver and Line Driver Features The MAX2981 powerline communication analog frontend (AFE) and line-driver IC is a state-of-the-art CMOS device that delivers high performance at low cost. This highly integrated design combines an analog-to-digital converter (ADC), digital-to-analog converter (DAC), adaptive gain control (AGC), filters, and line driver on a single chip. The MAX2981 substantially reduces previously required system components and complies with the HomePlug® 1.0 standard. Combined with Maxim’s integrated PHY/MAC digital baseband, the device delivers the most flexible and cost-effective solution. The advanced design of the MAX2981 allows operation without external control, enabling simplified connection to a variety of HomePlug 1.0 digital PHY ICs. o HomePlug 1.0 Compliant The MAX2981 is specified over the -40°C to +105°C automotive temperature range and is offered in a 64-pin lead-free LQFP package. The device is qualified to the AEC-Q100 Rev F automotive standard. o AEC-Q100 Rev F (Automotive) Qualified o Fully Integrated AFE and Line Driver o Fully Compatible with the MAX2982/MAX2986 o Pin-to-Pin Compatible with the MAX2980 o Seamless Interface to Third-Party PHY ICs o Fully Integrated, 10-Bit, 50Msps ADC and DAC o 56dB Adaptive Gain Control o Line Impedance Drive Capability as Low as 10Ω o Line-Driver Bypass Mode o 220mA in Rx Mode and 150mA in Tx Mode at 3.3V o -40°C to +105°C Operating Temperature Range o 64-Pin LQFP Package Ordering Information PART TEMP RANGE PIN-PACKAGE MAX2981GCB/V+ -40°C to +105°C 64 LQFP Applications Local Area Networking (LAN) Broadband-over-Powerline (BPL) /V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant part. Remote Monitoring and Control Pin Configuration Energy Management ENTX AVDD I.C. I.C. AGND AGND AVDD AVDD AGND AGND FREEZE DGND DVDD 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AGND 1 48 DAD0 AVDD 2 47 DGND PLIP 3 46 DAD1 PLIN 4 45 DAD2 AGND 5 44 DVDD3 AVDD 6 43 DAD3 CEXT 7 42 DAD4 REXT 8 41 DVDD3 AGND 9 40 DGND AGND 10 39 DAD5 PLOP 11 38 DAD6 AVDD 12 37 DVDD3 AGND 13 36 DAD7 PLON 14 35 DAD8 AVDD 15 34 DGND AVDD 16 33 DAD9 SCLK SHRCV 26 27 28 29 30 31 32 AGND SDIO 25 CLK DGND 24 DVDD3 23 AVDD 22 AGND 21 DGND 20 DVDD 19 CS 18 ENREAD 17 DVDD MAX2981 AGND HomePlug is a registered trademark of HomePlug Powerline Alliance, Inc. 64 + REGOUT Typical Operating Circuit appears at end of data sheet. SWR IPTV Distribution RESET Building Automation STBY Industrial Automation LQFP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2981 General Description MAX2981 Integrated Powerline Communication Analog Front-End Transceiver and Line Driver ABSOLUTE MAXIMUM RATINGS AVDD to AGND .....................................................-0.3V to +3.9V DVDD3 to DGND ...................................................-0.3V to +3.9V DVDD to DGND .....................................................-0.3V to +2.8V AGND to DGND.....................................................-0.3V to +0.3V All Other Pins..............................................-0.3V to (VDD + 0.3V) Current into Any Pin........................................................±100mA Short-Circuit Duration (VREGOUT to AGND) ........................10ms Continuous Power Dissipation (TA = +70°C) 64-Pin LQFP (derate 25mW/°C above +70°C)...........2000mW Operating Temperature Range .........................-40°C to +105°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-40°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE ELECTRICAL CHARACTERISTICS (VAVDD = VDVDD3 = +3.3V, DVDD = REGOUT, VAGND = VDGND = VSHRCV = 0V, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Analog Supply Voltage VAVDD 3.0 3.6 V Digital Supply Voltage VDVDD3 3.0 3.6 V Digital Supply Voltage VDVDD Quiescent Supply Current IAVDD Standby Supply Current Regulator Output (Note 2) 2.4 Receive mode, transmitter disabled, no signal applied 220 Transmit mode, receiver disabled, no signal and no load applied 150 V mA No clock 6 VREGOUT 2.4 Output-Voltage High VOH ISOURCE = 5mA Output-Voltage Low VOL ISINK = 5mA mA V 2.4 V 0.4 V LOGIC INPUT Input High Voltage VIH Input Low Voltage VIL Input Leakage Current 2.0 V 0.8 IIH VIH = VDVDD IIL VIL = 0V +5 -5 V µA ANALOG-TO-DIGITAL CONVERTER (ADC) Resolution 10 Bits Integral Nonlinearity INL N (Note 3) 2.3 LSB Differential Nonlinearity DNL 0.8 LSB Two-Tone 3rd-Order Distortion IM3 -51.5 dBc Two tones at 17MHz and 18MHz at input 1VP-P differential voltage DIGITAL-TO-ANALOG CONVERTER (DAC) Resolution 10 Bits Integral Nonlinearity INL 0.5 LSB Differential Nonlinearity DNL 0.4 LSB Two-Tone 3rd-Order Distortion IM3 -54 dBc 2 N (Note 3) Two tones at 17MHz and 18MHz at output 1VP-P differential voltage _______________________________________________________________________________________ Integrated Powerline Communication Analog Front-End Transceiver and Line Driver (VAVDD = VDVDD3 = +3.3V, DVDD = REGOUT, VAGND = VDGND = VSHRCV = 0V, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS RECEIVER Common-Mode Voltage Input Impedance ZIN Between PLIP or PLIN and 0V at 12MHz (Note 3) Two-Tone 3rd-Order Distortion IM3 Two tones at 17MHz and 18MHz at input 1VP-P differential voltage Receiver Gain Range Rx 1.6 V 875 Ω -52 dBc 56 dB Lowpass Filter -3dB Corner Frequency (Note 3) 23 MHz Lowpass Filter Ripple (Note 3) 2.6 dB Highpass Filter -3dB Corner Frequency (Note 3) 2.4 MHz 1.6 V Between PLOP/PLON and 0V at 12.5MHz (Note 3) 3 Ω Predriver gain = -6dB at 12.5MHz, VP-P at 10Ω single-ended output load 1.4 Predriver gain = 3dB at 12.5MHz, VP-P at 10Ω single-ended output load 4 TRANSMITTER Common-Mode Voltage Output Impedance ZOUT VP-P Output Voltage Swing Line driver in bypass mode, predriver gain = 3dB; at 50Ω single-ended output load 1.4 Two tones at 17MHz and 18MHz -50 Lowpass Filter -3dB Corner Frequency (Note 3) 23 MHz Lowpass Filter Ripple (Note 3) 2.6 dB Minimum Line Impedance Drive Capability Single-ended output 10 Ω Predriver Line Impedance Capability Line driver is in bypass mode, single-ended output 50 Ω Predriver Output Voltage Swing Two-Tone 3rd-Order Distortion IM3 VP-P -35 dBc TIMING CHARACTERISTICS CLK Frequency 50 MHz CLK Fall to ADC Data Output tADCO 2 ns CLK Fall to DAC Data Latch Time tDACI 3 ns Note 1: Min and max values are guaranteed by design and characterization at TA = -40°C and production tested at TA = +25°C and +105°C. Typical values are tested functionally at TA = +25°C. Note 2: Bypass internal 2.4V regulator with 0.1µF capacitor to DGND. Note 3: Typical values are guaranteed by design at TA = +25°C. _______________________________________________________________________________________ 3 MAX2981 ELECTRICAL CHARACTERISTICS (continued) MAX2981 Integrated Powerline Communication Analog Front-End Transceiver and Line Driver Pin Description PIN NAME 1, 5, 9, 10, 13, 17, 28, 32, 52, 53, 56, 57 AGND Analog Ground 2, 6, 12, 15, 16, 29, 54, 55, 60 AVDD Analog Power-Supply Voltage. AVDD supply range is 3.0V to 3.6V. Bypass AVDD with a 0.1µF capacitor to AGND. 4 FUNCTION 3 PLIP AC Powerline Positive Input 4 PLIN AC Powerline Negative Input 7 CEXT External Capacitor Connection. Connect a 10nF capacitor from CEXT to AGND. 8 REXT External Resistor Connection. Connect a 25kΩ resistor from REXT to AGND. 11 PLOP AC Powerline Positive Output 14 PLON AC Powerline Negative Output 18 REGOUT Voltage Regulator Output. Connect REGOUT to DVDD for normal operation. 19, 26, 49 DVDD Digital 2.4V Voltage Input. Connect DVDD to REGOUT for normal operation. 20, 27, 34, 40, 47, 50 DGND Digital Ground 21 SDIO Serial Data Input/Output 22 SCLK Serial Clock Input 23 SHRCV 24 ENREAD 25 CS 30, 37, 41, 44 DVDD3 31 CLK 33 DAD9 DAC/ADC Input/Output MSB Data Bit. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 35 DAD8 DAC/ADC Input/Output Data Bit 8. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. Receiver Shutdown Control. Drive SHRCV high to power down the receiver. Drive low for normal operation. Read-Mode Enable Control. Drive ENREAD high to place the DAD[9:0] bidirectional buffers in read mode. Data is transferred from the digital PHY to the AFE DAC. ENREAD signal frames the transmission. Active-High Carrier-Select Input. Drive CS high to initiate the internal timer. Digital Power-Supply Voltage. DVDD3 supply range is 3.0V to 3.6V. Bypass DVDD3 to DGND with a 0.1µF capacitor as close as possible to the pin. 50MHz System Clock Input _______________________________________________________________________________________ Integrated Powerline Communication Analog Front-End Transceiver and Line Driver PIN NAME 36 DAD7 DAC/ADC Input/Output Data Bit 7. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 38 DAD6 DAC/ADC Input/Output Data Bit 6. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 39 DAD5 DAC/ADC Input/Output Data Bit 5. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 42 DAD4 DAC/ADC Input/Output Data Bit 4. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 43 DAD3 DAC/ADC Input/Output Data Bit 3. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 45 DAD2 DAC/ADC Input/Output Data Bit 2. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 46 DAD1 DAC/ADC Input/Output Data Bit 1. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 48 DAD0 DAC/ADC Input/Output LSB Data Bit. Input/output of 10-bit, 50MHz bidirectional digital-to-analog and analog-to-digital converter. Data is in binary format. 51 FREEZE 58, 59 I.C. 61 ENTX 62 SWR 63 RESET 64 STBY FUNCTION Active-High Freeze-Mode Enable. Drive FREEZE high to place the adaptive gain control (AGC) in freeze mode. Drive FREEZE low if the the signal is not available for the companion baseband chip. Internally Connected. Leave these pins unconnected. Active-High Transmit Enable. Drive ENTX high to enable the transmitter. Drive ENTX low to place the transmitter in three-state. Active-High Register Write Enable. Drive SWR high to place the registers in write mode. Active-Low Reset Input. Drive RESET low to place the MAX2981 in reset mode. Set CLK in freerunning mode during a reset. The minimum reset pulse width is 100ns. Active-High Standby Input. Drive STBY high to place the MAX2981 in standby mode. Drive low for normal operation. _______________________________________________________________________________________ 5 MAX2981 Pin Description (continued) Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981 Functional Diagram MAX2981 PLIP LPF VGA HPF AGC ADC PLIN MUX DAD[9:0] PLOP LD BUF LPF DAC PLON Detailed Description The MAX2981 powerline communication AFE and linedriver IC is a state-of-the-art CMOS device that delivers high performance at low cost. This highly integrated design combines an ADC, DAC, AGC, filters, and line driver on a single chip as shown in the Functional Diagram. The MAX2981 substantially reduces previously required system components and complies with the HomePlug 1.0 standard. Combined with Maxim’s integrated PHY/MAC digital baseband, the device delivers the most flexible and cost-effective solution. The advanced design of the MAX2981 allows operation without external control, enabling simplified connection to a variety of HomePlug 1.0 digital PHY ICs. Receive Channel The receiver analog front-end consists of a variablegain amplifier (VGA), a lowpass filter (LPF), a highpass filter (HPF), and an AGC circuit. An ADC block samples the AGC output. The ADC communicates to the digital PHY chip through a mux block. The VGA reduces the receive channel input-referred noise by providing some signal gain to the AFE input. The filter blocks remove unwanted noise, and provide the anti-aliasing required by the ADC for accurate sampling. The AGC scales the signal for conversion from analog to digital. The scaling maintains the optimum signal level at the ADC input and keeps the AGC amplifiers out of saturation. The 10-bit ADC samples the analog signal at 50Msps and converts it to a 10-bit digital stream. The block fully 6 integrates reference voltages and biasing for the input differential signal. Transmit Channel The transmit channel consists of a 10-bit DAC, a LPF, and an adjustable-gain transmitter buffer and line driver. The DAC receives the data stream from the digital PHY IC through the mux block. The 50MHz, 10-bit DAC provides the complementary function to the receive channel. The DAC converts the 10bit digital stream to an analog voltage at a 50MHz rate. The LPF removes spurs and harmonics adjacent to the desired passband to help reduce the out-of-band transmitted frequencies and energy from the DAC output. The transmit buffer and line-driver blocks allow the output level of the LPF to obtain a level necessary to connect directly to the powerline medium, without the use of external amplifiers and buffers. The output level is adjustable from 1.4VP-P to 4.0VP-P differential. The line driver can drive resistive loads as low as 10Ω singleended. Line Driver Bypass Use register R6B[2:1] to bypass the line driver. With the line driver bypassed, the output can drive a 50Ω singleended external load. Digital Interface The digital interface is composed of control signals and a 10-bit bidirectional data bus for the DAC and ADC. The control signals include a reset line, a transmit request, an I/O direction request, and a receiver shutdown control. _______________________________________________________________________________________ Integrated Powerline Communication Analog Front-End Transceiver and Line Driver Read Enable (ENREAD) The ENREAD line sets the direction of the data bus DAD[9:0]. With ENREAD high, data is sent from the digital PHY to the DAC in the MAX2981 AFE. A low on ENREAD sends data from the ADC to the digital PHY. Receiver Power-Down (SHRCV) The SHRCV line provides receiver shutdown control. A logic-high on SHRCV powers down the receiver section of the MAX2981 whenever the device is transmitting. The MAX2981 also features a transmit power-saving mode, which reduces supply current from 350mA to 150mA. To enter the transmit power-saving mode, drive SHRCV high 0.1µs prior to the end of transmission. Connect SHRCV to ENTX and ENREAD for normal operation. Digital-to-Analog and Analog-to-Digital Converter Input/Output (DAD[9:0]) DAD[9:0] is the 10-bit bidirectional bus connecting the digital PHY to the MAX2981 DAC and ADC. The bus direction is controlled by ENREAD, as described in the Read Enable (ENREAD) section. AGC Control Signal (CS) The CS signal controls the AGC circuit of the receive path in the MAX2981. A logic-low on CS sets the gain circuit on the input signal to continuously adapt for maximum sensitivity. A valid preamble detected by the digital PHY raises CS to high. While CS is high, the AGC continues to adapt for an additional 8µs; then the AGC locks the currently adapted level on the incoming signal. The digital PHY holds CS high while receiving a transmission, and then lowers CS for continuous adaptation for maximum sensitivity of other incoming signals. AGC Freeze Mode (FREEZE) Use the FREEZE signal to instantly lock the AGC gain. Clock (CLK) The CLK signal provides all timing for the MAX2981. Apply a 50MHz clock to this input. See the timing diagram (Figure 1) for more information. Reset Input (RESET) The RESET signal provides reset control for the MAX2981. To perform a reset, set CLK in free-running MAX2981 Control Signals Transmit Enable (ENTX) The ENTX line enables the transmitter of the MAX2981 AFE circuit. With ENTX and ENREAD driven high, data sent to the DAC through DAD[9:0] is conditioned and delivered onto the power line. tCLK 50MHz CLK tADCO ADC DATA OUT tDACI DAC DATA INPUT Figure 1. ADC and DAC Timing Diagram mode and drive RESET low for a minimum of 100ns. Always perform a reset at power-up. Standby Control (STBY) The MAX2981 features a low-power, shutdown mode that is activated by STBY. Drive STBY high to place the MAX2981 in standby mode. In standby, the MAX2981 consumes only 20mA with a clock and 5mA without a clock. MAX2981 Control Registers MAX2981 Serial Interface The 3-wire serial interface controls the MAX2981 operation mode. The SCLK is the serial clock line for register programming. The SDIO is the I/O serial data input and output for register writing or reading. The SWR signal controls the write/read mode of the serial interface. If SWR is high, the serial interface is in write mode and a new value can be written into the MAX2981 registers. Following SWR low-to-high transitions, data is shifted synchronously (LSB first) to registers on the falling edge of the serial clock (SCLK) as illustrated in Figure 2. Note that one extra clock (WR_CLK) is required to write the content of holding the buffer to the appropriate register bank. If SWR is low, the serial interface is in read mode and the value of the current register can be read. The read operation to a specific register must be followed immediately after writing to the same register. Following SWR high-to-low transitions, data is shifted synchronously (LSB first) to registers on the falling edge of the serial clock (SCLK) as illustrated in Figure 3. The MAX2981 has a set of six read/write registers; bits A2, A1, A0 are the register address bits. _______________________________________________________________________________________ 7 MAX2981 Integrated Powerline Communication Analog Front-End Transceiver and Line Driver SWR SWR SDAT D0 D1 D2 D15 A0 A1 D0 SDAT A2 D1 D2 D12 D13 D14 D15 WR_CLK SCLK SCLK Figure 2. Writing Mode Register Timing Diagram Figure 3. Reading Mode Register Timing Diagram Table 1. Register Addresses REGISTER A2 A1 A0 R1 (R/W) 0 0 0 R2 (R/W) 0 0 1 R3 (R/W) 0 1 0 R4 (R/W) 0 1 1 R5 (R/W) 1 0 0 R6 (R/W) 1 0 1 MAX2981 AFE Register Maps Table 2. Register R1 Map REGISTER BIT NO. DEFAULT R1B0 High Active high, powers down the receiver when in transmit mode. R1B1 High Active high, powers down the transmitter when in receive mode. R1B2 Low Active high, powers down the DAC when in receive mode. R1B3 Low Active high, powers down the entire device. R1B4 Low Reserved. R1B5 Low Reserved. R1B6 Low Reserved. R1B7 Low Reserved. R1B8 Low Reserved. R1B9 Low Reserved. R1B10 Low Reserved. R1B11 Low Reserved. R1B12 Low Reserved. R1B13 Low Reserved. R1B14 Low Reserved. R1B15 Low Reserved. 8 COMMENT _______________________________________________________________________________________ Integrated Powerline Communication Analog Front-End Transceiver and Line Driver MAX2981 Table 3. Register R2 Map REGISTER BIT NO. DEFAULT COMMENT R2B0 Low Reserved. R2B1 Low Reserved. R2B2 Low Reserved. R2B3 High Reserved. R2B4 Low Reserved. R2B5 Low Reserved. R2B6 Low Reserved. R2B7 Low Reserved. R2B8 Low Reserved. R2B9 Low Reserved. R2B10 Low Reserved. R2B11 Low Reserved. R2B12 Low Reserved. R2B13 Low Reserved. R2B14 Low Reserved. R2B15 Low Active high, bypass the receive LPF. Table 4. Register R3 Map REGISTER BIT NO. DEFAULT R3B0 Low R3B1 Low R3B2 Low R3B3 Low R3B4 Low R3B5 Low R3B6 Low R3B7 Low R3B8 Low R3B9 Low R3B10 Low COMMENT Reserved. These set the predriver gain as follows setting 000 to 111: 3dB, 2dB, 1dB, 0dB, -1dB, -2dB, -3dB, -6dB R3B2 is the LSB. Reserved. R3B11 High Active high, place process tune in continuous mode. Otherwise active only during reset. R3B[15:12] 0111 Reserved. _______________________________________________________________________________________ 9 MAX2981 Integrated Powerline Communication Analog Front-End Transceiver and Line Driver Table 5. Register R4 Map REGISTER BIT NO. DEFAULT COMMENT R4B0 Low Reserved. R4B1 High Reserved. R4B2 High Reserved. R4B3 High Reserved. R4B4 Low Reserved. R4B5 Low Reserved. R4B[10:6] 01011 Reserved. R4B11 High Reserved. R4B12 High Reserved. R4B13 High Reserved. R4B14 R4B15 High Low Reserved. Reserved. Table 6. Register R5 Map REGISTER BIT NO. DEFAULT R5B[6:0] Low Reserved. COMMENT R5B[12:7] Low Reserved. R5B13 Low Reserved. R5B14 Low Reserved. R5B15 Low Reserved. Table 7. Register R6 Map REGISTER BIT NO. DEFAULT R6B0 Low R6B[2:1] 00 R6B3 Low Reserved. R6B4 Low Active high, allow bypass of transmit LPF. 10 R6B[6:5] 00 R6B7 Low R6B8 Low R6B9 Low R6B[11:10] 10 R6B[13:12] 00 COMMENT Reserved. 00 internal LD active; 01 internal LD bypassed external load up to 1kΩ and predriver current consumption 21mA; 11 internal LD bypassed external load 50Ω and predriver current consumption 42mA. Reserved. R6B14 High Disable receiver highpass filter. R6B15 High Reserved. ______________________________________________________________________________________ Integrated Powerline Communication Analog Front-End Transceiver and Line Driver Interfacing to Digital PHY Circuit The MAX2981 interfaces to the MAX2982/MAX2986 digital baseband IC using a bidirectional bus to pass the digital data to and from the DAC and ADC. Handshake lines help accomplish the data transfer and operation of the MAX2981. The application circuit diagram of Figure 4 shows the connection of the MAX2981 to the MAX2982/MAX2986 digital baseband chip. Layout Considerations A properly designed PCB is an essential part of any high-speed circuit. Use controlled-impedance lines on all frequency inputs and outputs. Use low-inductance connections to ground on all ground pins and wherever the components are connected to ground. Place decoupling capacitors close to all VDD connections. For proper operation, connect the metal exposed paddle at the back of the IC to the PCB ground plane with multiple vias. DAD[9:0] MAX2981 ENREAD* ENTX* MAX2982/MAX2986 PLIP SHRCV CS POWERLINE HOT PLIN POWERLINE INTERFACE NEUTRAL SCLK HOST INTERFACES SWR PLOP PLON SDI0 50MHz CLK RESET STBY *SIGNALS CAN BE CONNECTED TO ONE CONTROL LINE. CLOCK Figure 4. Interfacing the MAX2981 to the MAX2982/MAX2986 ______________________________________________________________________________________ 11 MAX2981 Applications Information MAX2981 Integrated Powerline Communication Analog Front-End Transceiver and Line Driver Typical Operating Circuit VDD 3 22nF 1:1 1 162Ω L VDD HPF RECEIVER 10nF POWERLINE SPARK GAP 10nF 162Ω 22nF 10nF* N 2 4 VDD 10Ω 5kΩ DRIVER 100nF 10nF 5kΩ 560pF MAX2981 3 1 4 2 270pF 6.8µH 5.6µH 4 2 560pF 220pF 270pF Chip Information PROCESS: CMOS *10nF CAPACITOR ON NEUTRAL IS OPTIONAL 1 = HPF 220pF 3 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 64 LQFP C64+1 21-0083 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.