P4C165 ULTRA HIGH SPEED 8K x 8 RESETTABLE STATIC CMOS RAM FEATURES Full CMOS, 6T Cell Output Enable and Dual Chip Enable Control Functions High Speed (Equal Access and Cycle Times) – 15/20/25 ns (Commercial) – 20/25/35 (Industrial) Single 5V±10% Power Supply Low Power Operation Fully TTL Compatible Inputs and Outputs Chip Clear Function Standard Pinout (JEDEC Approved) – 28-Pin Plastic DIP (300 mil) Common Data I/O DESCRIPTION The P4C165 is a 65,536-bit ultra high-speed static RAM organized as 8K x 8. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing and has equal access and cycle times. Inputs are fully TTLcompatible. The RAM operates from a single 5V±10% tolerance power supply. Access times as fast as 15 nanoseconds are available, permitting greatly enhanced system operating speeds. In full standby mode with CMOS inputs, power consumption is only 5.5 mW for the P4C165. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION The P4C165 is available in a 28-pin 300 mil DIP. 1519B DIP (P5) Document # SRAM117 Rev OR 1 Revised October 2005 P4C165 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Parameter Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) VCC = 5.0V, TA = 25°C, f = 1.0MHz Grade(2) Ambient Temperature GND VCC Symbol Commercial Industrial 0°C to +70°C –40°C to +85°C 0V 0V 5.0V ± 10% 5.0V ± 10% CIN COUT Parameter Input Capacitance Output Capacitance Conditions Typ. Unit VIN = 0V 5 pF VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter P4C165 Min Max Test Conditions Unit VIH Input High Voltage 2.2 VCC +0.5 V VIL Input Low Voltage –0.5(3) 0.8 V V HC CMOS Input High Voltage VLC CMOS Input Low Voltage V CD Input Clamp Diode Voltage VOL Output Low Voltage (TTL Load) Output High Voltage (TTL Load) VOH ILI Input Leakage Current ILO Output Leakage Current ISB Standby Power Supply Current (TTL Input Levels) ISB1 Standby Power Supply Current (CMOS Input Levels) VCC –0.2 VCC +0.5 V 0.2 V VCC = Min., IIN = –18 mA –1.2 V IOL = +8 mA, VCC = Min. 0.4 V –0.5 (3) IOH = –4 mA, VCC = Min. 2.4 V VCC = Max. VIN = GND to VCC Ind./Com’l. –5 +5 µA Ind./Com’l. –5 +5 µA Ind./Com’l. ___ 30 mA Ind./Com’l. ___ 15 mA VCC = Max., CE = VIH, VOUT = GND to VCC CE ≥ VIH or CE2 ≤VIL, VCC= Max f = Max., Outputs Open CE ≥ VHC or CE2 ≤VLC, VCC= Max f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. Document # SRAM117 Rev OR 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 2 Page 2 of 9 P4C165 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter ICC Dynamic Operating Current* –15 –20 –25 –35 Unit Commercial 160 155 150 N/A mA Industrial N/A 160 155 150 mA Temperature Range *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE1 = VIL, CE2 = VIH, OE = VIH AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) -15 -20 -25 -35 Sym. Parameter t RC Read Cycle Time tAA Address Access Time 15 20 25 35 ns tAC Chip Enable Access Time 15 20 25 35 ns t OH Output Hold from Address Change 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 2 2 2 2 ns t HZ Chip Disable to Output in High Z 8 8 10 15 ns tOE Output Enable Low to Data Valid 9 10 13 18 ns Min Max Min Max Min Max Min Max 15 tOLZ Output Enable Low to Low Z 2 Chip Enable to Power Up Time t PD Chip Disable to Power Down Time Document # SRAM117 Rev OR 0 3 2 9 0 15 35 25 2 9 tOHZ Output Enable High to High Z t PU 20 0 20 ns 2 12 ns 15 ns ns 0 20 Unit 20 ns Page 3 of 9 P4C165 OE CONTROLLED)(5) READ CYCLE NO. 1 (OE READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6) CE1, CE2 CONTROLLED)(5,7,10) READ CYCLE NO. 3 (CE Notes: 5. WE is HIGH for READ cycle. 6. CE1 is LOW, CE2 is HIGH and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE1 transition LOW and CE2 transition HIGH. 8. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. Document # SRAM117 Rev OR 9. READ Cycle Time is measured from the last valid address to the first transitioning address. 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE1 or CE2 causes them. 4 Page 4 of 9 P4C165 AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. -15 Parameter -25 -20 -35 Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 15 20 25 35 ns tCW Chip Enable Time to End of Write 12 15 18 25 ns tAW Address Valid to End of Write 12 15 18 25 ns tAS Address Set-up Time 0 0 0 0 ns tWP Write Pulse Width 12 15 18 20 ns tAH Address Hold Time 0 0 0 0 ns tDW Data Valid to End of Write 9 11 13 15 ns tDH Date Hold Time 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 7 3 8 3 10 3 14 3 ns ns WE CONTROLLED)(11) WRITE CYCLE NO. 1 (WE Notes: 11. CE1 and WE must be LOW, and CE2 HIGH for WRITE cycle. 12. OE is LOW for this WRITE cycle to show tWZ and tOW. 13. If CE1 goes HIGH, or CE2 goes LOW, simultaneously with WE HIGH, the output remains in a high impedance state. Document # SRAM117 Rev OR 14. Write Cycle Time is measured from the last valid address to the first transitioning address. 5 Page 5 of 9 P4C165 CE CONTROLLED)(11) TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE AC CHARACTERISTICS—CLEAR CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym. tCLCL -15 Parameter -20 -25 -35 Min Max Min Max Min Max Min Max Unit CLEAR Cycle Time 30 40 50 70 ns tCLPW CLEAR Pulse Width 12 15 15 20 ns tCLIX CLEAR Low to Inputs Don't Care 0 0 0 0 ns tCLIR CLEAR Low to Inputs Recognized 30 40 50 70 ns TIMING WAVEFORM OF CLEAR CYCLE Document # SRAM117 Rev OR 6 Page 6 of 9 P4C165 AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Input Rise and Fall Times 3ns Input Timing Reference Level 1.5V Output Timing Reference Level Output Load 1.5V See Figures 1 and 2 CLEAR CE1 Mode CE2 OE WE I/O Power Reset L X X X X --- Active Standby H H X X X High Z Standby Standby H X L X X High Z Standby Output Disabled H L H H H High Z Active Read H L H L H DOUT Active Write H L H X L High Z Active Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C165, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. To avoid signal Document # SRAM117 Rev OR reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 7 Page 7 of 9 P4C165 ORDERING INFORMATION SELECTION GUIDE The P4C165 is available in the following temperature, speed and package options. Temperature Range Package Speed 15 20 25 35 Commercial Plastic DIP -15PC -20PC -25PC -35PC Industrial Plastic DIP -15PI -20PI -25PI -35PI Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α P5 PLASTIC DUAL IN-LINE PACKAGE 28 (300 mil) Min Max 0.210 0.014 0.023 0.045 0.070 0.008 0.014 1.345 1.400 0.270 0.300 0.300 0.380 0.100 BSC 0.430 0.115 0.150 0° 15° Document # SRAM117 Rev OR 8 Page 8 of 9 P4C165 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM117 P4C165 ULTRA HIGH SPEED 8K x 8 RESETTABLE STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE OR Oct-05 JDB Document # SRAM117 Rev OR DESCRIPTION OF CHANGE New Data Sheet 9 Page 9 of 9