PCA9672 Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset Rev. 02 — 6 July 2007 Product data sheet 1. General description The PCA9672 provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C-bus) and is a part of the Fast-mode Plus family. The PCA9672 is a drop-in upgrade for the PCF8574 providing higher Fast-mode Plus (Fm+) I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without the need for bus buffers, higher total package sink capacity (200 mA versus 100 mA) that supports having all LEDs on at the same time and more device addresses (16 versus 8) are available to allow many more devices on the bus without address conflicts. The difference between the PCA9672 and the PCF8574 is that the A2 address pin is replaced by the RESET input on the PCA9672. The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCA9672 has low current consumption and include latched outputs with 25 mA high current drive capability for directly driving LEDs. The PCA9672 possesses an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. The internal Power-On Reset (POR), hardware reset pin (RESET), or Software Reset sequence initializes the I/Os as inputs. 2. Features n n n n n n n n n n 1 MHz I2C-bus interface Compliant with the I2C-bus Fast and Standard modes SDA with 30 mA sink capability for 4000 pF buses 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 8-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 200 mA Active LOW open-drain interrupt output 16 programmable slave addresses using 2 address pins Readable device ID (manufacturer, device type, and revision) PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset n Low standby current n −40 °C to +85 °C operation n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA n Packages offered: SO16, TSSOP16, HVQFN16 3. Applications n n n n n n n n LED signs and displays Servers Industrial control Medical equipment PLCs Cellular telephones Gaming machines Instrumentation and test measurement 4. Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PCA9672BS 672 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 × 3 × 0.85 mm SOT758-1 PCA9672D PCA9672D SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PCA9672PW PCA9672 TSSOP16 PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 2 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 5. Block diagram PCA9672 INTERRUPT LOGIC INT LP FILTER AD0 AD1 SCL SDA I2C-BUS CONTROL INPUT FILTER RESET VDD VSS SHIFT REGISTER I/O PORT 8 BITS P0 to P7 write pulse read pulse POWER-ON RESET 002aac321 Fig 1. Block diagram of PCA9672 write pulse 100 µA VDD IOH Itrt(pu) data from Shift Register D Q FF P0 to P7 IOL CI S power-on reset VSS D Q FF read pulse CI S to interrupt logic data to Shift Register 002aac109 Fig 2. Simplified schematic diagram of P0 to P7 PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 3 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 6. Pinning information 6.1 Pinning AD0 1 1 2 16 VDD 15 SDA AD0 AD1 AD1 2 16 VDD 15 SDA RESET 3 14 SCL RESET 3 14 SCL P0 4 13 INT P0 4 P1 5 12 P7 P1 5 P2 6 11 P6 P2 6 11 P6 P3 7 10 P5 P3 7 10 P5 VSS 8 9 VSS 8 PCA9672D P4 PCA9672PW 13 INT 12 P7 9 002aac322 P4 002aac323 RESET 1 P0 2 13 SDA 14 VDD terminal 1 index area 15 AD0 Fig 4. Pin configuration for TSSOP16 16 AD1 Fig 3. Pin configuration for SO16 12 SCL 11 INT PCA9672BS 7 8 P5 9 P4 4 6 P2 VSS 10 P7 5 3 P3 P1 P6 002aac325 Transparent top view Fig 5. Pin configuration for HVQFN16 6.2 Pin description Table 2. Symbol Pin description Pin Description SO16, TSSOP16 HVQFN16 AD0 1 15 address input 0 AD1 2 16 address input 1 RESET 3 1 reset input (active LOW) P0 4 2 quasi-bidirectional I/O 0 P1 5 3 quasi-bidirectional I/O 1 P2 6 4 quasi-bidirectional I/O 2 P3 7 5 quasi-bidirectional I/O 3 VSS 8 6[1] supply ground P4 9 7 quasi-bidirectional I/O 4 P5 10 8 quasi-bidirectional I/O 5 P6 11 9 quasi-bidirectional I/O 6 PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 4 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset Table 2. Symbol Pin description …continued Pin Description SO16, TSSOP16 HVQFN16 P7 12 10 quasi-bidirectional I/O 7 INT 13 11 interrupt output (active LOW) SCL 14 12 serial clock line SDA 15 13 serial data line VDD 16 14 supply voltage [1] HVQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. 7. Functional description Refer to Figure 1 “Block diagram of PCA9672”. 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9672 is shown in Figure 6. Slave address pins AD1 and AD0 choose 1 of 16 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and AD0. Address values depending on AD1 and AD0 can be found in Table 3 “PCA9672 address map”. Remark: When using the PCA9672 reserved I2C-bus addresses must be used with caution since they can interfere with: • “reserved for future use” I2C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111) • slave devices that use the 10-bit addressing scheme (1111 0xx) • High speed mode (Hs-mode) master code (0000 1xx) slave address A6 A5 A4 A3 A2 programmable A1 A0 R/W 002aab636 Fig 6. PCA9672 address The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. When AD1 and AD0 are held to VDD or VSS, the same address as the PCF8574 with A2 held to VSS is applied. PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 5 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 7.1.1 Address map Table 3. PCA9672 address map AD1 AD0 A6 A5 A4 A3 A2 A1 A0 Address SCL VSS 0 0 1 0 0 0 0 20h SCL VDD 0 0 1 0 0 0 1 22h SDA VSS 0 0 1 0 0 1 0 24h SDA VDD 0 0 1 0 0 1 1 26h SCL SCL 0 0 1 1 0 0 0 30h SCL SDA 0 0 1 1 0 0 1 32h SDA SCL 0 0 1 1 0 1 0 34h SDA SDA 0 0 1 1 0 1 1 36h VSS VSS 0 1 0 0 0 0 0 40h VSS VDD 0 1 0 0 0 0 1 42h VDD VSS 0 1 0 0 0 1 0 44h VDD VDD 0 1 0 0 0 1 1 46h VSS SCL 0 1 0 1 0 0 0 50h VSS SDA 0 1 0 1 0 0 1 52h VDD SCL 0 1 0 1 0 1 0 54h VDD SDA 0 1 0 1 0 1 1 56h 7.2 Software Reset Call, and device ID addresses Two other different addresses can be sent to the PCA9672. • General Call address: allows to reset the PCA9672 through the I2C-bus upon reception of the right I2C-bus sequence. See Section 7.2.1 “Software Reset” for more information. • Device ID address: allows to read ID information from the device (manufacturer, part identification, revision). See Section 7.2.2 “Device ID (PCA9672 ID field)” for more information. R/W 0 0 0 0 0 0 0 0 002aac115 Fig 7. General Call address 1 1 1 1 1 0 0 R/W 002aac116 Fig 8. Device ID address PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 6 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 7.2.1 Software Reset The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The Software Reset sequence is defined as following: 1. A START command is sent by the I2C-bus master. 2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I2C-bus master. 3. The PCA9672 device(s) acknowledge(s) after seeing the General Call address ‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C-bus master. 4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h. a. The PCA9672 acknowledges this value only. If the byte is not equal to 06h, the PCA9672 does not acknowledge it. If more than 1 byte of data is sent, the PCA9672 does not acknowledge any more. 5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9672 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. The I2C-bus master must interpret a non-acknowledge from the PCA9672 (at any time) as a ‘Software Reset Abort’. The PCA9672 does not initiate a reset of its registers. The unique sequence that initiates a Software Reset is described in Figure 9. SWRST Call I2C-bus address S 0 0 0 0 0 START condition 0 0 SWRST data = 06h 0 A R/W acknowledge from slave(s) 0 0 0 0 0 1 1 0 A P acknowledge from slave(s) PCA9672 is(are) reset. Registers are set to default power-up values. 002aac329 Fig 9. Software Reset sequence PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 7 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 7.2.2 Device ID (PCA9672 ID field) The Device ID field is a 3-byte read-only (24 bits) word giving the following information: • 8 bits with the manufacturer name, unique per manufacturer (for example, NXP). • 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the category ID and the 6 LSBs with the feature ID (for example, for example PCA9672 8-bit quasi-output I/O expander). • 3 bits with the die revision, assigned by manufacturer (for example, Rev X). The Device ID is read-only, hardwired in the device and can be accessed as follows: 1. START command 2. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W bit set to 0 (write). 3. The master sends the I2C-bus slave address of the slave device it needs to identify. The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one that has the I2C-bus slave address). 4. The master sends a Re-START command. Remark: A STOP command followed by a START command will reset the slave state machine and the Device ID read cannot be performed. Remark: A STOP command or a Re-START command followed by an access to another slave device will reset the slave state machine and the Device ID read cannot be performed. 5. The master sends the Reserved Device ID I2C-bus address ‘1111 100’ with the R/W bit set to 1 (read). 6. The device ID read can be done, starting with the 8 manufacturer bits (first byte + 4 MSB of the second byte), followed by the 13 part identification bits and then the 3 die revision bits (3 LSB of the third byte). 7. The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. Remark: The reading of the Device ID can be stopped anytime by sending a NACK command. Remark: If the master continues to ACK the bytes after the third byte, the PCA9672 rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. For the PCA9672, the Device ID is as shown in Figure 10. part identification 0 0 manufacturer 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 category identification feature identification revision 0 0 0 002aac326 Fig 10. PCA9672 ID PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 8 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset acknowledge from slave to be identified acknowledge from one or several slave(s) S 1 1 1 1 START condition 1 0 acknowledge from slave to be identified don't care device ID address 0 0 A A6 A5 A4 A3 A2 A1 A0 X R/W I2C-bus slave address of the device to be identified acknowledge from master A 1 1 1 1 1 0 device ID address acknowledge from master 0 1 A R/W no acknowledge from master M7 M6 M5 M4 M3 M2 M1 M0 A C6 C5 C4 C3 C2 C1 C0 F5 A F4 P3 P2 P1 P0 R2 R1 R0 A category identification = 0000001 manufacturer name = 00000000 P revision = 000 feature identification = 000011 STOP condition 002aac327 If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a ‘no acknowledge’. Fig 11. Device ID field reading 8. I/O programming 8.1 Quasi-bidirectional I/O architecture The PCA9672’s 8 ports (see Figure 2) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see Figure 13). Output data is transmitted to the ports in the Write mode (see Figure 12). This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS. 8.2 Writing to the port (Output mode) To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the write mode is entered. The PCA9672 acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the PCA9672. The 8-bit data is presented on the port lines after it has been acknowledged by the PCA9672. The number of data bytes that can be sent successively is not limited. The previous data is overwritten every time a data byte has been sent. PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 9 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset SCL 1 2 3 4 5 6 7 8 9 slave address data 1 SDA S A6 A5 A4 A3 A2 A1 A0 0 START condition R/W data 2 A P7 P6 1 P4 P3 P2 P1 P0 A P7 0 P5 P4 P3 P2 P1 P0 A P5 acknowledge from slave P5 acknowledge from slave acknowledge from slave write to port tv(Q) data output from port tv(Q) DATA 1 VALID DATA 2 VALID P5 output voltage Itrt(pu) P5 pull-up output current IOH INT td(rst) 002aac120 Fig 12. Write mode (output) 8.3 Reading from a port (Input mode) All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered. The data bytes that follow on the SDA are the values on the ports. If the data on the input port changes faster than the master can read, this data may be lost. slave address data from port SDA S A6 A5 A4 A3 A2 A1 A0 1 START condition R/W A data from port A DATA 1 DATA 4 1 P STOP condition acknowledge from master acknowledge from slave no acknowledge from master read from port DATA 2 data into port DATA 3 th(D) DATA 4 tsu(D) INT tv(Q) td(rst) td(rst) 002aac121 A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (Output mode). Input data is lost. Fig 13. Read input port register PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 10 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 8.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9672 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9672 registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset the device. 8.5 Interrupt output (INT) The PCA9672 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see Figure 12, Figure 13, and Figure 14). This gives these chips a kind of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs. After time tv(D) the signal INT is valid. The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely deactivated (HIGH). The interrupt is reset in the read mode on the rising edge of the read from port pulse. During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as an INT. VDD device 1 device 2 device 8 PCA9672 PCA9672 PCA9672 INT INT INT MICROCOMPUTER INT 002aac328 Fig 14. Application of multiple PCA9672s with interrupt 8.6 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9672 registers and I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 11 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 15). SDA SCL data line stable; data valid change of data allowed mba607 Fig 15. Bit transfer 9.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 16.) SDA SDA SCL SCL S P START condition STOP condition mba608 Fig 16. Definition of START and STOP conditions 9.2 System configuration A device generating a message is a ‘transmitter'; a device receiving is the ‘receiver'. The device that controls the message is the ‘master' and the devices which are controlled by the master are the ‘slaves' (see Figure 17). PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 12 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 17. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 S START condition 2 8 9 clock pulse for acknowledgement 002aaa987 Fig 18. Acknowledgement on the I2C-bus PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 13 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 10. Application design-in information 10.1 Bidirectional I/O expander applications In the 8-bit I/O expander application shown in Figure 19, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P2 to P7). During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I2C-bus. VDD VDD VDD SDA SCL INT RESET CORE PROCESSOR AD0 AD1 P0 P1 P2 P3 P4 P5 P6 P7 temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3 002aac330 Fig 19. Bidirectional I/O expander application 10.2 High current-drive load applications The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200 mA. VDD CORE PROCESSOR VDD SDA SCL INT RESET AD0 AD1 VDD P0 P1 P2 P3 P4 P5 P6 P7 LOAD 002aac331 Fig 20. High current-drive load application PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 14 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 11. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage −0.5 +6 V IDD supply current - ±100 mA ISS ground supply current - ±400 mA VI input voltage VSS − 0.5 5.5 V II input current - ±20 mA IO output current - ±50 mA Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +85 °C [1] [1] operating Total package (maximum) output current is 400 mA. 12. Static characteristics Table 5. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.3 - 5.5 V Supplies VDD supply voltage IDD supply current Operating mode; no load; VI = VDD or VSS; fSCL = 1 MHz; AD0, AD1 = static H or L - 260 500 µA Istb standby current Standby mode; no load; VI = VDD or VSS; fSCL = 0 kHz - 2.5 10 µA VPOR power-on reset voltage - 1.8 2.0 V [1] Input SCL; input/output SDA VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V; VDD = 2.3 V 20 - - mA VOL = 0.4 V; VDD = 3.0 V 25 - - mA VOL = 0.4 V; VDD = 4.5 V 30 - - mA IL leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 4 10 pF PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 15 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset Table 5. Static characteristics …continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VOL = 0.5 V; VDD = 2.3 V 12 28 - mA VOL = 0.5 V; VDD = 3.0 V 17 35 - mA VOL = 0.5 V; VDD = 4.5 V 25 43 - mA VOL = 0.5 V; VDD = 4.5 V - - 200 mA VOH = VSS −30 −250 −300 µA I/Os; P0 to P7 LOW-level output current[2] IOL current[2] IOL(tot) total LOW-level output IOH HIGH-level output current Itrt(pu) transient boosted pull-up current VOH = VSS; see Figure 12 −0.5 −1.0 - mA Ci input capacitance [3] - 3 10 pF output capacitance [3] - 3 10 pF Co Input RESET VIL LOW-level input voltage −0.5 - +0.8 V VIH HIGH-level input voltage 2 - 5.5 V ILI input leakage current −1 - +1 µA IOH HIGH-level output current −1 - +1 µA Ci input capacitance - 3 5 pF 3.0 - - mA - 2 5 pF Interrupt INT (see Figure 12 and Figure 13) IOL LOW-level output current Co output capacitance VOL = 0.4 V Inputs AD0, AD1 VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V ILI input leakage current −1 - +1 µA Ci input capacitance - 3 5 pF [1] The power-on reset circuit resets the I2C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD). [2] Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits. [3] The value is not tested, but verified on sampling basis. PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 16 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 13. Dynamic characteristics Table 6. Dynamic characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter fSCL SCL clock frequency tBUF Conditions Standard mode I2C-bus Fast mode I2C-bus Fast mode Plus Unit I2C-bus Min Max Min Max Min Max 0 100 0 400 0 1000 bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - µs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - 0.26 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - 0.26 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 - µs tHD;DAT data hold time 0 - 0 - 0 - ns tVD;ACK data valid acknowledge time[1] 0.3 3.45 0.1 0.9 0.05 0.45 µs tVD;DAT data valid time[2] 300 - 50 - 50 450 ns tSU;DAT data set-up time 250 - 100 - 50 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - µs tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 - 120 ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 - 120 ns tSP pulse width of spikes that must be suppressed by the input filter[6] - 50 - 50 - 50 ns [4][5] kHz Port timing; CL ≤ 100 pF (see Figure 12 and Figure 13) tv(Q) data output valid time - 4 - 4 - 4 µs tsu(D) data input setup time 0 - 0 - 0 - µs th(D) data input hold time 4 - 4 - 4 - µs Interrupt timing; CL ≤ 100 pF (see Figure 12 and Figure 13) tv(D) data input valid time - 4 - 4 - 4 µs td(rst) reset delay time - 4 - 4 - 4 µs 4 - 4 - 4 - µs 0 - 0 - 0 - µs 100 - 100 - 100 - µs Reset timing (see Figure 22) tw(rst) reset pulse width trec(rst) reset recovery time trst reset time [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 17 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset [3] Cb = total capacitance of one bus line in pF. [4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. [5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Rise and fall times refer to VIL and VIH. Fig 21. I2C-bus timing diagram ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % 50 % trec(rst) tw(rst) trst 50 % Pn output off 002aac332 Fig 22. Reset timing PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 18 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 14. Package outline HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm A B D SOT758-1 terminal 1 index area A E A1 c detail X e1 C 1/2 e e 5 y y1 C v M C A B w M C b 8 L 4 9 e e2 Eh 1/2 e 12 1 16 terminal 1 index area 13 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.75 1.45 3.1 2.9 1.75 1.45 e e1 1.5 0.5 e2 L v w y y1 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT758-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 02-03-25 02-10-21 Fig 23. Package outline SOT758-1 (HVQFN16) PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 19 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 24. Package outline SOT162-1 (SO16) PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 20 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 25. Package outline SOT403-1 (TSSOP16) PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 21 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 15. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 16. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 16.3 Wave soldering Key characteristics in wave soldering are: PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 22 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 26) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8 Table 7. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 8. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 26. PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 23 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 9. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge GPIO General Purpose Input/Output HBM Human Body Model LED Light Emitting Diode IC Integrated Circuit I2C-bus Inter IC bus ID Identification LSB Least Significant Bit MM Machine Model MSB Most Significant Bit PLC Programmable Logic Controller PWM Pulse Width Modulation RAID Redundant Array of Independent Disks PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 24 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 18. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9672_2 20070706 Product data sheet - PCA9672_1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 1 “Ordering information”: – changed Topside mark for PCA9672BS from “9672” to “672” – changed Topside mark for PCA9672PW from “9672” to “PCA9672” • Table 5 “Static characteristics”: – sub-section “Supplies”: changed IDD (Typ) from 100 µA to 260 µA – sub-section “Supplies”: changed IDD (Max) from 200 µA to 500 µA – sub-section “Input SCL; input/output SDA”: changed Ci (Typ) from 5 pF to 4 pF – sub-section “I/Os; P0 to P7”: all Typ “<tbd>” values updated – sub-section “Interrupt INT”: changed Co (Typ) from 3 pF to 2 pF – sub-section “Inputs AD0, AD1”: changed Ci (Typ) from 3.5 pF to 3 pF • Table 6 “Dynamic characteristics”: – tVD;DAT (Fast-mode Plus) (Min) changed from “<tbd>” to 50 ns; (Max) changed from “-” to 450 ns – tSP (Fast-mode Plus) (Max) changed from “<tbd>” to 50 ns PCA9672_1 20060620 Objective data sheet - PCA9672_2 Product data sheet - © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 25 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 19.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PCA9672_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 July 2007 26 of 27 PCA9672 NXP Semiconductors Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset 21. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.2.1 7.2.2 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.1.1 9.2 9.3 10 10.1 10.2 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 19 19.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address map. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Software Reset Call, and device ID addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device ID (PCA9672 ID field) . . . . . . . . . . . . . . 8 I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 9 Quasi-bidirectional I/O architecture . . . . . . . . . 9 Writing to the port (Output mode) . . . . . . . . . . . 9 Reading from a port (Input mode) . . . . . . . . . 10 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 11 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Characteristics of the I2C-bus. . . . . . . . . . . . . 12 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 START and STOP conditions . . . . . . . . . . . . . 12 System configuration . . . . . . . . . . . . . . . . . . . 12 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application design-in information . . . . . . . . . 14 Bidirectional I/O expander applications . . . . . 14 High current-drive load applications . . . . . . . . 14 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 Static characteristics. . . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Handling information. . . . . . . . . . . . . . . . . . . . 22 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Introduction to soldering . . . . . . . . . . . . . . . . . 22 Wave and reflow soldering . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25 Legal information. . . . . . . . . . . . . . . . . . . . . . . 26 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26 19.2 19.3 19.4 20 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 26 26 26 27 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 July 2007 Document identifier: PCA9672_2