PCS2I99447 September 2006 rev 0.4 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Features PCS2I99447 is specifically designed to distribute LVCMOS • 9 LVCMOS Compatible Clock Outputs compatible clock signals up to a frequency of 350 MHz. • 2 Selectable, LVCMOS Compatible Inputs • Maximum Clock Frequency of 350 MHz • Maximum Clock Skew of 150 pS • Synchronous Output Stop in Logic Low State Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support driving of 50Ω terminated transmission lines on the incident edge: each is capable of driving either one parallel terminated or Eliminates Output Runt Pulses two series terminated transmission lines. Two selectable independent LVCMOS compatible clock • High–Impedance Output Control • 3.3V or 2.5V Power Supply source systems. The PCS2I99447 CLK_STOP control is • Drives up to 18 Series Terminated Clock Lines synchronous to the falling edge of the input clock. It allows • Ambient Temperature Range -40°C to +85°C the start and stop of the output clock signal only in a logic • 32 Lead LQFP and TQFP Packaging low state, thus eliminating potential output runt pulses. • Supports Clock Distribution inputs are available, providing support of redundant clock in Networking, Telecommunications and Computer Applications • Applying the OE control will force the outputs into high impedance mode. Pin and Function Compatible to MPC947 and All inputs have an internal pull–up or pull–down resistor MPC9447 preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The Functional Description PCS2I99447 The PCS2I99447 is a 3.3V or 2.5V compatible, 1:9 clock is pin and function compatible but performance enhanced to the MPC947 and MPC9447. fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 pS, the device meets the needs of most demanding clock applications. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS2I99447 September 2006 rev 0.4 Block Diagram Q0 CCLK0 0 CCLK1 1 CLK Q1 STOP VCC Q2 CLK_SEL Q3 VCC SYNC CLK_STOP Q4 Q5 Q5 Q6 VCC Q7 VCC Q4 GND Q5 VCC GND Pin Configuration Q3 (All input resistors have a value of 25KΩ) GND OE 24 23 22 21 20 19 18 17 GND 25 16 GND Q2 26 15 Q6 VCC 27 14 VCC Q1 28 13 Q7 GND 29 12 GND Q0 30 11 Q8 VCC 31 10 VCC GND 32 PCS2I99447 2 3 4 5 6 7 8 GND CLK_SEL CCLK0 CCLK1 CLK_STOP OE VCC GND 9 1 GND 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 2 of 14 PCS2I99447 September 2006 rev 0.4 Table 1. Function Table Control Default CLK_SEL OE 1 1 CLK0 input selected Outputs disabled (high–impedance state)1 CLK1 input selected Outputs enabled 1 Outputs synchronously stopped in logic low state Outputs active CLK_STOP 0 1 Note: 1. OE = 0 will high–impedance tristate all outputs independent on CLK_STOP Table 2. Pin Configuration Pin # Pin Name 3 4 2 I/O Type Input Input Input LVCMOS LVCMOS LVCMOS Clock signal input Alternative clock signal input Clock input select Input LVCMOS Clock output enable/disable Input LVCMOS Q0 – Q8 Output LVCMOS GND Supply Ground VCC Supply VCC CCLK0 CCLK1 CLK_SEL 5 CLK_STOP 6 OE 11,13,15,19,21,23,26,28,30 1,8,9,12,16,17,20,24,25,29,32 7,10,14,18,22,27,31 Function Output enable/disable (high–impedance tristate) Clock outputs Negative power supply (GND) for Output and Core Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 3. General Specifications Symbol Characteristics Min VTT Output termination voltage MM ESD protection (Machine model) 200 HBM Typ Max VCC ÷2 Unit Condition V V ESD protection (Human body model) 2000 V LU Latch-up immunity 200 mA CPD Power dissipation capacitance 10 pF Per output CIN Input capacitance 4.0 pF Inputs Table 4. Absolute Maximum Ratings1 Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 3.9 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 ±20 V VOUT IIN IOUT TS DC Input Current DC Output Current Storage temperature ±50 -65 125 Condition mA mA °C Note: 1.These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 3 of 14 PCS2I99447 September 2006 rev 0.4 Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C) Symbol Max Unit Condition VIH Input High Voltage Characteristics Min 2.0 VCC + 0.3 V LVCMOS 0.8 VIL Input Low Voltage -0.3 VOH Output High Voltage 2.4 VOL Output Low Voltage ZOUT Output Impedance IIN ICCQ Typ V LVCMOS V IOH = -24 mA1 0.55 0.30 V V IOL = 24 mA IOL = 12 mA ±300 mA VIN = VCC or GND 2.0 mA All VCC Pins 17 W Input Current2 Maximum Quiescent Supply Current3 Note: 1. The PCS2I99447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for VCC=3.3V). 2. Inputs have pull-down or pull-up resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1 Symbol 5Characteristics fref Input Frequency fmax Output Frequency fP,REF tr, tf Min Reference Input Pulse Width Max Unit 0 Typ 350 MHz 0 350 MHz 1.4 nS CCLK0, CCLK1 Input Rise/Fall Time 1.0 nS 3.3 nS Propagation Delay tPLZ, HZ Output Disable Time 11 nS tPZL, ZH Output Enable Time 11 nS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) Setup Time 3 0.0 nS 3 1.0 nS CCLK0 or CCLK1 to CLK_STOP Hold Time CCLK0 or CCLK1 to CLK_STOP Output-to-Output Skew Device-to-Device Skew 4 Output Pulse Skew Output Duty Cycle MHz Output Rise/Fall Time Cycle-to-cycle jitter 1.3 2 tPLH/HL tS CCLK0 or CCLK1 to any Q fQ<170 45 50 0.1 RMS (1σ) Condition 0.8 to 2.0V 150 pS 2.0 nS 300 55 pS % DCREF = 50% nS 0.55 to 2.4V 1.0 TBD pS Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 3. Setup and hold times are referenced to the falling edge of the selected clock signal input. 4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 4 of 14 PCS2I99447 September 2006 rev 0.4 Table 7. DC Characteristics (VCC = 2.5V ± 5%, TA = -40°C to +85°C) Symbol Max Unit Condition VIH Input High Voltage Characteristics Min 1.7 VCC + 0.3 V LVCMOS 0.7 VIL Input Low Voltage -0.3 VOH Output High Voltage 1.8 VOL Output Low Voltage ZOUT Output Impedance IIN ICCQ Typ 0.6 19 V LVCMOS V IOH =-15 mA1 V IOL = 15 mA Ω Input Current2 Maximum Quiescent Supply Current3 ±300 2.0 mA mA VIN = VCC or GND All VCC Pins Note: 1.The PCS2I99447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines per output (VCC=2.5V). 2. Inputs have pull-down or pull-up resistors affecting the input current. 3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. Table 8. AC Characteristics (VCC = 2.5V ± 5%, TA = -40°C to +85°C)1 Symbol Characteristics Min Typ Max Unit fref Input Frequency 0 350 MHz fmax Output frequency 0 350 MHz fP,REF tr, tf Reference Input Pulse Width 1.4 nS CCLK0, CCLK1 Input Rise/Fall Time nS 4.4 nS Propagation Delay tPLZ, HZ Output Disable Time 11 nS tPZL, ZH Output Enable Time 11 nS tH tsk(O) tsk(PP) tSK(P) DCQ tr, tf tJIT(CC) Setup Time 1.7 1.02 tPLH/HL tS CCLK0 or CCLK1 to any Q 3 0.0 nS 3 1.0 nS CCLK0 or CCLK1 to CLK_STOP Hold Time CCLK0 or CCLK1 to CLK_STOP Output-to-Output Skew Device-to-Device Skew Output Pulse Skew4 Output Duty Cycle fQ<350 MHz Output Rise/Fall Time Cycle-to-cycle jitter RMS (1 σ) 45 0.1 Condition 50 150 pS 2.7 nS 200 55 1.0 TBD pS % nS pS 0.7 to 1.7V DCREF=50% 0.6 to 1.8V Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 3. Setup and hold times are referenced to the falling edge of the selected clock signal input. 4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |. 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 5 of 14 PCS2I99447 September 2006 rev 0.4 APPLICATIONS INFORMATION CCLK or PCLK 3.0 CLK _ STOP Q0 to Q11 Figure 1. Output Clock Stop (CLK_STOP) Timing Diagram Driving Transmission Lines The PCS2I99447 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17Ω (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. In most high performance clock networks, point–to–point distribution of signals is the method of choice. In a point–to–point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. PCS2I99447 OUTPUT BUFFER 17Ω PCS2I99447 OUTPUT BUFFER Z0=50Ω RS=33Ω Z0=50Ω RS=33Ω 17Ω RS=33Ω Z0=50Ω Figure 2. Single versus Dual Transmission Lines This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCS2I99447 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 2 “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the PCS2I99447 clock driver is effectively doubled due to its capability to drive multiple lines at VCC=3.3V. VOLTAGE (V) 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 0.5 0 2 4 6 8 10 12 14 TIME (nS) Figure 3. Single versus Dual Line Termination Waveforms The waveform plots in Figure 3 “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the PCS2I99447 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the PCS2I99447. The output waveform in Figure 3 “Single versus Dual Line Termination Waveforms” shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 (RS+R0 +Z0)) Z0 = 50Ω || 50Ω RS = 33Ω || 33Ω R0 = 17Ω VL = 3.0 ( 25 ÷ (16.5+17+25) = 1.28V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 6 of 14 PCS2I99447 September 2006 rev 0.4 round trip delay (in this case 4.0ns). Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 4 “Optimized Dual Line Termination” should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PCS2I99447 OUTPUT BUFFER RS16Ω 17Ω RS=16Ω Z0=50Ω Z0=50Ω 17Ω + 16Ω ║ 16Ω = 50Ω ║ 50Ω 25Ω = 25Ω Figure 4. Optimized Dual Line Termination The Following Figures Illustrate the Measurement Reference for the PCS2I99447 Clock Driver Circuit PCS2I99447 Pulse Generator Z=50Ω Z0=50Ω Z0=50Ω RT=50Ω RT=50Ω VTT TT Figure 5. CCLK PCS2I99447 AC Test Reference for Vcc = 3.3V and Vcc = 2.5V 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 7 of 14 PCS2I99447 September 2006 rev 0.4 VCC CCLK VCC ÷2 GND VCC QX VCC ÷2 tP(LH) GND tP(HL) Figure 6. Propagation Delay (tPD) Test Reference VCC VCC ÷2 VCC CCLK VCC ÷2 GND GND VCC VCC ÷2 tSK(LH) tSK(HL) GND VCC QX VCC ÷2 tP(LH) The pin-to-pin skew is defined as the worst case difference in propagation between any similar delay path within a single device Figure 7. Output–to–Output Skew tSK(LH, HL) GND tP(HL) tSK(P) =| tPHL - tPHL | Figure 8. Output Pulse Skew (tSK(P) Test VCC VCC ÷2 VCC = 3.3V VCC = 2.5V GND 2.4 0.5 tP T0 tR tF Figure 10. Output Transition Time Test Reference DC (tP ÷T0 Χ 100%) The time from the output controlled edge to the non-controlled edge, divided by the time output controlled edge, expressed as a percentage. Figure 9. Output Duty Cycle (DC) 1.8V 0.6V VCC CCLK PCLK VCC ÷2 GND VCC CLK_STOP VCC ÷2 TJIT(CC) = |TN -TN + 1| TN GND TN + 1 tS The variation in cycle time of a single between adjacent cycles, over a random sample of adjacent cycle pairs Figure 11. Cycle–to–Cycle Jitter Reference tH Figure 12. Setup and Hold Time (tS, tH) Test Reference 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 8 of 14 PCS2I99447 September 2006 rev 0.4 capacitive output load, N is the number of active outputs (N is always 12 in case of the PCS2I99447). The PCS2I99447 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. Power Consumption of the PCS2I99447 and Thermal Management The PCS2I99447 AC specification is guaranteed for the entire operating frequency range up to 350MHz. The PCS2I99447 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCS2I99447 die junction temperature and the associated device reliability. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Table 9. Die junction temperature and MTBF Junction temperature (°C) MTBF (Years) 100 20.4 110 9.1 120 4.2 130 2.0 Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCS2I99447 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the PCS2I99447 is represented in equation 1.Where ICCQ is the static current consumption of the PCS2I99447, CPD is the power dissipation capacitance per output, (Μ)ΣCL represents the external Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCS2I99447 in a series terminated transmission line system, equation 4 PTOT = I CCQ + VCC ⋅ f CLOCK ⋅ N ⋅ C PD + ∑ C L ⋅ VCC M Equation 1 PTOT = VCC ⋅ I CCQ + VCC ⋅ f CLOCK ⋅ N ⋅ C PD + ∑ C L + ∑ DC Q ⋅ I OH (VCC − VOH ) + (1 − DC Q ) ⋅ I OL ⋅ VOL M P T J = T A + PTOT ⋅ Rthja [ f CLOCKMAX = C PD 1 2 ⋅ N ⋅ VCC T − TA ⋅ JMAX − (I CCQ ⋅ VCC ) Rthja 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. ] Equation 2 Equation 3 Equation 4 9 of 14 PCS2I99447 September 2006 rev 0.4 If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the PCS2I99447. The charts were calculated for a maximum tolerable die junction temperature of 110°C (120°C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. TJ,MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Table 10. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 10. Thermal package impedance of the 32LQFP Convection, LFPM Rthja (1P2S board), °C/W Rthja (2P2S board), °C/W Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 86 76 71 68 66 61 56 54 53 52 fMAX (AC) 300 TA = 85°C 250 200 150 Safe operation 100 300 TA = 75°C 250 200 TA = 85°C 150 100 Safe operation 50 50 0 0 500 400 300 200 100 Convection Ifpm 500 0 fMAX (AC) 350 250 200 150 Safe operation 100 300 200 100 Convection Ifpm 0 fMAX (AC) 350 Operating frequency (MHz) 300 400 Figure 14. Maximum PCS2I99447 frequency VCC = 3.3V, MRBF 9.1 years, 4pF load per line, 2s2p board Figure 13. Maximum PCS2I99447 frequency VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines, 2s2p board Operating frequency (MHz) fMAX (AC) 350 Operating frequency (MHz) Operating frequency (MHz) 350 300 TA = 85°C 250 200 150 Safe operation 100 50 50 0 0 500 400 300 200 100 Convection Ifpm 0 Figure 15. No maximum frequency limitation for VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines, 2s2p board 500 400 300 200 100 Convection Ifpm 0 Figure 16. Maximum PCS2I99447 frequency VCC = 3.3V, MRBF 4 years, 4pF load per line, 2s2p board 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 10 of 14 PCS2I99447 September 2006 rev 0.4 Package Information 32-lead TQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.031 BASE 0.8 BASE 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 11 of 14 PCS2I99447 September 2006 rev 0.4 32-lead LQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0630 … 1.6 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.20 e a 0.031 BASE 0° 7° 0.8 BASE 0° 7° 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 12 of 14 PCS2I99447 September 2006 rev 0.4 Ordering Information Part Number Marking Package Type Operating Range PCS2P99447G-32-LT PCS2P99447GL 32-pin LQFP, Tray, Green Commercial PCS2P99447G-32-LR PCS2P99447GL 32-pin LQFP, Tape and Reel, Green Commercial PCS2P99447G-32-ET PCS2P99447GE 32-pin TQFP, Tray, Green Commercial PCS2P99447G-32-ER PCS2P99447GE 32-pin TQFP, Tape and Reel, Green Commercial PCS2I99447G-32-LT PCS2I99447GL 32-pin LQFP, Tray, Green Industrial PCS2I99447G-32-LR PCS2I99447GL 32-pin LQFP, Tape and Reel, Green Industrial PCS2I99447G-32-ET PCS2I99447GE 32-pin TQFP, Tray, Green Industrial PCS2I99447G-32-ER PCS2I99447GE 32-pin TQFP, Tape and Reel, Green Industrial Device Ordering Information P C S 2 I 9 9 4 4 7 G - 3 2 - L R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 13 of 14 PCS2I99447 September 2006 rev 0.4 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I99447 Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 14 of 14