ONSEMI NTMFS4839NT3G

NTMFS4839N
Power MOSFET
30 V, 66 A, Single N−Channel, SO−8FL
Features
•
•
•
•
Low RDS(ON) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices*
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V(BR)DSS
Applications
• Refer to Application Note AND8195/D
• CPU Power Delivery
• DC−DC Converters
RDS(ON) MAX
5.5 mW @ 10 V
30 V
D (5,6)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
15
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.17
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
9.5
A
Power Dissipation
RqJA (Note 2)
TA = 85°C
Steady
State
TA = 25°C
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
Power Dissipation
RqJC (Note 1)
TC = 25°C
S (1,2,3)
PD
ID
TC = 85°C
0.87
A
66
48
W
IDM
132
A
TJ,
TSTG
−55 to
+150
°C
IS
35
A
Drain to Source DV/DT
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 19 Apk, L = 1.0 mH, RG = 25 W
EAS
180.5
mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
TL
Operating Junction and Storage
Temperature
Source Current (Body Diode)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2010
May, 2010 − Rev. 4
MARKING
DIAGRAM
W
41.7
TA = 25°C,
tp = 10 ms
N−CHANNEL MOSFET
7.0
PD
Pulsed Drain
Current
G (4)
11
TA = 85°C
66 A
9.5 mW @ 4.5 V
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
ID MAX
1
1
SO−8 FLAT LEAD
CASE 488AA
STYLE 1
D
S
S
S
G
4839N
AYWWG
G
D
D
D
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
NTMFS4839NT1G
SO−8FL
(Pb−Free)
1500 /
Tape & Reel
NTMFS4839NT3G
SO−8FL
(Pb−Free)
5000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTMFS4839N/D
NTMFS4839N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
3.0
Junction−to−Ambient – Steady State (Note 3)
RqJA
57.7
Junction−to−Ambient – Steady State (Note )
RqJA
143.4
Unit
°C/W
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
25
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
RDS(on)
1.5
5.8
VGS = 10 V to
11.5 V
ID = 30 A
4.5
ID = 15 A
4.5
VGS = 4.5 V
ID = 30 A
8.4
ID = 15 A
8.4
gFS
VDS = 15 V, ID = 15 A
mV/°C
5.5
9.5
14.7
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
1588
VGS = 0 V, f = 1 MHz, VDS = 12 V
352
CRSS
196
Total Gate Charge
QG(TOT)
13
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
VGS = 4.5 V, VDS = 15 V; ID = 30 A
1.6
4.8
pF
18
nC
5.8
QG(TOT)
VGS = 11.5 V, VDS = 15 V;
ID = 30 A
28
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
12
tr
td(OFF)
VGS = 4.5 V, VDS = 15 V, ID = 15 A,
RG = 3.0 W
29
18
tf
7.0
td(ON)
8.0
tr
td(OFF)
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
21
24
7.0
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
ns
ns
NTMFS4839N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
TJ = 25°C
0.9
1.2
TJ = 125°C
0.8
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
VGS = 0 V,
IS = 30 A
tRR
Charge Time
22.2
ta
Discharge Time
12.5
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
tb
Reverse Recovery Charge
V
ns
9.7
QRR
10.8
nC
Source Inductance
LS
0.93
nH
Drain Inductance
LD
0.005
nH
Gate Inductance
LG
1.84
nH
Gate Resistance
RG
3.3
W
PACKAGE PARASITIC VALUES
TA = 25°C
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
90
4.6 V
6.0 V
4.2 V
4.0 V
60
50
40
30
3.5 V
20
10
0
1
2
3
4
5
60
50
40
TC = 25°C
30
20
TC = 125°C
TC = −55°C
0
6
7
1
8
2
3
4
5
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.012
ID = 30 A
TJ = 25°C
0.01
0.008
0.006
0.004
2.5
70
10
VGS = 3.0 V
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
80
ID, DRAIN CURRENT (A)
70
TJ = 25°C
3.5
4.5
5.5
6.5
7.5
8.5
9.5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
80
90
4.4 V
10.5 11.5
6
0.01
0.009
VGS = 4.5 V
0.008
0.007
0.006
0.005
VGS = 11.5 V
0.004
0.003
0.002
0.001
10
15
20
25
30
35
40
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Temperature
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3
100000
1.80
10000
ISS, LEAKAGE (nA)
1.60
VGS = 0 V
ID = 30 A
VGS = 10 V & 4.5 V
1.40
1.20
1.00
TJ = 150°C
1000
TJ = 125°C
100
0.80
10
0
25
50
75
100
125
150
4
8
TJ, JUNCTION TEMPERATURE (°C)
16
20
CISS
CISS
CRSS
COSS
CRSS
10
5
VGS
0
5
10
15
20
25
30
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
12
VDS
8
6
4
QGS
2
0
20
19
18
17
16
VGS
15
14
13
12
11
10
9
8
7
QGD
6
5
4
ID = 30 A
3
TJ = 25°C
2
1
0
5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
QT
10
0
2.5
28
Figure 6. Drain−to−Source Leakage Current
versus Voltage
TJ = 25°C
15
24
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
3000
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
800
600
400
200
0
12
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−25
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.60
−50
C, CAPACITANCE (pF)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
NTMFS4839N
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Gate Charge
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4
NTMFS4839N
1000
30
VGS = 0 V
IS, SOURCE CURRENT (A)
t, TIME (ns)
VDS = 15 V
ID = 30 A
VGS = 11.5 V
tf
100
td(off)
tr
10
td(on)
1
10
100
20
15
10
5
0.6
0.7
0.8
0.9
1
Figure 10. Diode Forward Voltage versus
Current
10 ms
100 ms
1 ms
10 ms
dc
RDS(on) Limit
Thermal Limit
Package Limit
1
10
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
10
0.1
0.1
0.5
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
VGS = 20 V
Single Pulse
TC = 25°C
1
0.4
RG, GATE RESISTANCE (W)
1000
ID, DRAIN CURRENT (A)
TJ = 25°C
0
1
100
25
200
190
180
170
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
1.1
ID = 19 A
25
50
75
100
125
150
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
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5
NTMFS4839N
PACKAGE DIMENSIONS
DFN5 5x6, 1.27P
(SO−8FL)
CASE 488AA−01
ISSUE D
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE
MOLD FLASH PROTRUSIONS OR GATE
BURRS.
0.20 C
D
2
A
B
D1
6
2X
0.20 C
5
4X
E1
1
2
3
q
E
2
c
A1
4
TOP VIEW
C
3X
e
0.10 C
SEATING
PLANE
DETAIL A
A
0.10 C
SIDE VIEW
8X
C A B
0.05
c
3X
4X
1.270
STYLE 1:
PIN 1. SOURCE
2. SOURCE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
e/2
L
1
4
K
0.750
4X
1.000
0.965
1.330
2X
0.905
2X
E2
L1
6
G
MILLIMETERS
MIN
NOM
MAX
0.90
1.00
1.10
0.00
−−−
0.05
0.33
0.41
0.51
0.23
0.28
0.33
5.15 BSC
4.50
4.90
5.10
3.50
−−−
4.22
6.15 BSC
5.50
5.80
6.10
3.45
−−−
4.30
1.27 BSC
0.51
0.61
0.71
0.51
−−−
−−−
0.51
0.61
0.71
0.05
0.17
0.20
3.00
3.40
3.80
0_
−−−
12 _
SOLDERING FOOTPRINT*
DETAIL A
b
0.10
DIM
A
A1
b
c
D
D1
D2
E
E1
E2
e
G
K
L
L1
M
q
0.495
M
4.530
3.200
0.475
5
D2
2X
1.530
BOTTOM VIEW
4.560
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTMFS4839N/D