CY7C1041DV33 4-Mbit (256K x 16) Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1041CV33 • High speed The CY7C1041DV33 is a high-performance CMOS Static RAM organized as 256K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written into the location specified on the address pins (A0–A17). If Byte HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). — tAA =10 ns • Low active power — ICC = 90 mA @ 10 ns (Industrial) • Low CMOS standby power • • • • • — ISB2 = 10 mA 2.0 V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in lead-free 48-ball VFBGA, 44-lead (400-mil) Molded SOJ and 44-pin TSOP II packages Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0–I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1041DV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package. Logic Block Diagram 256K × 16 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER INPUT BUFFER I/O0–I/O7 I/O8–I/O15 A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 COLUMN DECODER BHE WE CE OE BLE Note 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05473 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 17, 2006 [+] Feedback CY7C1041DV33 Selection Guide –10 (Industrial) –12 (Automotive)[2] Unit Maximum Access Time 10 12 ns Maximum Operating Current 90 95 mA Maximum CMOS Standby Current 10 15 mA Pin Configurations 48-ball Mini FBGA SOJ (Top View) TSOP II Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O0 BHE A3 A4 CE I/O 8 B I/O1 I/O 2 A5 A6 I/O10 I/O9 C VSS I/O3 A17 A7 I/O11 VCC D VCC I/O 4 NC A16 I/O12 VSS E I/O6 I/O 5 A14 A15 I/O13 I/O14 F I/O7 NC A12 A13 WE I/O15 G NC A8 A9 A10 A11 NC H A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Note 2. Automotive product information is Preliminary. Document #: 38-05473 Rev. *D Page 2 of 14 [+] Feedback CY7C1041DV33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............. ...............................>2001V Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range [3] Supply Voltage on VCC to Relative GND .... –0.3V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] .....................................–0.3V to VCC +0.3V DC Input Voltage[3] ..................................–0.3V to VCC +0.3V (per MIL-STD-883, Method 3015) Ambient Temperature VCC Speed Industrial –40°C to +85°C 3.3V ± 0.3V 10 ns Automotive –40°C to +125°C 3.3V ± 0.3V 12 ns Range DC Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA [3] –10 (Industrial) Test Conditions Min. Max. 2.4 –12 (Automotive) Min. Max. 2.4 0.4 Unit V 0.4 V Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL[3] Input LOW Voltage –0.3 0.8 –0.3 0.8 V VIH IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 100MHz 90 - mA 83MHz 80 95 mA 66MHz 70 85 mA 40MHz 60 75 mA 20 25 mA 10 15 mA Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB1 Automatic CE Power-down Current—TTL Inputs ISB2 Automatic CE Max. VCC, Power-down CE > VCC – 0.3V, Current—CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Note 3. Minimum voltage is–2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. Document #: 38-05473 Rev. *D Page 3 of 14 [+] Feedback CY7C1041DV33 Capacitance[4] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF 8 pF Thermal Resistance[4] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions FBGA Package SOJ Package TSOP II Package Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 27.89 57.91 50.66 °C/W 14.74 36.73 17.17 °C/W AC Test Loads and Waveforms[5] 10 ns device Z = 50Ω ALL INPUT PULSES 3.0V OUTPUT 90% 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* GND 90% 10% 10% 1.5V Rise Time: 1 V/ns (b) Fall Time: 1 V/ns (a) High-Z Characteristics R 317Ω 3.3V OUTPUT R2 351Ω 5 pF (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05473 Rev. *D Page 4 of 14 [+] Feedback CY7C1041DV33 AC Switching Characteristics Over the Operating Range[6] Parameter Description –10 (Industrial) Min. Max. –12 (Automotive) Min. Max. Unit Read Cycle tpower[7] VCC(typical) to the first access 100 100 µs tRC Read Cycle Time 10 12 ns tAA Address to Data Valid 10 3 12 ns tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 3 12 ns tDOE OE LOW to Data Valid 5 6 ns tLZOE OE LOW to Low-Z 0 [8, 9] tHZOE OE HIGH to High-Z tLZCE CE LOW to Low-Z[9] 0 5 3 High-Z[8, 9] ns ns 6 3 5 ns ns tHZCE CE HIGH to tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 10 12 ns tDBE Byte Enable to Data Valid 5 6 ns tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z 0 6 0 0 ns 0 6 ns ns 6 ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZCE,tHZBE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given device. Document #: 38-05473 Rev. *D Page 5 of 14 [+] Feedback CY7C1041DV33 AC Switching Characteristics Over the Operating Range[6](continued) Parameter –10 (Industrial) Description Min. Max. –12 (Automotive) Min. Unit Max. Write Cycle[10, 11] tWC Write Cycle Time 10 12 ns tSCE CE LOW to Write End 7 8 ns tAW Address Set-Up to Write End 7 8 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 7 8 ns tSD Data Set-Up to Write End 5 6 ns tHD Data Hold from Write End 0 0 ns tLZWE WE HIGH to Low-Z[9] 3 3 ns High-Z[8, 9] tHZWE WE LOW to tBW Byte Enable to End of Write 5 7 6 ns 8 ns Data Retention Characteristics Over the Operating Range Parameter Conditions[12] Description VDR VCC for Data Retention ICCDR Data Retention Current Min. Max. Unit Ind’l 10 mA Auto 15 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V tCDR[4] Chip Deselect to Data Retention Time tR[13] Operation Recovery Time V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE Notes 10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 12. No input may exceed VCC + 0.3V. 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs Document #: 38-05473 Rev. *D Page 6 of 14 [+] Feedback CY7C1041DV33 Switching Waveforms Read Cycle No. 1[14, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes 14. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05473 Rev. *D Page 7 of 14 [+] Feedback CY7C1041DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Notes 17. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05473 Rev. *D Page 8 of 14 [+] Feedback CY7C1041DV33 Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Write Cycle No. 3 (WE Controlled, OE HIGH During Write)[17, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE BHE, BLE t SD DATA I/O NOTE 19 tHD DATAIN VALID t HZOE Note 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05473 Rev. *D Page 9 of 14 [+] Feedback CY7C1041DV33 Switching Waveforms (continued) Write Cycle No. 4 (WE Controlled, OE LOW) tWC BHE, BLE ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD NOTE 19 DATA I/O tLZWE Truth Table CE H OE X WE X BLE X BHE X L L H L L L L H L L L H H L X L L X I/O0–I/O7 I/O8–I/O15 Mode Power High-Z High-Z Power-down Standby (ISB) Data Out Data Out Read All Bits Active (ICC) H Data Out High-Z Read Lower Bits Only Active (ICC) L High-Z Data Out Read Upper Bits Only Active (ICC) L L Data In Data In Write All Bits Active (ICC) L L H Data In High-Z Write Lower Bits Only Active (ICC) L X L H L High-Z Data In Write Upper Bits Only Active (ICC) L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1041DV33-10BVI Package Diagram 51-85150 CY7C1041DV33-10BVXI Package Type 48-ball VFBGA Industrial 48-ball VFBGA (Pb-Free) CY7C1041DV33-10VXI 51-85082 44-lead (400-mil) Molded SOJ (Pb-Free) CY7C1041DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-Free) Document #: 38-05473 Rev. *D Operating Range Page 10 of 14 [+] Feedback CY7C1041DV33 Ordering Information Speed (ns) Package Diagram Ordering Code 12 Operating Range Package Type CY7C1041DV33-12BVXE 51-85150 48-ball VFBGA (Pb-Free) CY7C1041DV33-12VXE 51-85082 44-lead (400-mil) Molded SOJ (Pb-Free) Automotive CY7C1041DV33-12ZSXE 51-85087 44-pin TSOP II (Pb-Free) Please contact your local Cypress sales representative for availability of these parts Package Diagrams Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm) (51-85150) BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 4 5 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 0.55 MAX. 6.00±0.10 0.10 C 0.21±0.05 0.25 C B 0.15(4X) 51-85150-*D C Document #: 38-05473 Rev. *D 1.00 MAX 0.26 MAX. SEATING PLANE Page 11 of 14 [+] Feedback CY7C1041DV33 Package Diagrams(continued) Figure 2. 44-lead (400-mil) Molded SOJ (51-85082) 51-85082-*B Document #: 38-05473 Rev. *D Page 12 of 14 [+] Feedback CY7C1041DV33 Package Diagrams(continued) Figure 3. 44-pin TSOP II (51-85087) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05473 Rev. *D Page 13 of 14 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1041DV33 Document History Page Document Title: CY7C1041DV33 4-Mbit (256K x 16) Static RAM Document Number: 38-05473 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Data sheet for C9 IPP *A 233729 See ECN RKF 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the ‘Ordering information’ *B 351117 See ECN PCI Changed from Advance to Preliminary Removed 15 and 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10 and 12ns speed bins respectively ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added Static Discharge Voltage and latch-up current spec Added VIH(max) spec in Note# 2 Changed Note# 4 on AC Test Loads Changed reference voltage level for measurement of Hi-Z parameters from ±500 mV to ±200 mV Added Data Retention Characteristics/Waveform and footnote # 11, 12 Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44 and from 44-lead (400-mil) Molded SOJ V34 to 44-lead (400-mil) Molded SOJ V44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns Product Information Added Lead-Free Ordering Information Shaded Ordering Information Table *C 446328 See ECN NXR Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Included Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High-Z parameter measurement Updated the ordering information and replaced Package Name column with Package Diagram in the Ordering Information Table *D 480177 See ECN VKN Added -10BVI product ordering code in the Ordering Information table Document #: 38-05473 Rev. *D Page 14 of 14 [+] Feedback