CYPRESS CY7C1041BN-15VC

CY7C1041BN
256K x 16 Static RAM
Features
Functional Description
• Temperature Ranges
— Commercial: 0°C to 70°C
The CY7C1041BN is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits.
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
• High speed
— tAA = 15 ns
• Low active power
— 1540 mW (max.)
• Low CMOS standby power (L version)
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
— 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free and non Pb-free 44-pin TSOP II and
molded 44-pin (400-Mil) SOJ packages
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1041BN is available in a standard 44-pin
400-mil-wide body width SOJ and 44-pin TSOP II package
with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
TSOP II
Top View
256K x 16
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
INPUT BUFFER
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
I/O0–I/O7
I/O8–I/O15
A9
A10
A 11
A 12
A 13
A14
A15
A16
A17
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document #: 001-06496 Rev. *A
•
198 Champion Court
•
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
San Jose, CA 95134-1709
•
408-943-2600
Revised August 31, 2006
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CY7C1041BN
Selection Guide
-15
Maximum Access Time
Maximum Operating Current
-20
15
20
ns
Commercial
190
170
mA
Industrial
210
190
Automotive-A
Maximum CMOS Standby Current
Unit
190
Commercial
Commercial L
3
3
0.5
0.5
6
6
Industrial
Automotive-A
mA
6
DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
Range
Commercial
Ambient
Temperature[2]
VCC
0°C to +70°C
5V ± 0.5
Industrial
–40°C to +85°C
Automotive-A
–40°C to +85°C
Electrical Characteristics Over the Operating Range
-15
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
Min.
-20
Max.
2.4
Min.
Unit
0.4
V
2.4
0.4
Voltage[1]
Max.
V
2.2
VCC + 0.5
2.2
VCC + 0.5
V
–0.5
0.8
–0.5
0.8
V
VIL
Input LOW
IIX
Input Load Current
IOZ
Output Leakage Current GND < VOUT < VCC, Output Disabled
ICC
VCC Operating Supply
Current
VCC = Max.,
f = fMAX = 1/tRC
190
mA
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
Max. VCC, CE > VIH, VIN > VIH or
VIN < VIL, f = fMAX
40
40
mA
ISB2
Automatic CE
Power-Down Current
—CMOS Inputs
Max. VCC, CE > VCC – 0.3V, Comm’l
VIN > VCC – 0.3V,
Comm’l L
or VIN < 0.3V, f = 0
Ind’l
3
3
mA
0.5
0.5
mA
6
6
mA
6
mA
GND < VI < VCC
–1
+1
–1
+1
mA
–1
+1
–1
+1
mA
Comm’l
190
170
mA
Ind’l
210
190
mA
Auto-A
Auto-A
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06496 Rev. *A
Page 2 of 10
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CY7C1041BN
Capacitance[3]
Parameter
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
Max.
Unit
8
pF
8
pF
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms
ALL INPUT PULSES
R1 481Ω
R1 481Ω
5V
5V
OUTPUT
3.0V
90%
OUTPUT
R2
255Ω
30 pF
5 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
90%
10%
10%
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
(b)
≤ 3 ns
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Equivalent to:
Switching Characteristics[4] Over the Operating Range
-15
Parameter
Description
Min.
-20
Max.
Min.
Max.
Unit
Read Cycle
tpower
VCC(typical) to the First Access[5]
1
tRC
Read Cycle Time
15
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
tLZCE
OE HIGH to High
CE LOW to Low
Z[7]
20
15
3
3
7
0
3
20
ns
8
ns
ns
8
3
7
ns
ns
0
7
Z[6, 7]
ns
20
15
Z[6, 7]
µs
1
ns
ns
tHZCE
CE HIGH to High
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
15
20
ns
tDBE
Byte Enable to Data Valid
7
8
ns
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
8
ns
0
8
0
0
0
7
ns
ns
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is
started.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
Document #: 001-06496 Rev. *A
Page 3 of 10
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CY7C1041BN
Switching Characteristics[4] Over the Operating Range (continued)
-15
Parameter
Write Cycle
Description
Min.
-20
Max.
Min.
Max.
Unit
[8, 9]
tWC
Write Cycle Time
15
20
ns
tSCE
CE LOW to Write End
12
13
ns
tAW
Address Set-Up to Write End
12
13
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
12
13
ns
tSD
Data Set-Up to Write End
8
9
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
ns
tHZWE
WE LOW to High Z[6, 7]
tBW
Byte Enable to End of Write
7
12
8
13
ns
ns
Data Retention Characteristics Over the Operating Range (L version only)
Parameter
VDR
VCC for Data Retention
ICCDR
tCDR
Conditions[11]
Description
Chip Deselect to Data Retention Time
tR[10]
Max.
2.0
Data Retention Current
[3]
Min.
Operation Recovery Time
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Unit
V
200
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
tCDR
VDR > 2V
3.0V
tR
CE
Notes:
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
10. tr < 3 ns for the -15 speed. tr < 5 ns for the -20 and slower speeds.
11. No input may exceed VCC + 0.5V.
Document #: 001-06496 Rev. *A
Page 4 of 10
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CY7C1041BN
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
12. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 001-06496 Rev. *A
Page 5 of 10
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CY7C1041BN
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATAI/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATAI/O
Notes:
15. Data I/O is high impedance if OE or BHE and/or BLE= VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06496 Rev. *A
Page 6 of 10
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CY7C1041BN
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
BLE
BHE
H
X
X
X
X
High Z
High Z
Power Down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read All bits
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read Lower bits only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read Upper bits only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write All bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write Lower bits only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write Upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 001-06496 Rev. *A
I/O0–I/O7
I/O8–I/O15
Mode
Power
Page 7 of 10
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CY7C1041BN
Ordering Information
Speed
(ns)
15
Ordering Code
CY7C1041BN-15VC
Package
Name
51-85082
CY7C1041BN-15VXC
CY7C1041BN-15ZC
44-pin (400-Mil) Molded SOJ
51-85087
Commercial
44-pin TSOP Type II
44-pin TSOP Type II (Pb-free)
CY7C1041BNL-15ZC
44-pin TSOP Type II
CY7C1041BNL-15ZXC
44-pin TSOP Type II (Pb-free)
CY7C1041BN-15ZI
44-pin TSOP Type II
CY7C1041BN-15ZXI
44-pin TSOP Type II (Pb-free)
51-85082
44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1041BN-20VXC
44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1041BNL-20VXC
44-pin (400-Mil) Molded SOJ (Pb-free)
51-85087
Industrial
44-pin (400-Mil) Molded SOJ
CY7C1041BN-15VXI
CY7C1041BN-20ZC
Operating
Range
44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1041BN-15ZXC
CY7C1041BN-15VI
20
Package Type
Commercial
44-pin TSOP Type II
CY7C1041BN-20ZXC
44-pin TSOP Type II (Pb-free)
CY7C1041BN-20ZI
44-pin TSOP Type II
CY7C1041BN-20ZXI
44-pin TSOP Type II (Pb-free)
CY7C1041BN-20VXI
51-85082
44-pin (400-Mil) Molded SOJ (Pb-free)
CY7C1041BN-20ZSXA
51-85087
44-pin TSOP Type II
Industrial
Automotive-A
Please contact local sales representative regarding availability of these parts.
Package Diagrams
44-pin (400-Mil) Molded SOJ (51-85082)
51-85082-*B
Document #: 001-06496 Rev. *A
Page 8 of 10
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CY7C1041BN
Package Diagrams (continued)
44-Pin TSOP II (51-85087)
51-85087-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06496 Rev. *A
Page 9 of 10
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1041BN
Document History Page
Document Title: CY7C1041BN 256K x 16 Static RAM
Document Number: 001-06496
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
424111
See ECN
NXR
New Data Sheets
*A
498575
See ECN
NXR
Added Automotive-A operating range
updated Ordering Information Table
Document #: 001-06496 Rev. *A
Page 10 of 10
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