19-4605; Rev 0; 6/09 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control The MAXQ8913 is a single-chip servo controller designed as a complete solution for dual axis optical image stabilization (OIS) applications. The device incorporates all the necessary elements for conditioning of sensor signals, analog-to-digital conversion, digital servo algorithm implementation using a 16-bit RISC microcontroller, and digital-to-analog conversion, as well as including dual servo amplifiers. Even though the device is targeted for OIS applications, it can be effectively used in many other types of servo control. The MAXQ8913 supports both voice coil and stepper motor applications. The MAXQ8913 includes four op amps; a 7-channel, 12-bit ADC; dual 10-bit differential DACs; and dual 8-bit single-ended DACs. It also contains 64KB of flash memory, 4KB of RAM, 4KB of ROM, a 16-bit timer/counter, a universal asynchronous/synchronous receiver-transmitter (USART), an I2C port, and an SPI™ master/slave port. For the ultimate in low-power performance, the OIS device includes a low-power sleep mode, the ability to selectively disable peripherals, and multiple power-saving operating modes. Applications Digital Camera and Cell Phone Optical Image Stabilization Servo Loop Control Tone Generation with Speaker Drive Ordering Information PART TEMP RANGE PIN-PACKAGE MAXQ8913EWG+T -40°C to +85°C 58 WLP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Pin Configuration appears at end of data sheet. Features ♦ High-Performance, Low-Power, 16-Bit MAXQ® RISC Core ♦ One-Cycle, 16 x 16 Hardware Multiply/Accumulate with 48-Bit Accumulator ♦ Two Current Sinks for Driving Hall-Effect Elements ♦ Four DACs ♦ DC to 10MHz Operation; Approaching 1MIPS per MHz ♦ 2.7V to 3.6V Logic/Analog Operating Voltage ♦ 33 Instructions, Most Single Cycle ♦ Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement ♦ 16-Level Hardware Stack ♦ 16-Bit Instruction Word, 16-Bit Data Bus ♦ 16 x 16-Bit General-Purpose Working Registers ♦ Optimized for C Compilers ♦ Memory Features 64KB Flash Memory 4KB of Internal Data RAM 4KB of Utility ROM JTAG Bootloader for Programming and Debug ♦ Peripherals Four Operational Amplifiers 12-Bit SAR ADC with Internal Reference and Autoscan Up to 312ksps Sample Rate Seven-Input Mux (Four Internally Connected to Op-Amp Outputs, One Internally Connected to Temp Sensor, and Two Connected to Uncommitted External Pins) Brownout Reset Generation 16-Bit Programmable Timer/Counter USART, I2C, and SPI Master/Slave On-Chip Power-On Reset/Brownout Reset Programmable Watchdog ♦ Low-Power Consumption 3mA (max) at 10MHz Flash Operation at 3.3V 4.5µA (max) in Stop Mode Low-Power Power-Management Mode (PMM) SPI is a trademark of Motorola, Inc. MAXQ is a registered trademark of Maxim Integrated Products, Inc. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAXQ8913 General Description MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control ABSOLUTE MAXIMUM RATINGS Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +150°C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification. Voltage Range on All Pins (including AVDD, DVDD) Relative to Ground .................................-0.5V to +3.6V Voltage Range on Any Pin Relative to Ground except AVDD, DVDD...........................-0.5V to (VDVDD + 0.5V) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER Digital Supply Voltage SYMBOL CONDITIONS MIN TYP MAX UNITS VRST 3.3 3.6 V 3.6 V 1.8 1.89 V 3.6 V VDVDD VAVDD = VDVDD Regulator Voltage Output VREG18 (Note 2) 1.71 Analog Supply Voltage VAVDD VAVDD = VDVDD 2.7 Ground GND AGND = DGND 0 Digital Power-Fail Reset Voltage VRST Monitors VDVDD 2.58 Digital Operating Voltage Active Current (Note 3) Stop-Mode Current Stop-Mode Resume Time VRST IDD_HFX3 IDD_HFX4 fCK = 10MHz, VDVDD = 2.7V fCK = 10MHz, VDVDD = 3.3V I STOP_1 (Notes 4, 5) I STOP_2 (Notes 4, 6) 0 0 V 2.68 V 2.2 3.0 0.2 4.5 40 I STOP_3 (Notes 4, 7) t STOP_1 Internal regulator on 15 t STOP_2 Internal regulator off, brownout or SVM on 375 mA μA 500 μs Input Low Voltage on HFXIN VIL1 VDGND 0.20 x VDVDD V Input Low Voltage on All Other Port Pins VIL2 VDGND 0.30 x VDVDD V Input High Voltage on HFXIN VIH1 0.75 x VDVDD VDVDD V Input High Voltage on All Other Port Pins VIH2 0.70 x VDVDD VDVDD V Input Hysteresis (Schmitt) VIHYS 0.18 V Output Low Voltage for All Port Pins Except SHDNL, SHDNR VOL I OL = 4mA (Note 8) VDGND 0.4 V Output Low Voltage for SHDNL, SHDNR VOL I OL = 1.5mA VDGND 0.4 V Output High Voltage for All Port Pins VOH I OH = -4mA (Note 8) VDVDD - 0.4 I/O Pin Capacitance CIO Guaranteed by design 2 _______________________________________________________________________________________ V 15 pF 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control (VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN Input Low Current for Port Pins IIL VIN = 0.4V Input-Leakage Current IL Internal pullup disabled Input Pullup Resistor RPU 30 External Clock Frequency fHFIN DC External Clock Duty Cycle t XCLK_DUTY 40 TYP -300 70 MAX UNITS 100 μA +300 nA 110 k 10 MHz CLOCK SOURCE Internal Ring Oscillator System Clock Frequency 60 1 fCK DC % MHz 10 MHz FLASH AC CHARACTERISTICS System Clock During Flash Programming/Erase Program Time Page Erase Time 2 MHz t PROG 20 40 μs t ERASETME 20 40 ms 20 40 ms Mass Erase Time Write/Erase Cycles Data Retention TA = +25°C 1000 Cycles 100 Years ANALOG-TO-DIGITAL CONVERTER (Note 9) ADC Clock Frequency Input Voltage Range Analog Input Capacitance Current Consumption f SCLK VAIN Unipolar (single-ended) Bipolar (differential) (Note 10) 0.1 5 0 VREF -VREF/2 +VREF/2 CAIN 16 MHz V pF IAVDD1 f SCLK = 5MHz, internal reference 3.0 IAVDD2 f SCLK = 5MHz, external reference (internal reference disabled) 800 IASTOP Power-down mode 2.5 mA μA ANALOG-TO-DIGITAL CONVERTER PERFORMANCE (VREF = 3V, 0.1μF capacitor on REFA, fSCLK = 5MHz) Resolution 12 Integral Nonlinearity INL Differential Nonlinearity DNL ±1 Bits ±2 LSB ±1 LSB Offset Error ±10 LSB Gain Error ±1 % No missing codes from +25°C to +85°C ±0.5 Gain Temperature Coefficient ppm/°C Signal-to-Noise Plus Distortion SINAD f IN = 1kHz 69 dB Spurious-Free Dynamic Range SFDR f IN = 1kHz 76 dB Throughput 16f SCLK samples ADC Setup Time tADC_SETUP (Note 11) Input-Leakage Current I ILA Shutdown or conversion stopped; AIN0/AIN1 and VAEREF 312 ksps 4 μs ±1 μA _______________________________________________________________________________________ 3 MAXQ8913 RECOMMENDED DC OPERATING CONDITIONS (continued) MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control RECOMMENDED DC OPERATING CONDITIONS (continued) (VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL Autoscan Throughput CONDITIONS MIN TYP All channels active MAX UNITS 39 ksps per channel 1.56 V 50 μs VAVDD + 0.05 V ±50 ppm/°C 4 Samples ANALOG-TO-DIGITAL CONVERTER REFERENCE Internal Reference Voltage VAIREF Internal Reference Voltage Startup Time tAIREF External Reference Voltage Input VAEREF Internal Reference Voltage Drift VADRIFT Reference Settle Time (Switching ADC Reference from Either Internal or External Reference to AVDD) Reference Output tAAVDD_ SETUP 1.44 1.5 0.9 Guaranteed by design (Note 12) VREFA VREF V SUPPLY VOLTAGE MONITOR Supply Voltage Set Point SVTR 2.7 Supply Voltage Increment Resolution 80 Supply Voltage Default Set Point Supply Voltage Monitor Start Time Supply Voltage Monitor Setup Time 100 3.5 V 120 mV 2.7 t SVMST V 50 t SVM_SU1 Changing from one set point to another set point 2 t SVM_SU2 Exit from stop mode 8 μs μs CLASS D AMPLIFIER CONTROL DACs, 10-BIT DACs Resolution Full-Scale Output Voltage 10 VFS Output Common-Mode Voltage VCM DC Output Impedance ZOUT Integral Nonlinearity INL Differential Nonlinearity DNL Settling Time Code 0 = -2.5, code 1023 = +2.5, VREF = 1.5V ±2.3 ±2.5 ±2.8 1.15 1.25 1.4 At DC, per side Guaranteed monotonic by design -1 From 1/4 FS to 3/4 FS to 1 LSB Digital Feedthrough Glitch Impulse Major carry transition Update Rate (Note 13) 4 Bits V V 10 k ±2 LSB ±0.10 LSB 2 μs 0.15 nV-s 12 100 _______________________________________________________________________________________ nV-s ksps 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control (VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DAC3 AND DAC4 INCLUDING BUFFER Resolution 8 Full-Scale Output Voltage VFS Output Common-Mode Voltage VCM DC Drive Capability IDRIVE Integral Nonlinearity INL Differential Nonlinearity DNL Code 0 = 0.35, code 255 = 2.35, VREF = 1.5 Code = 128, VREF = 1.5V (Note 14) Guaranteed monotonic by design Bits 0.30 to 2.20 0.35 to 2.35 0.45 to 2.7 V 1.25 1.35 1.55 V 1 -1 Settling Time From 1/4 FS to 3/4 FS to 1 LSB Update Rate (Note 14) 100 VOS VCM = 2V -8 VOSDRIFT VCM = 2V mA ±1 LSB ±0.5 LSB 5 μs ksps OP AMP A, B, C, D Offset Voltage Offset Drift Input Bias Current IBIAS Common-Mode Rejection Ratio Gain Bandwidth Product Input Common-Mode Range ±2 TA = +25°C (Note 13) CMMR GB mV μV/°C 1 60 CMRNG +8 10 nA 80 dB > 200 kHz 1 VAVDD V TEMPERATURE SENSOR Sensitivity Code 0 = -273.15C; absolute 0; 8 LSB/°C for VREF = 1.5V, 12-bit ADC; 4 LSB/°C for VREF = 3.0V Raw Accuracy No correction, T = 300°K (Note 14) -6 Code 0 = 0, code 1 = 62.5μA, code 255 = 15.94mA 8 2.9304 mV/°C +6 °C CURRENT SINK Resolution Full-Scale Sink Current IS15 Zero-Scale Sink Current IS0 Code = 255, VDS = 2V, VREF = 1.5V Code = 0, VDS = 2V LSB Size LSB VDS = 2V, VREF = 1.5V 14.9 Bits 15.94 18.0 mA 0 1 μA 62.5 μA SPI: MASTER MODE (See Figures 1, 2) SPI Master Operating Frequency 1/tMCK f SYS/2 tMCK/ 2 - tRF MHz SCLK Output Pulse WidthHigh/Low tMCH, tMCL I/O Rise/Fall Time (This parameter is device dependent.) tRF MOSI Output Valid to SCLK Sample Edge (MOSI Setup) tMOV tMCK/ 2 - tRF ns MOSI Output Hold After SCLK Sample Edge tMOH tMCK/ 2 - tRF ns CL = 15pF, pullup = 560 ns 16 ns _______________________________________________________________________________________ 5 MAXQ8913 RECOMMENDED DC OPERATING CONDITIONS (continued) MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control RECOMMENDED DC OPERATING CONDITIONS (continued) (VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL SCLK Last Sample Edge to MOSI Output Change (MOSI Last Hold) tMLH MISO Input Valid to SCLK Sample Edge (MISO Setup) tMIS MISO Input Hold After SCLK Sample Edge tMIH CONDITIONS (Note 13) MIN TYP MAX UNITS tMCK/ 2 - tRF ns 2tRF ns 0 ns SPI: SLAVE MODE (See Figures 1, 3) SPI Slave Operating Frequency SCLK Input Pulse-Width High/Low I/O Rise/Fall Time (This parameter is device dependent.) 1/t SCK f SYS/4 t SCK/ 2 - tRF t SCH, t SCL tRF CL = 15pF, pullup = 560 kHz ns 16 ns SSEL Active to First Shift Edge t SSE tRF ns MOSI Input to SCLK Sample Edge Rise/Fall Setup t SIS tRF ns MOSI Input from SCLK Sample Edge Transition Hold t SIH tRF ns MISO Output Valid After SCLK Shift Edge Transition t SOV SSEL Inactive to Next SSEL Asserted t SSH t SYS + tRF ns SCLK Inactive to SSEL Deasserted t SD tRF ns MISO Output Disabled After SSEL Edge Deasserted t SLH Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: 6 (Note 13) 2tRF 2t SYS + 2tRF ns ns Specifications to -20°C are guaranteed by design and are not production tested. Connect to ground through a 1µF capacitor. Crystal connected to HFXIN, HFXOUT. Operating in /1 mode. Measured on the DVDD pin and the device not in reset. All inputs are connected to GND or DVDD. Outputs do not source/sink any current. One timer B enabled, with the device executing code from flash. ISTOP is the total current into the device when the device is in stop mode. Regulator, brownout disabled. Stop mode current through AVDD and DVDD. Regulator disabled, brownout enabled. Stop mode current through AVDD and DVDD. Regulator enabled, brownout enabled. IOH(MAX) + IOL(MAX) for all outputs combined should not exceed 35mA to meet the specification. VREF = VAVDD. The operational input voltage range for each individual input of a differentially configured pair is from GND to AVDD. The operational input voltage difference is from -VREF/2 to +VREF/2. The typical value is applied when a conversion is requested with ADPMO = 0. Under these conditions, the minimum delay is met. If ADPMO = 1, the user is responsible for ensuring the 4µs delay time is met. Total on-board decoupling capacitance on the AVDD pin < 100nF. The output impedance of the regulator driving the AVDD pin < 10Ω. This value is the sum of input R/F and output R/F. Guaranteed by design and characterization. _______________________________________________________________________________________ 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control SAMPLE SHIFT MAXQ8913 SHIFT SAMPLE SSEL (SAS = 0) tMCK SCLK CKPOL/CKPHA 1/0 1/0 0/1 0/1 tMCH SCLK CKPOL/CKPHA tMCL 1/1 1/1 0/0 0/0 tMOH tMOV MSB MOSI tRF MSB-1 tMIS LSB tMIH MSB MISO tMLH MSB-1 LSB Figure 1. Enhanced SPI Master Timing SHIFT SSEL (SAS = 0) SAMPLE SHIFT SAMPLE tSSE tSSH tSCK tSD SCLK CKPOL/CKPHA 0/1 tSCH tSCL SCLK CKPOL/CKPHA 1/1 tSIS MOSI tSIH MSB MSB-1 tSOV MISO MSB LSB tRF MSB-1 tSLH LSB Figure 2. Enhanced SPI Slave Mode Timing (CKPHA = 1) _______________________________________________________________________________________ 7 MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control SHIFT SSEL (SAS = 0) SAMPLE SHIFT SAMPLE tSSE tSSH tSCK tSD SCLK CKPOL/CKPHA 1/0 tSCH tSCL SCLK CKPOL/CKPHA 0/0 tSIS MOSI tSIH MSB MSB-1 tSOV MISO MSB LSB tRF MSB-1 tSLH LSB MSB Figure 3. Enhanced SPI Slave Mode Timing (CKPHA = 0) 8 _______________________________________________________________________________________ 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control (VDVDD = 1.8V to 3.6V, TA = -40°C to +85°C.) (See Figure 4.) PARAMETER SYMBOL STANDARD MODE TEST CONDITIONS MIN MAX 0.3 x VDVDD -0.5 0.3 x VDVDD (Note 15) V 0.7 x VDVDD (Note 16) V VIL_I2C -0.5 Input High Voltage VIH_I2C 0.7 x VDVDD VIHYS_I2C VDVDD > 2V Output Logic-Low (Open Drain or Open Collector) VOL_I2C VDVDD > 2V, 3mA sink current Output Fall Time from VIH(MIN) to VIL(MAX) with Bus Capacitance from 10pF to 400pF (Notes 17, 18) t OF_I2C Pulse Width of Spike Filtering That Must Be Suppressed by Input Filter t SP_I2C Input Current Each I/O Pin with an Input Voltage Between 0.1 x VDVDD and 0.9 x VDVDD(MAX) (Note 19) I IN_I2C I/O Capacitance CIO_I2C UNITS MAX Input Low Voltage Input Hysteresis (Schmitt) FAST MODE MIN 0.05 x VDVDD 0 -10 V 0.4 0 0.4 V 250 20 + 0.1CB 250 ns 0 50 ns -10 +10 μA 10 pF +10 10 Note 15: Devices that use nonstandard supply voltages that do not conform to the intended I2C-bus system levels must relate their input levels to the VDVDD voltage to which the pullup resistors RP are connected. Note 16: Maximum VIH_I2C = VDVDD(MAX) + 0.5V. Note 17: CB = capacitance of one bus line in pF. Note 18: The maximum fall time of 300ns for the SDA and SCL bus lines as shown in the I2C Bus Controller Timing table is longer than the specified maximum tOF_I2C of 250ns for the output stages. This allows series protection resistors (Rs) to be connected between the SDA/SCL pins and the SDA/SCL bus lines as shown in the I2C Bus Controller Timing (Acting as I2C Slave) table without exceeding the maximum specified fall time. See Figure 4. Note 19: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VDVDD is switched off. VDVDD VDVDD I2C DEVICE I2C DEVICE RP RS RS RS RP RS SDA SCL Figure 4. Series Resistors (RS) for Protecting Against High-Voltage Spikes _______________________________________________________________________________________ 9 MAXQ8913 I2C BUS CONTROLLER AC CHARACTERISTICS MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control I2C BUS CONTROLLER TIMING (All values referenced to VIH_I2C(MIN) and VIL_I2C(MAX). See Figure 5.) PARAMETER Operating Frequency SYMBOL STANDARD MODE MIN MAX 100 FAST MODE MIN MAX 0 400 UNITS f I2C 0 Hold Time After (Repeated) START tHD:STA 4.0 0.6 μs Clock Low Period tLOW_I2C 4.7 1.3 μs Clock High Period μs tHIGH_I2C 4.0 0.6 Setup Time for Repeated START t SU:STA 4.7 0.6 Hold Time for Data (Notes 20, 21) tHD:DAT 0 Setup Time for Data (Note 22) t SU:DAT 250 SDA/SCL Fall Time (Note 23) SDA/SCL Rise Time (Note 23) μs 3.45 0 tF_I2C 300 20 + 0.1CB 0.9 300 ns tR_I2C 1000 300 ns 100 t SU:STO 4.0 20 + 0.1CB 0.6 Bus-Free Time Between STOP and START tBUF 4.7 1.3 Capacitive Load for Each Bus Line CB Setup Time for STOP kHz 400 μs ns μs μs 400 pF Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) VNL_I2C 0.1 x VDVDD 0.1 x VDVDD V Noise Margin at the High Level for Each Connected Device (Including Hysteresis) VNH_I2C 0.2 x VDVDD 0.2 x VDVDD V Note 20: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIH_I2C(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 21: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW_I2C) of the SCL signal. Note 22: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU:DAT ≥ 250ns must be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR_I2C(MAX) + tSU:DAT = 1000 + 250 = 1250ns (according to the standard-mode I2C specification) before the SCL line is released. Note 23: CB = Total capacitance of one bus line in pF. 10 ______________________________________________________________________________________ 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control PARAMETER SYMBOL System Frequency f SYS Operating Frequency f I2C STANDARD MODE MIN MAX 1 FAST MODE MIN MAX 3.60 f SYS/8 UNITS MHz f SYS/8 Hz Hold Time After (Repeated) START tHD:STA tHIGH_I2C tHIGH_I2C μs Clock Low Period tLOW_I2C 5 5 t SYS Clock High Period tHIGH_I2C 3 3 t SYS Setup Time for Repeated START t SU:STA tLOW_I2C Hold Time for Data tHD:DAT 0 Setup Time for Data t SU:DAT 250 SDA/SCL Fall Time tLOW_I2C μs 3.45 0 0.9 tF_I2C 300 20 + 0.1CB 300 ns SDA/SCL Rise Time tR_I2C 1000 20 + 0.1CB 300 ns Setup Time for STOP 100 μs ns t SU:STO tHIGH_I2C tHIGH_I2C μs Bus-Free Time Between STOP and START tBUF tLOW_I2C tLOW_I2C μs Capacitive Load for Each Bus Line CB 400 400 pF Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) VNL_I2C 0.1 x VDVDD 0.1 x VDVDD V Noise Margin at the High Level for Each Connected Device (Including Hysteresis) VNH_I2C 0.2 x VDVDD 0.2 x VDVDD V I2C BUS CONTROLLER TIMING (ACTING AS I2C SLAVE) PARAMETER SYMBOL System Frequency f SYS Operating Frequency f I2C System Clock Period STANDARD MODE MIN MAX 1 FAST MODE MIN MAX 3.60 f SYS/8 UNITS MHz f SYS/8 Hz 1/f I2C μs t SYS 1/f I2C Hold Time After (Repeated) START tHD:STA 3t SYS 3t SYS μs Clock Low Period tLOW_I2C 5t SYS 5t SYS μs Clock High Period μs tHIGH_I2C 3t SYS 3t SYS Setup Time for Repeated START t SU:STA 5t SYS 5t SYS Hold Time for Data tHD:DAT 0 Setup Time for Data t SU:DAT 250 SDA/SCL Fall Time μs 3.45 0 0.9 tF_I2C 300 20 + 0.1CB 300 ns SDA/SCL Rise Time tR_I2C 1000 300 ns Setup Time for STOP 100 t SU:STO 3t SYS 20 + 0.1CB 3t SYS Bus-Free Time Between STOP and START tBUF 5t SYS 5t SYS Capacitive Load for Each Bus Line CB 400 μs ns μs μs 400 pF Noise Margin at the Low Level for Each Connected Device (Including Hysteresis) VNL_I2C 0.1 x VDVDD 0.1 x VDVDD V Noise Margin at the High Level for Each Connected Device (Including Hysteresis) VNH_I2C 0.2 x VDVDD 0.2 x VDVDD V ______________________________________________________________________________________ 11 MAXQ8913 I2C BUS CONTROLLER TIMING (ACTING AS I2C MASTER) MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control S Sr P S SDA tBUF tR_I2C tF_I2C tLOW tSU:DAT tSU:STA SCL tHD:STA tHIGH tHD:DAT tSU:STO NOTE: TIMING REFERENCED TO VIH_I2C(MIN) AND VIL_I2C(MAX). Figure 5. I2C Timing Diagram OUTPUT CODE (HEX) 3FE FS = VREF 1 LSB = VREF/1024 ZS = 0 1FF 1FE OUTPUT CODE (HEX) 3FF 3FD 004 003 002 +FS = VREF/2 -FS = -VREF/2 1 LSB = VREF/1024 ZS = 0 001 000 3FF 201 FS - 0.5 LSB 001 -FS + 0.5 LSB 200 +FS - 0.5 LSB 000 1 2 3 4 FS INPUT VOLTAGE (LSB) Figure 6. Single-Ended Unipolar Transfer Function 12 -FS 0 INPUT VOLTAGE (LSB) Figure 7. Differential Bipolar Transfer Function ______________________________________________________________________________________ +FS 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control OUTA MAXQ20 16-BIT RISC CORE INAAIN2 INA+ DAC1 OUTB INB- RIN+ RIN- 10-BIT DAC AIN3 INB+ OUTC INC- DAC2 AIN4 INC+ LIN+ LIN- 10-BIT DAC OUTD INDAIN5 IND+ 1.5V REFERENCE AVDD AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 REF 12-BIT SAR DAC MUX TEMP SENSOR MAXQ8913 DAC3 8-BIT DAC 8-BIT 8-BIT PORT 0 AND INTERRUPT P0.0/INT0/TCK P0.1/INT1/TDI P0.2/INT2/TMS P0.3/INT3/TDO P0.4/INT4/SSEL P0.5/INT5/SCLK P0.6/INT6/MOSI P0.7/INT7/MISO PORT 1 AND INTERRUPT P1.0/INT8/SCL/TX P1.1/INT9/SDA/RX P1.2/INT10/TB0A P1.3/INT11/TB0B JTAG CURRENT SINK SRAM 4KB UTILITY ROM 4KB HFXIN HFXOUT WATCHDOG TIMER DVDD DGND AVDD AGND RST 8-BIT DAC FLASH 64KB CLOCK GENERATOR RC OSC, HF CRYSTAL OSC, 1MHz RING OSC REG18 POWER-ON RESET, BROWNOUT MONITOR CURRENT SINK DAC4 SINK2 1.8V CORE LDO REG AIN6 AGND SINK1 SYNCIN FAULT SHDNR SHDNL CLASS D-AMP CONTROL REFA 4-WIRE (SPI) INTERFACE I2 C USART TIMER B 16 x 16 HARDWARE MULTIPLY ACCUMULATE UNIT ______________________________________________________________________________________ 13 MAXQ8913 Block Diagram 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control MAXQ8913 Pin Description PIN NAME FUNCTION POWER PINS L4 DVDD Digital Supply Voltage M5 DGND Digital Ground E4 AVDD Analog Supply Voltage B5 AGND Analog Ground K1 REG18 Regulator Output. This pin must be connected to ground through a 1.0μF capacitor. It provides the 1.8V internal regulated output. This pin is not meant to provide power externally. ANALOG MEASUREMENT PINS 14 G2 REFA Analog Voltage Reference. When using an external reference source, this pin must be connected to 1μF and a 0.01μF filter capacitors in parallel. When using an internal reference source, this pin must be connected to a 0.01μF capacitor. The external reference can only be used for the ADC. A8 INA+ Operational Amplifier A Noninverting Input. This analog input pin serves as the operational amplifier A noninverting input. B7 INA- Operational Amplifier A Inverting Input. This analog input pin serves as the operational amplifier A inverting input. B9 OUTA Operational Amplifier A Output. This analog input pin serves as the operational amplifier A output. This pin is also internally connected to the ADC input mux. D3 INB+ Operational Amplifier B Noniverting Input. This analog input pin serves as the operational amplifier B noninverting input. A2 INB- Operational Amplifier B Inverting Input. This analog input pin serves as the operational amplifier B inverting input. B3 OUTB Operational Amplifier B Output. This analog input pin serves as the operational amplifier B output. This pin is also internally connected to the ADC input mux. E2 INC+ Operational Amplifier C Noninverting Input. This analog input pin serves as the operational amplifier C noninverting input. C2 INC- Operational Amplifier C Inverting Input. This analog input pin serves as the operational amplifier C inverting input. B1 OUTC Operational Amplifier C Output. This analog input pin serves as the operational amplifier C output. This pin is also internally connected to the ADC input mux. F1 IND+ Operational Amplifier D Noninverting Input. This analog input pin serves as the operational amplifier A noninverting input. F3 IND- Operational Amplifier D Inverting Input. This analog input pin serves as the operational amplifier D inverting input. D1 OUTD Operational Amplifier D Output. This analog input pin serves as the operational amplifier D output. This pin is also internally connected to the ADC input mux. H1 AIN0 H3 AIN1 C6 DAC3 DAC3 Single-Ended Output C4 DAC4 DAC4 Single-Ended Output A6 SINK1 Programmable Current Sink 1 A4 SINK2 Programmable Current Sink 2 ADC Input 0, 1. These two analog pins function as single-ended ADC inputs or a differential pair. ______________________________________________________________________________________ 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control PIN NAME C8 DAC1 DAC1 Buffer Output. Positive terminal of the differential DAC1’s output buffered signal. FUNCTION D7 DAC2 DAC2 Buffer Output. Positive terminal of the differential DAC2’s output buffered signal. E6 LIN+ DAC2 Output. Positive DAC output voltage to drive the left Class D amplifier. D9 LIN- DAC2 Output. Negative DAC output voltage to drive the left Class D amplifier. H9 RIN+ DAC1 Output. Positive DAC output voltage to drive the right Class D amplifier. H7 RIN- DAC1 Output. Negative DAC output voltage to drive the right Class D amplifier. RESET PIN N6 RST Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low and begins executing from the reset vector when released. The pin includes a pullup current source and should be driven by an open-drain external source capable of sinking in excess of 4mA. This pin is driven low as an output when an internal reset condition occurs. CLOCK PINS High-Frequency Crystal Input. Connect an external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input for an external high-frequency CMOS clock source when HFXOUT is floating. M1 HFXIN J2 HFXOUT High-Frequency Crystal Output. Connect an external crystal or resonator between HFXIN and HFXOUT as the high-frequency system clock. Alternatively, float HFXOUT when an external high-frequency CMOS clock source is connected to the HFXIN pin. F9 SYNCIN SYNCIN Clock. This pin acts as the input clock to the Class D amplifier’s sawtooth generator. SYNCIN is a divided system clock with the divide ratio set by programmable bits. GENERAL-PURPOSE I/O, SPECIAL FUNCTION PINS M9 P0.0 I/O with Interrupt or JTAG Test Clock. This pin defaults as an input with weak pullup after a reset P.0.0/INT0/ and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special function TCK disables the general-purpose I/O on the pin and makes the pin function as the test clock input. Note that the JTAG function can be disabled using the TAP bit in the SC register. L8 P0.1/INT1/ TDI P0.1 I/O with Interrupt or JTAG Test Data In. This pin defaults as an input with a weak pullup after a reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special function disables the general-purpose I/O on the pin and makes the pin function as the test data input. Note that the JTAG function can be disabled using the TAP bit in the SC register. P0.2/INT2/ TMS P0.2 I/O with Interrupt or JTAG Test Mode Select. This pin defaults as an input with a weak pullup after a reset and functions as a general-purpose I/O with interrupt capability. Enabling the pin’s special function disables the general-purpose I/O on the pin and makes the pin function as the test mode select. Note that the JTAG function can be disabled using the TAP bit in the SC register. The TMS should be gated high when JTAG is disabled. J6 P0.3/INT3/ TDO P0.3 I/O with Interrupt or JTAG Test Data Out. This pin defaults as an input with a weak pullup after a reset and functions as a general-purpose I/O with interrupt capability. The output function of the test data is only enabled during the TAP’s Shift_IR or Shift_DR states. Enabling the pin's special function disables the general-purpose I/O on the pin and makes the pin function as the test data output. Note that the JTAG function can be disabled using the TAP bit in the SC register. N8 P0.4/INT4/ SSEL P0.4 I/O with Interrupt or SPI Chip Select. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI chip select. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit. M7 P0.5/INT5/ SCLK P0.5 I/O with Interrupt or SPI Clock. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI clock. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit. K7 ______________________________________________________________________________________ 15 MAXQ8913 Pin Description (continued) 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control MAXQ8913 Pin Description (continued) PIN NAME FUNCTION L6 P0.6/INT6/ MOSI P0.6 I/O with Interrupt or Master Out-Slave In. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI master out-slave in. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit. K5 P0.7/INT7/ MISO P0.7 I/O with Interrupt or Master In-Slave Out. This port pin functions as a bidirectional I/O pin with interrupt capability or as the SPI master in-slave out. This port pin defaults to an input with a weak pullup after a reset and functions as a general-purpose I/O. The port pad also contains a Schmitt input circuit. P1.0/INT8/ SCL/TX P1.0 I/O with Interrupt or I2C Clock or USART Transmit. This pin defaults to an input with a weak pullup after reset and functions as a general-purpose I/O with interrupt capability. The port pad contains a Schmitt input circuit. Enabling the pin’s special function disables the general-purpose I/O on the pin and enables the I2C clock or USART transmitter function. P1.1/INT9/ SDA/RX P1.1 I/O with Interrupt or I2C Data or USART Receive. This pin defaults to an input with a weak pullup after reset and functions as a general-purpose I/O with interrupt capability. The port pad contains a Schmitt input circuit. Enabling the pin’s special function disables the general-purpose I/O on the pin and enables the I2C data or USART receiver function. N4 M3 K3 P1.2 I/O with Interrupt or Timer B0 Pin A. This pin defaults to an input with a weak pullup after reset P1.2/INT10/ and functions as a general-purpose I/O. The port pad contains a Schmitt input circuit. Enabling the pin’s special function disables the general-purpose I/O on the pin and enables the timer B pin A TB0A function. L2 P1.3 I/O with Interrupt or Timer B0 Pin B. This pin defaults to an input with a weak pullup after reset P1.3/INT11/ and functions as a general-purpose I/O. The port pad contains a Schmitt input circuit. Enabling the TB0B pin’s special function disables the general-purpose I/O on the pin and enables the timer B pin B function. MISCELLANEOUS PINS E8 SHDNL Shutdown for Left Motor Driver. Shutdown signal for the motor drivers. G8 SHDNR Shutdown for Right Motor Driver. Shutdown signal for the motor drivers. F7 FAULT Fault Indicator. Thermal or short circuit fault indicator from the driver IC. NO CONNECTION PINS D5, F5, G6, G4, H5, J4, J8, K9, N2 16 N.C. No Connection. Reserved for future use. Leave these pins unconnected. ______________________________________________________________________________________ 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control The following is an introduction to the primary features of the microcontroller. More detailed descriptions of the device features can be found in the data sheets, errata sheets, and user’s guides described later in the Additional Documentation section. MAXQ Core Architecture The MAXQ core is a low-cost, high-performance, CMOS, fully static, 16-bit RISC microcontroller with flash memory. The MAXQ8913 supports 7 channels of high-performance measurement using a 10-bit successive approximation register (SAR) ADC with internal reference. These parts are structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations are completed in one cycle without pipelining because the instruction contains both the op code and data. The result is a streamlined microcontroller performing at up to 1 million instructions per second (MIPS) for each MHz of the system operating frequency. The highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. Data can be quickly and efficiently manipulated with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention. As a result, application speed is greatly increased. Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The instruction set is highly orthogonal, allowing arithmetic and logical operations to use any register along with the accumulator. Special function registers control the peripherals and are subdivided into register modules. The family architecture is modular so new devices and modules can reuse code developed for existing products. The architecture is transport triggered. This means that writes or reads from certain register locations can also cause side effects to occur. These side effects form the basis for the higher level op codes defined by the assembler, such as ADDC, OR, JUMP, etc. The op codes are actually implemented as MOVE instructions between certain register locations, while the assembler handles the encoding, which need not be a concern to the programmer. The 16-bit instruction word is designed for efficient execution. Bit 15 indicates the format for the source field of the instruction. Bits 0 to 7 represent the source for the transfer. Depending on the value of the format field, this can be either an immediate value or a source register. If this field represents a register, the lower 4 bits contain the module specifier and the upper 4 bits contain the register index in that module. Bits 8 to 14 represent the destination for the transfer. This value always represents a destination register, with the lower 4 bits containing the module specifier and the upper 3 bits containing the register subindex within that module. Any time that it is necessary to directly select one of the upper 24 registers as a destination, the prefix register, PFX, is needed to supply the extra destination bits. This prefix register write is inserted automatically by the assembler and requires only one additional execution cycle. Memory Organization The device incorporates several memory areas: • 4KB utility ROM • 64KB of flash memory for program storage • 4KB of SRAM for storage of temporary variables • 16-level stack memory for storage of program return addresses and general-purpose use The incorporation of flash memory allows the devices to be reprogrammed multiple times allowing modifications to user applications post production. Additionally, the flash can be used to store application information including configuration data and log files. The default memory organization is organized as a Harvard architecture, with separate address spaces for program and data memory. Pseudo-Von Neumann memory organization is supported through the utility ROM for applications that require dynamic program modification and execution from RAM. The pseudo-Von Neumann memory organization places the code, data and utility ROM memories into a single contiguous memory map. Stack Memory A 16-bit-wide hardware stack provides storage for program return addresses and can also be used as general-purpose data storage. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and when an interrupt is serviced. An application can also store values in the stack explicitly by using the PUSH, POP, and POPI instructions. ______________________________________________________________________________________ 17 MAXQ8913 Detailed Description MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP. Utility ROM The utility ROM is a 4KB block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from application software. These include the following: • In-system programming (bootstrap loader) using JTAG interface • In-circuit debug routines • Test routines (internal memory tests, memory loader, etc.) • User-callable routines for in-application flash programming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the special routines mentioned. Routines within the utility ROM are user accessible and can be called as subroutines by the application software. More information on the utility ROM contents is contained in the MAXQ Family User’s Guide: MAXQ8913 Supplement. Some applications require protection against unauthorized viewing of program code memory. For these applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied. The password is defined as the 16 words of physical program memory at addresses 0010h to 001Fh. reduce the life-cycle cost of the embedded system. These features can be password protected to prevent unauthorized access to code memory. (Bootloader) In-System Programming An internal bootstrap loader allows the device to be reloaded over a simple JTAG interface. As a result, software can be upgraded in-system, eliminating the need for a costly hardware retrofit when updates are required. Remote software updates enable application updates to physically inaccessible equipment. The interface hardware can be a JTAG connection to another microcontroller or a connection to a PC serial port using a serial-to-JTAG converter such as the MAXQJTAG-001, available from Maxim. If in-system programmability is not required, a commercial gang programmer can be used for mass programming. Activating the JTAG interface and loading the test access port (TAP) with the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset through the JTAG interface executes the bootstrap-loader mode program that resides in the utility ROM. When programming is complete, the bootstrap loader can clear the SPE bit and reset the device, allowing the device to bypass the utility ROM and begin execution of the application software. The following bootstrap loader functions are supported: • Load • Dump • CRC • Verify • Erase A single password lock (PWL) bit is implemented in the SC register. When the PWL is set to one (power-on reset default) and the contents of the memory at addresses 0010h to 001Fh are any value other than FFh or 00h, the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When PWL is cleared to zero, these utilities are fully accessible without password. The password is automatically set to all ones following a mass erase. In-Application Programming The in-application programming feature allows the microcontroller to modify its own flash program memory while simultaneously executing its application software. This allows on the fly software updates in mission-critical applications that cannot afford downtime. Alternatively, it allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the MAXQ Family User’s Guide: MAXQ8913 Supplement. Programming Register Set The flash memory of the microcontroller can be programmed by two different methods: in-system programming and in-application programming. Both methods afford great flexibility in system design as well as Most functions of the device are controlled by sets of registers. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are 18 ______________________________________________________________________________________ 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control Programmable Timer The microcontroller incorporates one instance of the 16-bit programmable timer/counter B peripheral. It can be used in counter/timer/capture/compare/PWM functions, allowing precise control of internal and external events. The timer/counter supports clock input prescaling and set/reset/toggle PWM/output control functionality not found on other MAXQ timer implementations. A new register, TBC, supports PWM/output control functions. A distinguishing characteristic of timer/counter B is that its count ranges from 0000h to the value stored in the 16-bit capture/reload register (TBR) counting up. The timer/counter B timer is fully described in the MAXQ Family User’s Guide: MAXQ8913 Supplement. Timer B operational modes include the following: • Autoreload • Autoreload using external pin • Capture using external pin • Up/down count using external pin • Up-count PWM/output • Up/down PWM/output • Clock output on TBxB pin • Up/down PWM mode with double-buffered output mode: • On interrupt, the user loads buffered output data, which does not begin sending until current iteration is completed. This enables a glitchless PWM because there is no output pause while interrupt is being serviced, and a race condition does not occur in setting TBC before it is used. A TBC value written after timer rollover becomes effective during the following counter cycle. Watchdog Timer An internal watchdog timer greatly increases system reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running counter designed to be periodically reset by the application software. If software is operating correctly, the counter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset and optionally a watchdog timer interrupt. This protects the system against electrical noise or electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. The internal watchdog timer is an upgrade to older designs with external watchdog devices, reducing system cost and simultaneously increasing reliability. The watchdog timer is controlled through bits in the WDCN register. Its timeout period can be set to one of four programmable intervals ranging from 212 to 221 system clocks in its default mode, allowing flexibility to support different types of applications. The interrupt occurs 512 system clocks before the reset, allowing the system to execute an interrupt and place the system in a known, safe state before the device performs a total system reset. At 10MHz, watchdog timeout periods can be programmed from 410µs to 54s, depending on the system clock mode. Op Amps The MAXQ8913 contains four uncommitted op amps. It is electrically acceptable for op-amp outputs to exceed the reference voltage, but they saturate the ADC code. Gains and offsets introduced in the op-amp circuits should be carefully set to maintain the outputs of the op amps at or below the reference voltage if the ADC converted values are expected to be unsaturated. The device provides REFA as an output to aid in this endeavor. The outputs of the op amps are internally connected to ADC channels 2 to 5. Unused op amps should be connected with their “+” input terminal grounded and the output and “-” input terminals shorted together. Differential DAC and External Class D Amplifier Output Stage Operation The power stage of the MAXQ8913 is designed to drive a stereo Class D amplifier (DAMP). These amplifiers are ______________________________________________________________________________________ 19 MAXQ8913 divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality that could be included by different products based on the MAXQ architecture. This functionality is broken up into discrete modules so that only the features required for a given product need to be included. The module and register functions are covered fully in the MAXQ Family User’s Guide and the MAXQ Family User’s Guide: MAXQ8913 Supplement. This information includes the locations of status and control bits and a detailed description of their function and reset values. Refer to this documentation for a complete understanding of the features and operation of the microcontroller. MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control suitable for driving self-commutating DC motors or voice coil motors. Each external DAMP is differentially driven by a 10-bit DAC. The DAC output common mode is 1.25V, based on the bandgap reference, and each differential output can swing from GND to 2.5V (if VDVDD ≥ 3V), so the effective differential peak-to-peak voltage is 5V. The DAMP has a 6dB gain, so its ouput can swing 10V (if DAMP supply = 5V). The differential output voltage follows the simple formula: VDIFF = 2.5 x (code - 512)/512V There are four Class D amplifier control bits and one status bit. The SHDNR and SHDNL pins are the activehigh shutdown controls for the two Class D amplifiers, respectively. The SYNCIN_DIV bits control the input clock to the Class D amplifier sawtooth generator. The SYNCIN frequency must fall within 2MHz and 2.8MHz. The optimal frequency is 2.2MHz. The frequency of the high-frequency oscillator and the divide ratio need to be chosen wisely to accomodate this requirement. For example, if a 9MHz crystal is used, a divide-by-4 ratio produces a SYNCIN frequency of 2.25MHz. Table 1 shows the divide ratio applied to the high-frequency oscillator output based on the value of SYNCIN_DIV. Table 1. SYNCIN Divisor vs. SYNCIN_DIV Value SYNCIN_DIV HF DIVIDED BY 0 (default) SYNCIN clock off 1 2 2 3 3 4 To start operating the DACs and DAMPs, the following procedural steps should be followed: 1) Set both DAC inputs to code 512. 2) Enable the SYNCIN clock by setting an appropriate value for SYNCIN_DIV. 3) Wait 100µs. Clear the SHDNR and SHDNL bits. 4) Wait 100µs. One or both DAMPs can be shut down at any time by setting the corresponding SHDN bit. If both DAMPs are shut down, the firmware should disable the SYNCIN signal. 20 The DAMP FAULT bit goes high for at least 500ns following a thermal shutdown or current-limit event. It stays low in shutdown and is glitch-free during powerup. FAULT interrupts the microcontroller if enabled. Alternatively, the firmware can poll the bit periodically to detect faults of the type previously described. DAC1 and DAC2 Buffers While the MAXQ8913 contains power drivers for the actuator, the positive terminal of each differential DAC output pair is buffered and available as an output pin. This feature is intended primarily for test, and no significant load should be added to the DAC1 and DAC2 pins. The specifications for these pins are not yet determined, except for the no-load output voltage, which is expected to be between GND and 2.5V. DAC3 and DAC4 DAC3 and DAC4 are single-ended DACs. Their outputs are intended for driving the positive terminal (through a resistor) of single-supply op amps to force the virtual GND to a value that allows the op amp to operate below and above the virtual ground DC value. Operated in this fashion, the DACs can also serve as offset cancellation devices as necessary. SINK1 and SINK2 Popular optical-image stabilization implementations include the use of Hall-effect elements for position feedback. Hall-effect elements require a current to flow through two of its terminals for proper operation. The device includes two current sinks intended to drive these elements. The current sinks are programmable between 0 and 15.94mA with 62.5mA resolution through an 8-bit code. Code 0 turns them off. When operating Hall-effect elements from 3V, the maximum achievable current is given by (3V - 0.5V)/RHALL, where 0.5V is the minimum voltage value at the input of the current sink. For example, if RHALL = 250Ω, the maximum current is 10mA. If higher currents are desirable, the user must provide a larger supply voltage to the Hall-effect element. In this case, care must be exercised so that the output nodes of the Hall-effect element do not exceed V AVDD . Exceeding V AVDD could cause the input-protection diodes of the op-amp terminals to begin conduction and waste power when the device is in sleep mode. If supplying a voltage larger than VAVDD to the Hall-effect element, a switchable supply is recommended to avoid the leakage path identified above. ______________________________________________________________________________________ 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control Designers must have four documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user’s guides offer detailed information about device features and operation. • This MAXQ8913 data sheet, which contains electrical/timing specifications and pin descriptions. • The MAXQ8913 errata sheet for the specific device revision, available at www.maxim-ic.com/errata. • The MAXQ Family User's Guide , which contains detailed information on core features and operation, including programming. This document is available on our website at www.maxim-ic.com/MAXQUG. Development and Technical Support A variety of highly versatile, affordably priced development tools for this microcontroller are available from Maxim and third-party suppliers, including: • Compilers • In-circuit emulators • Integrated development environments (IDEs) • JTAG-to-serial converters for programming and debugging. A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. For technical support, go to https://support.maximic.com/micro. • The MAXQ Family User's Guide: MAXQ8913 Supplement, which contains detailed information on features specific to the MAXQ8913. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 58 WLP W584B2+1 21-0220 ______________________________________________________________________________________ 21 MAXQ8913 Additional Documentation MAXQ8913 16-Bit, Mixed-Signal Microcontroller with Op Amps, ADC, and DACs for All-in-One Servo Loop Control Pin Configuration MAXQ8913 TOP VIEW 1 2 3 4 5 6 7 8 9 + INB- A B OUTC C D OUTD G AIN0 J P1.3/ INT11/ TB0B L N N.C. SHDNR P0.3/ INT3/ TDO P0.2/ INT2/ TMS N.C. P0.1/ INT1/ TDI P0.5/ INT5/ SCLK DGND P1.0/ INT8/SCL/ TX RIN+ N.C. P0.6/ INT6/ MOSI DVDD SYNCIN RIN- P0.7/ INT7/ MISO P1.1/ INT9/SDA/ RX HFXIN SHDNL N.C. N.C. LIN- FAULT N.C. P1.2/ INT10/ TBOA REG18 DAC2 N.C. AIN1 OUTA DAC1 LIN+ N.C. HFXOUT INA- N.C. IND- INA+ DAC3 AVDD REFA H AGND INB+ IND+ SINK1 DAC4 INC+ F M OUTB INC- E K SINK2 RST P0.0/ INT0/ TCK P0.4/ INT4/ SSEL WLP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.