CY28158 Spread Spectrum Timing Solution for Serverworks Chipset Features Key Specifications • Maximized EMI suppression using Cypress’s spread spectrum technology • Based on Industry Standard CK133 Pinout with all outputs compliant to CK98 specifications • 0.5% downspread outputs deliver up to 10dB lower EMI • 6 skew-controlled copies of CPU output • 6 copies of PCI output (synchronous w/CPU output) • 2 copies of 66 MHz fixed frequency 3.3V clock • 3 copies of 16.67 MHz IOAPIC clock, synchronous to CPU clock • 1 copy of 48 MHz USB output • 2 copies of 14.31818 MHz reference clock • Programmable to 133 or 100 MHz operation • Power management control pins for clock stop and shut down • Available in 56-pin SSOP Supply Voltages:...................................... VDD33 = 3.3V ± 5% ................................................................ VDD25 = 2.5V ± 5% CPU Output Jitter: ....................................................<150 ps CPU Output Skew: ....................................................<175 ps CPU to 3V66 Output Offset: 0.0 to1.5 ns CPU to IOAPIC Output Offset 1.5 to 4.0 ns (CPU leads) CPU to PCI Output Offset................. 0 to 4.0 ns (CPU leads) Table 1. Pin Selectable Frequency. SEL133/100# CPU0:5 (MHz) PCI 1 133 33.3 0 100 33.3 Block Diagram X1 X2 Pin Configuration 2 XTAL OSC REF0:1 CPU_STOP# STOP Clock Logic 6 STOP Clock Logic 2 CPU0:5 PLL 1 SEL133/100# ÷2/÷1.5 3V66_0:1 1 PCI_F ÷2 PWRDWN# STOP Clock Logic 5 PCI1:5 PCI_STOP# Power Down Logic 3 ÷2 IOAPIC0:2 Tristate Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_IOAPIC IOAPIC2 IOAPIC1 IOAPIC0 GND_IOAPIC VDD_CPU CPU5 CPU4 GND_CPU VDD_CPU CPU3 CPU2 GND_CPU VDD_CPU CPU1 CPU0 GND_CPU VDDA GNDA PCI_STOP# CPU_STOP# PWR_DWN# SPREAD# SEL1 SEL0 VDD_48MHZ 48MHZ GND_48MHZ 1 PLL2 Cypress Semiconductor Corporation Document #: 38-07039 Rev. *B GND_REF REF0 REF1 VDD_REF X1 X2 GND_PCI GND_PCI PCI_F VDD_PCI PCI1 PCI2 GND_PCI PCI3 PCI4 VDD_PCI VDD_PCI PCI5 GND_PCI GND_3V66 GND_3V66 VDD_3V66 VDD_3V66 GND_3V66 3V66_0 3V66_1 VDD_3V66 SEL133/100# CY28158 SPREAD# SEL0 SEL1 (CPU leads) 48MHz • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised June 25, 2004 CY28158 Pin Definitions Name X1[1] Pins 5 Description Reference crystal input X2[1] 6 Reference crystal feedback CPU [0–5] 41, 42, 45, 46, 49, 50 CPU clock outputs PCI [1–5] 11, 12, 14, 15, 18 PCI clock outputs, synchronously running at 33.33 MHz PCI_F 9 Free running PCI clock 3V66 [0–1] 25, 26 3V66 clock outputs, running at 66.66 MHz IOAPIC [0–2] 53, 54, 55 IOAPIC clock outputs, running at 16.67 MHz REF [0–1] 2, 3 Reference clock outputs, 14.318 MHz 48MHZ 30 48-MHz USB clock output CPU_STOP# 36 Active LOW input, disables CPU and 3V66 clocks when asserted PCI_STOP# 37 Active LOW input, disables PCI clocks when asserted PWR_DWN# 35 Active LOW input, powers down part when asserted SPREAD# 34 Active LOW input, enables spread spectrum when asserted SEL1 33 CPU frequency select input (See Function Table) SEL0 32 CPU frequency select input (See Function Table) SEL133/100# 28 CPU frequency select input (See Function Table) GND_REF 1 3.3V Reference ground GND_PCI 7, 8, 13, 19 3.3V PCI ground GND_3V66 20, 21, 24 3.3V 66-MHz (AGP) ground GND_48MHZ 29 3.3V 48-MHz (USB) ground GND_IOAPIC 52 2.5V APIC ground GND_CPU 40, 44, 48 2.5V CPU ground GNDA 38 Analog ground to PLL and Core VDD_REF 4 3.3V Reference voltage supply VDD_PCI 10, 16, 17 3.3V PCI voltage supply VDD_3V66 22, 23, 27 3.3V 66-MHz (AGP) voltage supply VDD_48MHZ 31 3.3V 48-MHz (USB) voltage supply VDD_IOAPIC 56 2.5V APIC voltage supply VDD_CPU 43, 47, 51 2.5V CPU voltage supply VDDA 39 Analog voltage supply to PLL and Core Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, “Crystal Oscillator Topics.” Document #: 38-07039 Rev. *B Page 2 of 10 CY28158 Function Table[2] SEL133 /100# SEL1 CPU (MHz) SEL0 3V66 (MHz) PCI (MHz) 48MHZ (MHz) REF (MHz) IOAPIC (MHz) 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 1 100.227[3] 66.818[3] 33.409[3] 48.008[3] 14.318[3] 16.705[3] 0 1 0 100 66.67 33.33 OFF 14.318 16.67 0 1 1 100 66.67 33.33 48.008[3] 14.318 16.67 1 0 0 TCLK/2 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 1 0 1 N/A N/A N/A N/A N/A N/A 1 1 0 133.33 66.67 33.33 OFF 14.318 16.67 1 1 1 133.33 66.67 33.33 48.008[3] 14.318 16.67 Actual Clock Frequency Values Target Frequency (MHz) Clock Output Actual Frequency (MHz) PPM CPU 100.0 99.126 –8740 CPU 133.33 132.769 –4208 48.0 48.008 167 48MHZ Clock Enable Configuration CPU_STOP# PWR_DWN# PCI_STOP# CPU 3V66 PCI PCI_F REF IOAPIC OSC. VCOs X 0 X LOW LOW LOW LOW LOW OFF OFF 0 1 0 LOW LOW LOW ON ON ON ON 0 1 1 LOW LOW ON ON ON ON ON 1 1 0 ON ON LOW ON ON ON ON 1 1 1 ON ON ON ON ON ON ON Clock Driver Impedances Impedance Buffer Name CPU, IOAPIC VDD Range Buffer Type Minimum Ω Typical Ω Maximum Ω 2.375V – 2.625V Type 1 13.5 29 45 48MHZ, REF 3.135V – 3.465V Type 3 20 40 60 PCI, 3V66 3.135V – 3.465V Type 5 12 30 55 Note: 2. TCLK is a test clock driven in on the X1 input in test mode. 3. This selection is defined as “N/A” or “Reserved.” Document #: 38-07039 Rev. *B Page 3 of 10 CY28158 Maximum Ratings Storage Temperature (Non-Condensing) ... –65°C to +150°C (Above which the useful life may be impaired. For user guidelines, not tested.) Max. Soldering Temperature (10 sec) ...................... +260°C Junction Temperature............................................... +150°C Supply Voltage ..................................................–0.5 to +7.0V Package Power Dissipation.............................................. 1W Input Voltage .............................................. –0.5V to VDD+0.5 Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V Operating Conditions[4] Over which Electrical Parameters are Guaranteed Min. Max. Unit VDD_REF, VDD_PCI, VDDA, VDD_3V66, VDD_48MHZ Parameter 3.3V Supply Voltages Description 3.135 3.465 V VDD_CPU CPU Supply Voltage 2.375 2.625 V VDD_IOAPIC IOAPIC Supply Voltage 2.375 2.625 V TA Operating Temperature, Ambient 0 70 °C CL Max. Capacitive Load on CPU, 48MHZ, REF, IOAPIC PCI, 3V66 f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min. Max. Unit VIH High-level Input Voltage Except Crystal Pads. Threshold voltage for crystal pads = VDD/2 2.0 VIL Low-level Input Voltage Except Crystal Pads VOH High-level Output Voltage CPU, IOAPIC VOL Low-level Output Voltage IIH Input High Current 0 < VIN < VDD IIL Input Low Current 0 < VIN < VDD IOH High-level Output Current CPU VOH = 2.0V –16 IOAPIC VOH = 2.0V –20 48 MHZ, REF VOH = 2.4V –15 3V66, PCI VOH = 2.4V –30 CPU VOL = 0.4V 19 IOAPIC VOL = 0.4V 25 48 MHZ, REF VOL = 0.4V 10 3V66, PCI VOL = 0.4V 20 V 0.8 IOH = –1 mA 2.0 48 MHZ, REF, PCI, 3V66 IOH = –1 mA 2.4 CPU, IOAPIC IOL = 1 mA 0.4 48 MHZ, REF, PCI, 3V66 IOL = 1 mA 0.4 V V 10 10 V µA µA mA –60 –72 –51 –100 IOL Low-level Output Current mA 49 58 24 49 IOZ Output Leakage Current Three-state 10 µA IDD2 2.5V Power Supply Current VDDA/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz 90 mA Document #: 38-07039 Rev. *B Page 4 of 10 CY28158 Electrical Characteristics Over the Operating Range (continued) Parameter Description Test Conditions Min. Max. Unit IDD3 3.3V Power Supply Current VDDA/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 133 MHz 160 mA IDDPD2 2.5V Shutdown Current VDDA/VDD33 = 3.465V, VDD25 = 2.625V 100 µA IDDPD3 3.3V Shutdown Current VDDA/VDD33 = 3.465V, VDD25 = 2.625V 200 µA Switching Characteristics[5] Over the Operating Range Min. Max. Unit t1 Parameter All Output Output Duty Cycle[6] Description t1A/t1B 45 55 % t2 CPU, IOAPIC Rising Edge Rate Between 0.4V and 2.0V 1.0 4.0 V/ns t2 48MHZ, REF Rising Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns t2 PCI, 3V66 Rising Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t3 CPU, IOAPIC Falling Edge Rate Between 2.0V and 0.4V 1.0 4.0 V/ns t3 48MHZ, REF Falling Edge Rate Between 2.4V and 0.4V 0.5 2.0 V/ns t3 PCI, 3V66 Falling Edge Rate Between 2.4V and 0.4V 1.0 4.0 V/ns t6 CPU CPU-CPU Skew Measured at 1.25V 175 ps t8 IOAPIC IOAPIC-IOAPIC Skew Measured at 1.25V 250 ps t9 3V66 3V66-3V66 Skew Measured at 1.5V 250 ps t10 PCI PCI-PCI Skew Measured at 1.5V 500 ps t11 CPU, 3V66 CPU-3V66 Clock Skew CPU leads. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks 0 1.5 ns t12 3V66, PCI 3V66-PCI Clock Skew 3V66 leads. Measured at 1.5V 0.5 2.5 ns t13 CPU, IOAPIC CPU-IOAPIC Clock Skew CPU leads. Measured at 1.25V 1.5 4 ns CPU Cycle-Cycle Clock Jitter With all outputs running 150 ps IOAPIC Cycle-Cycle Clock Jitter 500 ps 48MHZ Cycle-Cycle Clock Jitter 500 ps 3V66 Cycle-Cycle Clock Jitter 500 ps REF Cycle-Cycle Clock Jitter CPU, PCI Settle Time Test Conditions CPU and PCI clock stabilization from power-up 1000 ps 3 ms Notes: 4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. All parameters specified with loaded outputs. 6. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. Document #: 38-07039 Rev. *B Page 5 of 10 CY28158 Switching Waveforms Duty Cycle Timing t1A t1B All Outputs Rise/Fall Time VDD OUTPUT t2 t3 0V CPU-CPU Clock Skew CPUCLK CPUCLK t6 IOAPIC-IOAPIC Clock Skew IOAPIC IOAPIC t8 3V66 - 3V66 Clock Skew 3V66 3V66 t9 Document #: 38-07039 Rev. *B Page 6 of 10 CY28158 Switching Waveforms (continued) PCI-PCI Clock Skew PCI PCI t10 CPU - 3V66 Clock Skew CPU 3V66 t11 3V66 - PCI Clock Skew 3V66 PCI t12 CPU-IOAPIC Clock Skew CPU t13 IOAPIC [7, 8] CPU_STOP# Timing CPU (Internal) PCI (Internal) PCI_F (Free-Running) CPU_STOP# CPU, 3V66 (External) Notes: 7. CPU on and CPU off latency is 2 or 3 CPU cycles. 8. CPU_STOP# may be applied asynchronously. It is synchronized internally. Document #: 38-07039 Rev. *B Page 7 of 10 CY28158 Switching Waveforms (continued) PCI_STOP# CPU (Internal) PCI (Internal) PCI_F (Free-Running) PCI_STOP# PCI (External) PWR_DWN# CPU (Internal) PCI (Internal) PWR_DWN# CPU (External) PCI (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. Test Circuit VDD_PCI, VDD_3V66, VDD_48MHZ, VDD_REF, VDDA 1, 7, 8, 13, 19, 20, 21, 24, 29, 40, 44, 48, 52 4, 10, 16, 17, 22, 23, 27, 31, 39 CY28158 VDD_CPU, VDD_IOAPIC OUTPUTS CLOAD 43, 47, 51, 56 Note: Each supply pin must have an individual decoupling capacitor on test circuit at 0.1 µF. Note: All capacitors must be placed as close to the pins as is physically possible. Ordering Information Ordering Code Package Name Package Type Operating Range CY28158PVC O56 56-Pin SSOP Commercial CY28158PVCT O56 56-Pin SSOP- Tape and Reel Commercial CY28158OXC O56 56-Pin SSOP Commercial CY28158OXCT O56 56-Pin SSOP- Tape and Reel Commercial Lead Free Document #: 38-07039 Rev. *B Page 8 of 10 CY28158 Package Diagram 56-Lead Shrunk Small Outline Package O56 51-85062-C Document #: 38-07039 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28158 Document Title: CY28158 Spread Spectrum Timing Solution for Serverworks Chipset Document Number: 38-07039 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107005 08/08/01 IKA New Data Sheet *A 122732 12/16/02 RBI Added power-up requirements to operating conditions information. *B 237871 See ECN RGL Added Lead Free Devices Document #: 38-07039 Rev. *B Page 10 of 10