UC2856-Q1 www.ti.com ...................................................................................................................................................................................................... SLVS863 – JUNE 2008 IMPROVED CURRENT-MODE PWM CONTROLLER FEATURES 1 • • • • • • • • • • Qualified for Automotive Applications Pin-for-Pin Compatible With the UC2846 65-ns Typical Delay From Shutdown to Outputs and 50-ns Typical Delay From Sync to Outputs Improved Current Sense Amplifier With Reduced Noise Sensitivity Differential Current Sense With 3-V Common-Mode Range Trimmed Oscillator Discharge Current for Accurate Deadband Control Accurate 1-V Shutdown Threshold High Current Dual Totem Pole Outputs (1.5-A Peak) TTL Compatible Oscillator SYNC Pin Thresholds ESD Protection – 4-kV Human-Body Model (HBM) – 500-V Charged-Device Model (CDM) DW PACKAGE (TOP VIEW) CL SS VREF CS− CS+ EA+ EA− COMP CT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SHUTDOWN VIN BOUT VC GND AOUT SYNC RT P0008-01 DESCRIPTION The UC2856 is a high performance version of the popular UC2846 series of current mode controllers, and is intended for both design upgrades and new applications where speed and accuracy are important. All input to output delays have been minimized, and the current sense output is slew rate limited to reduce noise sensitivity. Fast 1.5-A peak output stages have been added to allow rapid switching of power FETs. A low impedance TTL compatible sync output has been implemented with a 3-state function when used as a sync input. Internal chip grounding has been improved to minimize internal noise caused when driving large capacitive loads. This, in conjunction with the improved differential current-sense amplifier, results in enhanced noise immunity. Other features include a trimmed oscillator current (8%) for accurate frequency and dead-time control, a 1-V 5% shutdown threshold, and 4-kV minimum ESD protection (HBM) on all pins. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) SOP – DW Reel of 2000 ORDERABLE PART NUMBER UC2856QDWRQ1 TOP-SIDE MARKING UC2856Q1 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated UC2856-Q1 SLVS863 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com BLOCK DIAGRAM 5.1 V Reference Regulator VIN 15 2 VREF SYNC 10 RT UV Lockout 9 13 VC OSC CT 8 FF 11 AOUT Q T 4.1 V CS− 3 − X3 CS+ Q + COMP + 4 R S − Q − S 0.5 V 14 BOUT + 0.5 mA EA+ 5 − EA− 6 + 12 GND EA 1 COMP 7 CL SS 16 SHUTDOWN + 6 kΩ − 1V B0010-01 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 UC2856-Q1 www.ti.com ...................................................................................................................................................................................................... SLVS863 – JUNE 2008 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) Supply voltage 40 V Collector supply voltage IO 40 V DC Output current (sink or source) 0.5 A Pulse (0.5 ms) 2A Error amplifier input voltage –0.3 V to VIN Shutdown input voltage –0.3 V to 10 V Current sense input voltage –0.3 V to 3 V SYNC output current 10 mA Error amplifier output current –5 mA Soft start sink current 50 mA Oscillator charging current 5 mA Power dissipation TA = 25°C 1W TC = 25°C 2W TJ Operating junction temperature range –55°C to 150°C Tstg Storage temperature range –65°C to 150°C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds ESD (1) (2) Electrostatic discharge protection 300°C Human-Body Model (HBM) 4000 V Charged-Device Model (CDM) 500 V Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Unless otherwise indicated, voltages are reference to ground and currents are positive into and negative out of the specified terminals. ELECTRICAL CHARACTERISTICS TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.05 5.1 5.15 V Reference Section Output voltage IO = 1 mA, TJ = 25°C Line regulation voltage VIN = 8 V to 40 V 20 mV Load regulation voltage IO = –1 mA to –10 mA 15 mV Total output variation Over line, load, and temperature 5.2 V Output noise voltage f = 10 Hz to 10 kHz, Long term stability 1000 hours, Short circuit current VREF = 0 V 5 TJ = 25°C 50 TJ = 25°C 5 25 mV –25 –45 –65 mA TJ = 25°C 180 200 220 TJ = Full range 170 (2) V Oscillator Section Initial accuracy Voltage stability 230 VIN = 8 V to 40 V 7.5 8 8.8 VCT = 2 V 6.7 8 8.8 Sync output high level voltage IO = –1 mA 2.4 3.6 Sync output low level voltage IO = 1 mA Sync input high level voltage CT = 0 V, RT = VREF Sync input low level voltage CT = 0 V, RT = VREF Sync input current CT = 0 V, RT = VREF, VSYNC = 5 V Sync delay to outputs CT = 0 V RT = VREF, VSYNC = 0.8 V to 2 V Discharge current (1) (2) VCT = 2 V, 2 TJ = 25°C 0.2 2 % mA V 0.4 1.5 1.5 kHz V V 0.8 V 1 10 A 50 100 ns All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. This parameter, although specified over the recommended operating conditions, is not 100% tested in production. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 3 UC2856-Q1 SLVS863 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Error Amplifier Section Input offset voltage VCM = 2 V Input bias current Input offset current 5 mV –1 A 500 nA Common mode range VIN = 8 V to 40 V 0 Open loop gain VO = 1.2 V to 3 V 80 Unity gain bandwidth TJ = 25°C CMRR VCM = 0 V to 38 V, PSRR VIN = 8 V to 40 V Output sink current VID = –15 mV VCOMP = 1.2 V Output source current VID = 15 mV VCOMP = 2.5 V High-level output voltage VID = 50 mV, RL (COMP) = 15 kΩ 4.3 4.6 4.9 V Low-level output voltage VID = –50 mV, RL (COMP) = 15 kΩ 0.7 1 V Amplifier gain VCS– = 0 V, CL SS Open (3) 2.5 2.75 3 V/V Maximum differential input signal (VCS+ – VCS–) CL SS Open 3, RL (COMP) = 15 kΩ 1.1 1.2 Input offset voltage VCL COMP open (3) CMRR VCM = 0 V to 3 V PSRR VIN = 8 V to 40 V Input bias current VCL SS = 0.5 V, COMP open (3) –1 A Input offset current VCL SS = 0.5 V, COMP open (3) 1 mA 3 V 120 250 ns 0.5 0.6 V –10 –30 A 1.00 1.05 V VIN = 40 V VIN–2 V 100 dB 1 1.5 MHz 75 100 dB 80 100 dB 5 10 mA –0.4 –0.5 mA Current Sense Amplifier Section SS = 0.5 V (4) 5 35 60 dB 0 VEA+ = VREF, EA– = 0 V, CS+ – CS– = 0 V to 1.5 V mV dB 60 Input common mode range Delay to outputs V Current Limit Adjust Section Current limit offset VCS– = 0 V, VCS+ = 0 V, COMP open (3) Input bias current VEA+ = VREF, VEA– = 0 V 0.4 SHUTDOWN Terminal Section Threshold voltage 0.95 Input voltage range 0 3 (3) (4) (5) (6) 4 1.5 (6) Maximum non-latching current (ICL SS) Delay to outputs 5 (5) Minimum latching current (ICL SS) VSHUTDOWN = 0 V to 1.3 V V mA 1.5 0.8 mA 65 110 ns Parameter measured at trip point of latch with VEA+ = VREF, VEA– = 0 V. DV COMP ; DV G+ CS * + 0 V 1 V. DV CS) Amplifier gain defined as: Current into CL SS assured to latch circuit into shutdown state. Current into CL SS assured not to latch circuit into shutdown state. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 UC2856-Q1 www.ti.com ...................................................................................................................................................................................................... SLVS863 – JUNE 2008 ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output Section Collector-emitter voltage Off-state bias current Output low level voltage Output high level voltage 40 V VC = 40 V 250 IOUT = 20 mA 0.1 0.5 IOUT = 200 mA 0.5 2.6 IOUT = –20 mA IOUT = –200 mA 12.5 13.2 12 13.1 A V V Rise time C1 = 1 nF 40 80 ns Fall time C1 = 1 nF 40 80 ns UVLO low saturation VIN = 0 V, 0.8 1.5 V 47 50 % 0 % 8 V IOUT = 20 mA PWM Section Maximum duty cycle 45 Minimum duty cycle Undervoltage Lockout Section Startup threshold 7.7 Threshold hysteresis 0.7 V Total Standby Current Supply current 18 23 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 mA 5 UC2856-Q1 SLVS863 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com APPLICATION AND OPERATION INFORMATION VREF SAWTOOTH CT 9 COMP OSC SYNC 8 CT RT Output Deadtime (td) 8 mA 10 SYNC 2C NOTE: Output deadtime is determined by the size of the external capacitor, CT, according to the formula: For large values of RT: Td + 250 C T 2 ƒT + Oscillator frequency is approximated by the formula: RT CT Td + T 8 mA * R3.6 T S0019-01 Figure 1. Oscillator Circuit 90 VREF VIN = 20 V TJ = 25° 5 + 0.5 mA Zs − 6 Open-Loop Voltage Gain − dB 80 70 60 50 40 30 20 10 7 0 0 COMP Zf lf < 0.5 mA S0020-01 −10 −90 −20 100 1k 10k 100k 1M −180 10M Open-Loop Phase − ° VREF f − Frequency − Hz G001 NOTE: Error Amplifier can source up to 0.5 mA. Figure 2. Error Amplifier Output Configuration 6 Figure 3. Error Amplifier Gain and Phase vs Frequency Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 UC2856-Q1 www.ti.com ...................................................................................................................................................................................................... SLVS863 – JUNE 2008 110 VIN = 20 V TJ = 25° Open-Loop Voltage Gain − dB 105 100 95 90 85 RL 80 75 70 0 10 20 30 40 50 60 70 80 90 100 110 RL − Output Load Resistance − kΩ G002 Figure 4. Error Amplifier Open-Loop DC Gain vs Load Resistance 9 RT Master 8 RT CT CT VREF EA+ SYNC COMP EA− 2 5 10 7 6 VOUT 9 2 5 10 7 6 VREF EA+ SYNC COMP EA− Output Filters RT Slave (Additional Units) 8 CT S0021-01 NOTE: Slaving allows parallel operation of two or more units with equal current sharing. Figure 5. Parallel Operation Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 7 UC2856-Q1 SLVS863 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com IS (+) 4 RS ISENSE (−) X3 COMP 3 − 0.5 V VREF + 0.5 mA R1 EA 1 Current Limit R2 7 COMP S0022-01 ǒ R2 I + S NOTE: Peak current (IS) is determined by the formula: V Ǔ REF * 0.5 R1)R2 3RS Figure 6. Pulse by Pulse Current Limiting 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 UC2856-Q1 www.ti.com ...................................................................................................................................................................................................... SLVS863 – JUNE 2008 VREF ISENSE + R1 1 − 0.5 V Current Limit COMP S S ISS C R2 EA VREF 16 SHUTDOWN − − + + 1.0 V SHUTDOWN With Auto-Restart SHUTDOWN Without Auto-Restart (Latched) Current Limit 0.5 V 0 Shutdown On Off PWM S0023-01 NOTE: If VREF / R1 < 0.8 mA, the shutdown latch commutates when ISS = 0.8 mA, and a restart cycle is initiated. If VREF / R1 > 3 mA, the device latches off until power is cycled. Figure 7. Shutdown Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): UC2856-Q1 9 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing UC2856QDWRQ1 ACTIVE SOIC DW Pins Package Eco Plan (2) Qty 16 2000 Green (RoHS & no Sb/Br) Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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