PSMN003-30P N-channel TrenchMOS intermediate level FET Rev. 02 — 25 February 2010 Product data sheet 1. Product profile 1.1 General description SiliconMAX intermediate level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for high frequency applications due to fast switching characteristics 1.3 Applications High frequency computer motherboard DC-to-DC convertors OR-ing applications 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 and 3 - - 75 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 230 W VGS = 10 V; ID = 75 A; VDS = 15 V; Tj = 25 °C; see Figure 11 - 45 - nC VGS = 5 V; ID = 25 A; Tj = 25 °C; see Figure 9 and 10 - 3.3 4 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 9 and 10 - 2.4 2.8 mΩ Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate 2 D drain Simplified outline Graphic symbol D mb 3 S source mb D mounting base; connected to drain G mbb076 S 1 2 3 SOT78 (TO-220AB) 3. Ordering information Table 3. Ordering information Type number PSMN003-30P PSMN003-30P_2 Product data sheet Package Name Description Version TO-220AB plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead SOT78 TO-220AB All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 2 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 - 75 A VGS = 10 V; Tmb = 25 °C; see Figure 1 and 3 - 75 A - 400 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 230 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C VGSM peak gate-source voltage pulsed; tp ≤ 50 µs; δ = 25 %; Tj ≤ 150 °C -25 25 V Source-drain diode IS source current Tmb = 25 °C - 75 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 400 A Avalanche ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 75 A; Vsup = 15 V; drain-source avalanche unclamped; tp = 0.1 ms; RGS = 50 Ω energy - 500 mJ IAS non-repetitive avalanche current - 75 A Vsup = 15 V; VGS = 10 V; Tj(init) = 25 °C; RGS = 50 Ω; unclamped 03af36 120 Ider (%) 100 03aa16 120 Pder (%) 80 80 60 40 40 20 0 0 Fig 1. 0 30 60 90 120 Normalized continuous drain current as a function of mounting base temperature PSMN003-30P_2 Product data sheet 0 150 180 Tmb (°C) 50 100 150 200 Tmb (°C) Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 3 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 03af49 103 RDSon = VDS/ID tp = 10 μs ID (A) 100 µs 102 1 ms δ= P 10 tp 10 ms 100 ms DC T t tp T 1 1 102 10 VDS (V) Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN003-30P_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 4 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - - 0.65 K/W Rth(j-a) thermal resistance from junction to ambient vertical in still air - 60 - K/W 03af48 1 Zth(j-mb) (K/W) δ = 0.5 0.2 10−1 0.1 0.05 0.02 10−2 δ= P tp T single pulse t tp 10−3 10−6 T 10−5 10−4 10−3 10−2 10−1 1 10 tp (s) Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN003-30P_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 5 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 27 - - V ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 30 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 8 1 2 3 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 8 0.4 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 8 - - 3.4 V VDS = 30 V; VGS = 0 V; Tj = 175 °C - - 500 µA VDS = 30 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 25 A; Tj = 175 °C; see Figure 9 and 10 - 4.32 5 mΩ VGS = 5 V; ID = 25 A; Tj = 25 °C; see Figure 9 and 10 - 3.3 4 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 9 and 10 - 2.4 2.8 mΩ ID = 75 A; VDS = 15 V; VGS = 10 V; Tj = 25 °C; see Figure 11 - 170 - nC - 44 - nC - 45 - nC - 9200 - pF - 1930 - pF - 1300 - pF - 33 - ns - 66 - ns IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time - 210 - ns tf fall time - 115 - ns - 0.85 1.2 V VDS = 25 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 12 VDS = 15 V; RL = 1.25 Ω; VGS = 10 V; RG(ext) = 6 Ω; Tj = 25 °C Source-drain diode VSD source-drain voltage PSMN003-30P_2 Product data sheet IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 13 All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 6 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET ID (A) 03af50 400 VGS = 10 V 7 V 5.2 V 350 15 V ID Tj = 25 °C 5V 03af52 100 VDS > I D x R DSon (A) 4.8 V 80 20 V 300 4.6 V 250 175 °C 60 4.4 V Tj = 25 °C 200 4.2 V 40 150 4V 100 3.8 V 20 3.6 V 50 3.4 V 0 0 Fig 5. 0 0.5 1 1.5 2 VDS (V) 0 2.5 Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. 03af66 1 ID (A) 10-1 1 2 3 4 5 6 VGS (V) Transfer characteristics: drain current as a function of gate-source voltage; typical values 03af65 4 VGS(th) (V) 3 10-2 max typ min 10-3 max 2 typ 10-4 1 min -5 10 10-6 0 Fig 7. 1 2 3 VGS (V) Sub-threshold drain current as a function of gate-source voltage PSMN003-30P_2 Product data sheet 0 -60 4 20 100 180 Tj (°C) Fig 8. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 7 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 03af51 0.006 RDSon (Ω) 0.005 03af18 2 3.8 V 4 V 4.2 V 4.4 V 4.6 V 4.8 V a 1.5 5V 0.004 5.2 V 1 0.003 6V 10 V 0.002 15 V VGS = 20 V 0.5 0.001 Tj = 25 °C 0 Fig 9. 0 100 200 300 400 ID (A) Drain-source on-state resistance as a function of drain current; typical values 03af56 12 VGS ID = 75 A (V) 0 -60 500 0 60 120 Tj (°C) 180 Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature 03af55 105 C (pF) 10 VDD = 15 V 104 8 Ciss Tj = 25 °C 6 Coss 103 4 Crss 2 0 0 50 100 150 Q G (nC) 200 Fig 11. Gate-source voltage as a function of gate charge; typical values PSMN003-30P_2 Product data sheet 102 10−1 1 10 VDS (V) 102 Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 8 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 03af54 100 IS (A) VGS = 0 V 80 175 °C 60 Tj = 25 °C 40 20 0 0.0 0.5 1.0 VSD (V) 1.5 Fig 13. Source current as a function of source-drain voltage; typical values PSMN003-30P_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 9 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 7. Package outline Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB SOT78 E A A1 p q mounting base D1 D L1(1) L2(1) Q L b1(2) (3×) b2(2) (2×) 1 2 3 b(3×) c e e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1(2) b2(2) c D D1 E e L L1(1) L2(1) max. p q Q mm 4.7 4.1 1.40 1.25 0.9 0.6 1.6 1.0 1.3 1.0 0.7 0.4 16.0 15.2 6.6 5.9 10.3 9.7 2.54 15.0 12.8 3.30 2.79 3.0 3.8 3.5 3.0 2.7 2.6 2.2 Notes 1. Lead shoulder designs may vary. 2. Dimension includes excess dambar. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC JEITA 3-lead TO-220AB SC-46 EUROPEAN PROJECTION ISSUE DATE 08-04-23 08-06-13 Fig 14. Package outline SOT78 (TO-220AB) PSMN003-30P_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 10 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN003-30P_2 20100225 Product data sheet - PSMN003-30P_1 Modifications: PSMN003-30P_1 PSMN003-30P_2 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 20011023 Product data - All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 - © NXP B.V. 2010. All rights reserved. 11 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PSMN003-30P_2 Product data sheet Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 12 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products — Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PSMN003-30P_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 25 February 2010 © NXP B.V. 2010. All rights reserved. 13 of 14 PSMN003-30P NXP Semiconductors N-channel TrenchMOS intermediate level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 February 2010 Document identifier: PSMN003-30P_2