INTERSIL QLX4600LIQT7

QLx4600-SL30
Features
The QLx4600-SL30 is a settable quad receive-side
equalizer with extended functionality for advanced
protocols operating with line rates up to 6.25Gb/s such
as InfiniBand (SDR and DDR) and 10GBase-CX4. The
QLx4600-SL30 compensates for the frequency
dependent attenuation of copper twin-axial cables,
extending the signal reach up to 30m on 24AWG cable.
The small form factor, highly-integrated quad design is
ideal for high-density data transmission applications
including active copper cable assemblies. The four
equalizing filters within the QLx4600-SL30 can each be
set to one of 32 compensation levels, providing optimal
signal fidelity for a given media and length. The
compensation level for each filter can be set by either (a)
three external control pins or (b) a serial bus interface.
When the external control pins are used, 18 of the 32
boost levels are available for each channel. If the serial
bus is used, all 32 compensation levels are available.
Operating on a single 1.2V power supply, the
QLx4600-SL30 enables per channel throughputs of up to
6.25Gb/s while supporting lower data rates including 5,
4.25, 3.125, and 2.5Gb/s. The QLx4600-SL30 uses
current mode logic (CML) inputs/outputs and is packaged
in a 4mmx7mm 46 lead QFN. Individual lane LOS
support is included for module applications.
• Supports data rates up to 6.25Gb/s
• Low power (78mW per channel)
• Low latency (<500ps)
• Four equalizers in a 4mmx7mm QFN package for
straight route-through architecture and simplified
routing
• Each equalizer boost is independently pin selectable
and programmable
• Beacon signal support and line silence preservation
• 1.2V supply voltage
• Individual lane LOS support
Applications
• QSFP active copper cable modules
• InfiniBand (SDR and DDR)
• 10GBase-CX4
• XAUI and RXAUI
• SAS (2.0)
• High-speed active cable assemblies
• High-speed printed circuit board (PCB) traces
Benefits
• Thinner gauge cable
• Extends cable reach greater than 3x
• Improved BER
Typical Application Circuit
November 19, 2009
FN6981.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
QLx4600-SL30
Quad Lane Extender
QLx4600-SL30
Ordering Information
PART NUMBER
(Note)
TEMP. RANGE
(°C)
PART MARKING
PACKAGE
(Pb-Free)
PKG. DWG. #
QLX4600LIQT7
QLX4600LIQ
0 to +70
46 Ld QFN
7” Prod. Tape & Reel; Qty 1,000
L46.4x7
QLX4600LIQSR
QLX4600LIQ
0 to +70
46 Ld QFN
7” Sample Reel; Qty 100
L46.4x7
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
Pin Configuration
CP2[B]
CP2[C]
CP1[C]
CP2[A]
CP1[B]
CP1[A]
ENB
CLK
QLx4600-SL30
(46 LD 4x7 QFN)
TOP VIEW
46 45 44 43 42 41 40 39
DT
1
38 BGREF
IN1[P]
2
37 OUT1[P]
IN1[N]
3
36 OUT1[N]
VDD
4
35 VDD
IN2[P]
5
34 OUT2[P]
IN2[N] 6
33 OUT2[N]
VDD 7
32 VDD
EXPOSED PAD
(GND)
IN3[P] 8
31 OUT3[P]
IN3[N] 9
30 OUT3[N]
VDD 10
29 VDD
IN4[P] 11
28 OUT4[P]
IN4[N] 12
27 OUT4[N]
LOS1 13
26 LOS3
LOS2 14
25 LOS4
GND 15
24 MODE
2
CP4[C]
CP4[B]
CP4[A]
CP3[C]
CP3[B]
CP3[A]
DO
DI
16 17 18 19 20 21 22 23
FN6981.1
November 19, 2009
QLx4600-SL30
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
DT
1
IN1[P,N]
2, 3
Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
VDD
4, 7, 10, 29,
32, 35
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to
ground is recommended for each of these pins for broad high-frequency noise suppression.
IN2[P,N]
5, 6
Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IN3[P,N]
8, 9
Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
IN4[P,N]
11, 12
Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
LOS1
13
LOS indicator 1. High output when equalized IN1 signal is below DT threshold.
LOS2
14
LOS indicator 2. High output when equalized IN2 signal is below DT threshold.
GND
15
Ground
DI
16
Serial data input, CMOS logic. Input for serial data stream to program internal registers
controlling the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides
the boost setting established on CP control pins. Internally pulled down.
DO
17
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four
equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed
by 21 clock cycles.
CP3[A,B,C]
18, 19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
CP4[A,B,C]
21, 22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
MODE
24
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers
through pins DI, ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost
levels set by CP pins when set LOW. If serial programming is not used, this pin should be
grounded.
LOS4
25
LOS indicator 4. High output when equalized IN4 signal is below DT threshold.
LOS3
26
LOS indicator 3. High output when equalized IN3 signal is below DT threshold.
OUT4[N,P]
27, 28
Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT3[N,P]
30, 31
Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT2[N,P]
33, 34
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
OUT1[N,P]
36, 37
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
BGREF
38
Detection Threshold. Reference DC current threshold for input signal power detection. Data
output OUT[k] is muted when the power of the equalized version of IN[k] falls below the
threshold. Tie to ground to disable electrical idle preservation and always enable the limiting
amplifier.
External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.
3
FN6981.1
November 19, 2009
QLx4600-SL30
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
ENB
45
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and
CLK pins only when the ENB pin is ‘LOW’. Internally pulled down.
CLK
46
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI
is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and
20MHz. Internally pulled down.
EXPOSED
PAD
-
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
4
FN6981.1
November 19, 2009
QLx4600-SL30
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V
Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V
ESD Rating at All Pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM)
Thermal Resistance (Typical)
θJA (°C/W) θJc (°C/W)
46 Ld QFN Package (Note 1). . . . .
32
2.3
Operating Ambient Temperature Range. . . . . . 0°C to +70°C
Storage Ambient Temperature Range . . . . . -55°C to +150°C
Maximum Junction Temperature. . . . . . . . . . . . . . . +125°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
Operating Conditions
PARAMETER
SYMBOL
Supply Voltage
MIN
TYP
MAX
UNITS
VDD
1.1
1.2
1.3
V
TA
0
25
70
°C
6.25
Gb/s
Operating Ambient Temperature
Bit Rate
CONDITION
NRZ data applied to any channel
1.5
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
0
350
mV
VDD
mV
250
mV
NOTES
Input ‘LOW’ Logic Level
VIL
DI, Clk, ENB
0
Input ‘HIGH’ Logic Level
VIH
DI, Clk, ENB
750
Output ‘LOW’ Logic Level
VOL
LOS[k], DO
0
Output ‘HIGH’ Logic Level
VOH
LOS[k], DO
1000
VDD
mV
0
1
kΩ
2
27.5
kΩ
2
∞
kΩ
2
100
µA
‘LOW’ Resistance State
CP[k][A,B,C]
‘MID’ Resistance State
CP[k][B,C]
22.5
‘HIGH’ Resistance State
CP[k][A,B,C]
500
Input Current
Current draw on digital pin, i.e.,
CP[k][A,B,C], DI, Clk, ENB
0
25
30
NOTE:
2. If four CP pins are tied together, the resistance values in this table should be divided by four.
Electrical Specifications
PARAMETERS
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C.
SYMBOL
Supply Current
IDD
Cable Input Amplitude
Range
VIN
CONDITION
MIN
TYP
MAX
260
Measured differentially at data source
before encountering channel loss
UNITS NOTES
mA
800
1200
1600
mVP-P
DC Differential Input
Resistance
Measured on input channel IN[k]
80
100
120
Ω
DC Single-Ended Input
Resistance
Measured on input channel IN[k]P or
IN[k]N
40
50
60
Ω
50MHz to 3.75GHz
10
Input Return Loss
(Differential)
SDD11
5
dB
3
4
FN6981.1
November 19, 2009
QLx4600-SL30
Electrical Specifications
PARAMETERS
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C. (Continued)
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS NOTES
Input Return Loss
(Common Mode)
SCC11
50MHz to 3.75GHz
6
dB
4
Input Return Loss
(Com. to Diff. Conversion)
SDC11
50MHz to 3.75GHz
20
dB
4
Output Amplitude Range
VOUT
Active data transmission mode; Measured
differentially at OUT[k]P and OUT[k]N with
50Ω load on both output pins
450
Line Silence mode; Measured differentially
at OUT[k]P and OUT[k]N with 50Ω load on
both output pins
Differential Output
Impedance
Measured on OUT[k]
80
550
650
mVP-P
10
20
mVP-P
105
120
Ω
Output Return Loss
(Differential)
SDD22
50MHz to 3.75GHz
10
dB
4
Output Return Loss
(Common Mode)
SCC22
50MHz to 3.75GHz
5
dB
4
Output Return Loss (Com.
to Diff. Conversion)
SDC22
50MHz to 3.75GHz
20
dB
4
Output Residual Jitter
tr, tf
Output Transition Time
2.5Gb/s, 3.125Gb/s, 4.25Gb/s, 5Gb/s; Up
to 20m 24AWG standard twin-axial cable
(approx. -25dB @ 2.5GHz); 800mVP-P ≤
VIN ≤ 1600mVP-P
0.15
0.25
UI
3, 5, 6
2.5Gb/s, 3.125Gb/s, 4.25Gb/s, 5Gb/s;
12m 30AWG standard twin-axial cable
(approx. -30dB @ 2.5GHz); 800mVP-P ≤
VIN ≤ 1600mVP-P
0.20
0.30
UI
3, 5, 6
2.5Gb/s, 3.125Gb/s, 4.25Gb/s, 5Gb/s;
20m 28AWG standard twin-axial cable
(approx. -35dB @ 2.5GHz); 1200mVP-P ≤
VIN ≤ 1600mVP-P
0.25
0.35
UI
3, 5, 6
6.25Gb/s, Up to 15m 28AWG standard
twin-axial cable (approx. -30dB @
3.2GHz); 1200mVP-P ≤ VIN ≤ 1600mVP-P
0.25
0.35
UI
3, 5, 6
60
80
ps
7
50
ps
20% to 80%
Lane-to-Lane Skew
30
Propagation Delay
From IN[k] to OUT[k]
500
ps
LOS Assert Time
Time to assert Loss-of-Signal (LOS)
indicator when transitioning from active
data mode to line silence mode
100
µs
8
LOS De-Assert Time
Time to assert Loss-of-Signal (LOS)
indicator when transitioning from line
silence mode to active data mode
100
µs
8
Time to transition from active data to line
silence (muted output) on 20m 24AWG
standard twin-axial cable at 5Gb/s
15
ns
8, 11
Time from last bit of ALIGN(0) for SAS OOB
signaling to line silence (<20mVP-P
output); Meritec 24AWG 20m; 3Gb/s
14
ns
12
Data-to-Line Silence
Response Time
tDS
6
FN6981.1
November 19, 2009
QLx4600-SL30
Electrical Specifications
PARAMETERS
SYMBOL
CONDITION
tSD
Time to transition from line silence mode
(muted output) to active data on 20m
24AWG standard twin-axial cable at 5Gb/s
20
ns
8, 11
Time from first bit of ALIGN(0) for SAS
OOB signaling to 450mVP-P output;
Meritec 24AWG 20m; 3Gb/s
19
ns
12
5
ns
12
Line Silence-to-Data
Response Time
Timing Difference (SAS)
Typical values are at VDD = 1.2V, TA = +25°C, and VIN = 800mVP-P, unless otherwise noted.
VDD = 1.1V to 1.3V, TA = 0°C to +70°C. (Continued)
MIN
TYP
|t DS - t SD| For SAS OOB signaling support; Meritec
24AWG 20m
MAX
UNITS NOTES
NOTES:
3. After channel loss, differential amplitudes at QLx4600-SL30 inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 5.
4. Temperature = +25°C, VDD = 1.2V.
5. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJPP + 14.1 x RJRMS.
6. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
7. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
8. For active data mode, cable input amplitude is 400mVP-P (differential) or greater. For line silence mode, cable input amplitude
is 20mVP-P (differential) or less.
9. Measured differentially across the data source.
10. During line silence, transmitter noise in excess of this voltage range may result in differential output amplitudes from the
QLx4600 that are greater than 20mVP-P.
11. The data pattern preceding line silence mode is comprised of the PCIe electrical idle ordered set (EIOS). The data pattern
following line silence mode is comprised of the PCIe electrical idle exit sequence (EIES).
12. The data pattern preceding or following line silence mode is comprised of the SAS-2 ALIGN (0) sequence for OOB signaling at
3Gb/s, and amplitude of 800mVP-P.
Serial Bus Timing Characteristics
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
CLK Setup Time
tSCK
From the falling edge of ENB
10
ns
DI Setup Time
tSDI
Prior to the rising edge of CLK
10
ns
DI Hold Time
tHDI
From the rising edge of CLK
6
ns
ENB ‘HIGH’
tHEN
From the falling edge of the last data bit’s CLK
10
ns
Boost Setting Operational
tD
From ENB ‘HIGH’
DO Hold Time
tCQ
From the rising edge of CLK to DO transition
Clock Rate
fCLK
Reference clock for serial bus EQ programming
7
10
12
ns
ns
20
MHz
FN6981.1
November 19, 2009
QLx4600-SL30
Typical Performance Characteristics
VDD = 1.2V, TA = +25°C, unless otherwise noted. Performance was characterized using the system testbed shown in
Figure 1. Unless otherwise noted, the transmitter generated a non-return-to-zero (NRZ) PRBS-7 sequence at 800mVP-P
(differential) with 10ps of peak-to-peak deterministic jitter. This transmit signal was launched into twin-axial cable test
channels of varying gauges and lengths. The loss characteristics of these test channels are plotted as a function of
frequency in Figure 2. The received signal at the output of these test channels was then processed by the QLx4600-SL30
before being passed to a receiver. Eye diagram measurements were made with 4000 waveform acquisitions and include
random jitter.
Pattern
Generator
SMA
Adapter
Card
SMA
Adapter
Card
Ω Twin-Axial
100O
Cable
QLx4600-SL30
Eval Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION TEST SETUP
TEST CHANNEL LOSS CHARACTERISTICS
FIGURE 2. TWIN-AXIAL CABLE LOSS AS A FUNCTION OF FREQUENCY FOR VARIOUS TEST CHANNELS
0.5
Jitter (UI)
0.4
0.3
0.2
Cable A (24AWG 20m)
0.1
Cable B (30AWG 12m)
Cable C (28AWG 20m)
0
4
8
12
16
20
24
28
Boost Setting
FIGURE 3A. JITTER vs CABLE LENGTH, 5Gb/s
FIGURE 3B. JITTER vs BOOST SETTING, 5Gb/s
FIGURE 3. JITTER VS CABLE LENGTH AND JITTER VS BOOST SETTING AT 5 GBPS
8
FN6981.1
November 19, 2009
QLx4600-SL30
60mV/div
80mV/div
Typical Performance Characteristics (Continued)
40ps/div
40ps/div
FIGURE 5. QLx4600-SL30 OUTPUT AFTER 20m OF 24AWG
TWIN-AXIAL CABLE (CABLE A), 5Gb/s
60mV/div
80mV/div
FIGURE 4. RECEIVED SIGNAL AFTER 20m OF 24AWG
TWIN-AXIAL CABLE (CABLE A), 5Gb/s
40ps/div
40ps/div
FIGURE 7. QLx4600-SL30 OUTPUT AFTER 12m OF 30AWG
TWIN-AXIAL CABLE (CABLE B), 5Gb/s
70mV/div
80mV/div
FIGURE 6. RECEIVED SIGNAL AFTER 12m OF 30AWG
TWIN-AXIAL CABLE (CABLE B), 5Gb/s
40ps/div
FIGURE 8. RECEIVED SIGNAL AFTER 20m OF 28AWG
TWIN-AXIAL CABLE (CABLE C) (NOTE 13),
5Gb/s
9
40ps/div
FIGURE 9. QLx4600-S30 OUTPUT AFTER 20m OF 28AWG
TWIN-AXIAL CABLE (CABLE C) (NOTE 13),
5Gb/s
FN6981.1
November 19, 2009
QLx4600-SL30
70mV/div
80mV/div
Typical Performance Characteristics (Continued)
40ps/div
40ps/div
FIGURE 11. QLx4600-SL30 OUTPUT AFTER 30m OF
24AWG TWIN-AXIAL CABLE (NOTE 13), 5Gb/s
80mV/div
70mV/div
FIGURE 10. RECEIVED SIGNAL AFTER 30m OF 24AWG
TWIN-AXIAL CABLE (NOTE 13), 5Gb/s
32ps/div
32ps/div
FIGURE 13. QLx4600-SL30 OUTPUT AFTER 15m OF
28AWG TWIN-AXIAL CABLE (CABLE D)
(NOTE 13), 6.25Gb/s
70mV/div
80mV/div
FIGURE 12. RECEIVED SIGNAL AFTER 15m OF 28AWG
TWIN-AXIAL CABLE (CABLE D) (NOTE 13),
6.25Gb/s
32ps/div
FIGURE 14. RECEIVED SIGNAL AFTER 40" FR4,
6.25Gb/s
10
32ps/div
FIGURE 15. QLx4600-SL30 OUTPUT AFTER 40" FR4,
6.25Gb/s
FN6981.1
November 19, 2009
QLx4600-SL30
Typical Performance Characteristics (Continued)
0
-5
Channel 1
Channel 2
Channel 3
-5
-10
Channel 4
-10
Channel 1
SCC22 (dB)
SCC11 (dB)
0
-15
-20
Channel 2
Channel 3
Channel 4
-15
-20
-25
-25
-30
-30
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.5
1
FIGURE 16. INPUT COMMON-MODE RETURN LOSS
2
2.5
3
3.5
4
FIGURE 17. OUTPUT COMMON-MODE RETURN LOSS
0
0
-5
-5
-10
-10
SDD22 (dB)
SDD11 (dB)
1.5
Frequency (GHz)
Frequency (GHz)
-15
-20
Channel 1
Channel 2
Channel 3
Channel 4
-25
-30
Channel 1
Channel 2
Channel 3
Channel 4
-15
-20
-25
-30
-35
-35
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
FIGURE 18. INPUT DIFFERENTIAL RETURN LOSS
FIGURE 20. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNELS
0
0.5
1
1.5
2
2.5
3
3.5
4
Frequency (GHz)
FIGURE 19. OUTPUT DIFFERENTIAL RETURN LOSS
FIGURE 21. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNELS
NOTE:
13. Differential transmit amplitude = 1200mVP-P.
11
FN6981.1
November 19, 2009
QLx4600-SL30
Limiting
Amplifier
IN[k] [P,N]
Adjustable
Equalizer
EQ Setting
(CP[k] / DI)
OUT[k] [P,N]
Signal
Detector
+
LOS[k]
Detection
Threshold
FIGURE 22. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx4600-SL30
Operation
The QLx4600-SL30 is an advanced quad lane-extender
for high-speed interconnects. A functional diagram of one
of the four channels in the QLx4600-SL30 is shown in
Figure 22. In addition to a robust equalization filter to
compensate for channel loss and restore signal fidelity,
the QLx4600-SL30 contains unique integrated features
to preserve special signaling protocols typically broken by
other equalizers. The signal detect function is used to
mute the channel output when the equalized signal falls
below the level determined by the Detection Threshold
(DT) pin voltage. This function is intended to preserve
periods of line silence (“quiescent state” in InfiniBand
contexts). Furthermore, the output of the signal
detect/DT comparator is used as a loss of signal (LOS)
indicator to indicate the absence of a received signal.
As illustrated in Figure 22, the core of each high-speed
signal path in the QLx4600-SL30 is a sophisticated
equalizer followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. Each
equalizer is followed by a limiting amplification stage that
provides a clean output signal with full amplitude swing
and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
Individually Adjustable Equalization Boost
Each channel in the QLx4600-SL30 features an
independently settable equalizer for custom signal
restoration. Each equalizer can be set to one of 32 levels
of compensation when the serial bus is used to program
the boost level and one of 18 compensation levels when
the CP[k] pins are used to set the level. The equalizer
transfer functions for a subset of these compensation
levels are plotted in Figure 23. The flexibility of this
adjustable compensation architecture enables signal
fidelity to be optimized on a channel-by-channel basis,
providing support for a wide variety of channel
characteristics and data rates ranging from 2.5Gb/s to
6.25Gb/s. Because the boost level is externally set rather
than internally adapted, the QLx4600-SL30 provides
reliable communication from the very first bit
transmitted. There is no time needed for adaptation and
control loop convergence. Furthermore, there are no
12
pathological data patterns that will cause the
QLx4600-SL30 to move to an incorrect boost level.
The Applications Information section beginning on
page 13 details how to set the boost level by both the
CP-pin voltage approach and the serial programming
approach.
FIGURE 23. EQUALIZER TRANSFER FUNCTIONS FOR
SETTINGS 0, 5, 10, 15, 20, 25, AND 31 IN
THE QLx4600-SL30
CML Input and Output Buffers
The input and output buffers for the high-speed data
channels in the QLx4600-SL30 are implemented using
CML. Equivalent input and output circuits are shown in
Figures 24 and 25, respectively.
FN6981.1
November 19, 2009
QLx4600-SL30
stages are muted and held at their nominal common
mode voltage1.
VDD
LOS Indicator
IN[k] P
50Ω
Buffer
50Ω
Applications Information
52Ω
OUT[k] P
OUT[k] N
CP1[B]
CP1[C]
CP2[A]
CP2[B]
CP2[C]
46
ENB
VDD
CP1[A]
FIGURE 24. CML INPUT EQUIVALENT CIRCUIT FOR THE
QLx4600-S30
Several aspects of the QLx4600-SL30 are capable of
being dynamically managed by a system controller to
provide maximum flexibility and optimum performance.
These functions are controlled by interfacing to the
highlighted pins in Figure 26. The specific procedures for
controlling these aspects of the QLx4600-SL30 are the
focus of this section.
CLK
IN[k] N
52Ω
Pins LOS[k] are used to output the state of the muting
circuitry to serve as a loss of signal indicator for channel
k. This signal is directly derived from the muting signal
off the DT-threshold signal detector output. The LOS
signal goes ‘HIGH’ when the power signal is below the DT
threshold and ‘LOW’ when the power goes above the DT
threshold. This feature is meant to be used in optical
systems (e.g. QSFP) where there are no quiescent or
electrical-idle states. In these cases, the DT threshold is
used to determine the sensitivity of the LOS indicator.
45
44
43
42
41
40
39
DT
1
38 BGREF
IN1[P]
2
37 OUT1[P]
IN1[N]
3
36 OUT1[N]
VDD
4
35 VDD
IN2[P]
5
IN2[N]
6
VDD
7
IN3[P]
8
IN3[N]
9
34 OUT2[P]
Quellan
QLx4600-SL30
33 OUT2[N]
32 VDD
46-Lead QFN
7mm x 4mm
0.4mm Pitch
31 OUT3[P]
30 OUT3[N]
Exposed Pad
(GND)
VDD 10
29 VDD
IN4[P] 11
28 OUT4[P]
IN4[N] 12
27 OUT4[N]
LOS1 13
26 LOS3
LOS2 14
25 LOS4
GND 15
NOTE: The load value of 52Ω is used to internally match
SDD22 for a characteristic impedance of 50Ω.
Line Silence/Electrical Idle/Quiescent Mode
Line silence is commonly broken by the limiting
amplification in other equalizers. This disruption can be
detrimental in many systems that rely on line silence as
part of the protocol. The QLx4600-SL30 contains special
lane management capabilities to detect and preserve
periods of line silence while still providing the fidelityenhancing benefits of limiting amplification during active
data transmission. Line silence is detected by measuring
the amplitude of the equalized signal and comparing that
to a threshold set by the current at the DT pin. When the
amplitude falls below the threshold, the output driver
21
22
23
CP4[B]
CP4[C]
CP3[A]
20
CP4[A]
DI
19
CP3[B]
18
CP3[C]
17
DO
FIGURE 25. CML OUTPUT EQUIVALENT CIRCUIT FOR
THE QLx4600-S30
24 MODE
16
FIGURE 26. PIN DIAGRAM HIGHLIGHTING PINS USED
FOR DYNAMIC CONTROL OF THE QLx4600SL30
Equalization Boost Level
Channel equalization for the QLx4600-SL30 can be
individually set to either (a) one of 18 levels through the
DC voltages on external control pins or (b) one of 32
levels via a set of registers programmed by a low speed
serial bus. The pins used to control the boost level are
highlighted in Figure 26. Descriptions of these pins are
listed in Table 1. Please refer to “Pin Descriptions” on
page 3 for descriptions of all other pins on the
QLx4600-SL30.
1. The output common mode voltage remains constant during both active data transmission and output muting modes.
13
FN6981.1
November 19, 2009
QLx4600-SL30
TABLE 1. DESCRIPTIONS OF PINS USED TO SET EQUALIZATION BOOST LEVEL
PIN NAME
PIN NUMBER DESCRIPTION
DI
16
Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling
the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost
setting established on CP control pins. Internally pulled down.
DO
17
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four
equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by
21 clock cycles.
CP3[A,B,C]
18, 19, 20
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP4[A,B,C]
21, 22, 23
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
MODE
24
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers
through pins DI, ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost
levels set by CP pins when set LOW. If serial programming is not used, this pin should be grounded.
CP2[C,B,A]
39, 40, 41
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
CP1[C,B,A]
42, 43, 44
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
ENB
45
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK
pins only when the ENB pin is ‘LOW’. Internally pulled down.
CLK
46
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is
latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz.
Internally pulled down.
The boost setting for equalizer channel k can be read as
a three digit ternary number across CP[k][A,B,C]. The
ternary value is established by the value of the resistor
between VDD and the CP[k][A,B,C] pin.
As a second option, the equalizer boost setting can be
taken from a set of registers programmed through a
serial bus interface (pins 16, 17, 45, and 46). Using this
interface, a set of registers is programmed to store the
boost level. A total of 21 registers are used. Registers 2
through 21 are parsed into four 5-bit words. Each 5-bit
word determines which of 32 boost levels to use for the
corresponding equalizer. Register 1 instructs the
QLx4600-SL30 to use registers 2 through 21 to set the
boost level rather than the control pins CP[k][A,B,C].
Both options have their relative advantages. The control
pin option minimizes the need for external controllers as
the boost level can be set in the board design resulting in
a compact layout. The register option is more flexible for
cases in which the optimum boost level will not be known
and can be changed by a host bus adapter with a small
number of pins. It is noted that the serial bus interface
can also be daisy-chained among multiple QLx4600-SL30
devices to afford a compact programmable solution even
when a large number of data lines need to be equalized.
Upon power-up, the default value of all the registers (and
register 1 in particular) is zero, and thus, the CP pins are
used to set the boost level. This permits an alternate
interpretation on setting the boost level. Specifically, the
14
CP pins define the default boost level until the registers
are (if ever) programmed via the serial bus.
TABLE 2. MAPPING BETWEEN CP-SETTING RESISTOR
AND PROGAMMED BOOST LEVELS
RESISTANCE BETWEEN CP PIN AND VDD
CP[A]
CP[B]
CP[C]
SERIAL
BOOST LEVEL
Open
Open
Open
0
Open
Open
25kΩ
2
Open
Open
0Ω
4
Open
25kΩ
Open
6
Open
25kΩ
25kΩ
8
Open
25kΩ
0Ω
10
Open
0Ω
Open
12
Open
0Ω
25kΩ
14
Open
0Ω
0Ω
15
0Ω
Open
Open
16
0Ω
Open
25kΩ
17
0Ω
Open
0Ω
19
0Ω
25kΩ
Open
21
0Ω
25kΩ
25kΩ
23
0Ω
25kΩ
0Ω
24
0Ω
0Ω
Open
26
0Ω
0Ω
25kΩ
28
0Ω
0Ω
0Ω
31
FN6981.1
November 19, 2009
QLx4600-SL30
Control Pin Boost Setting
When register 1 of the QLx4600-SL30 is zero (the default
state on power-up), the voltages at the CP pins are used
to determine the boost level of each channel. For each of
the four channels, k, the [A], [B], and [C] control pins
(CP[k]) are associated with a 3-bit non binary word.
While [A] can take one of two values, ‘LOW’ or ‘HIGH’,
[B] and [C] can take one of three different values: ‘LOW’,
‘MIDDLE’, or ‘HIGH’. This is achieved by changing the
value of a resistor connected between VDD and the CP
pin, which is internally pulled low with a 25kΩ resistor.
Thus, a ‘HIGH’ state is achieved by using a 0Ω resistor,
‘MIDDLE’ is achieved with a 25kΩ resistor, and ‘LOW’ is
achieved with an open resistance. Table 2 defines the
mapping from the 3-bit CP word to the 18 out of 32
possible levels available via the serial interface.
If all four channels are to use the same boost level, then
a minimum number of board resistors can be realized by
tying together like CP[k][A,B,C] pins across all channels
k. For instance, all four CP[k][A] pins can be tied to the
same resistor running to VDD. Consequently, only three
resistors are needed to control the boost of all four
channels. If the CP Pins are tied together and the 25kΩ is
used, the value changes to a 6.25kΩ resistor because the
25kΩ is divided by 4.
TABLE 3. OPTIMAL CABLE BOOST SETTINGS
CABLE
APPROX. LOSS @
2.5GHZ (DB)
QLx4600-SL30
BOOST
Cable A
22
10
Cable B
27
14
Cable C
35
19
NOTE: Optimal boost settings should be determined on an
application-by-application basis to account for variations in
channel type, loss characteristics, and encoding schemes. The
settings in this table are presented as guidelines to be used as
a starting point for application-specific optimization.
Register Description
The QLx4600-SL30’s internal registers are listed in
Table 4. Register 1 determines whether the CP pins or
register values 2 through 21 are used to set the boost
level. When this register is set, the QLx4600-SL30 uses
registers 2-6, 7-11, 12-16, and 17-21 to set the boost
level of equalizers 1, 2, 3, and 4. When register 1 is not
set, the CP pins are used to determine the boost level for
each equalizer channel. The use of five registers for each
equalizer channel allows all 32 boost levels as candidate
boost levels.
Optimal Cable Boost Settings
The settable equalizing filter within the QLx4600 enables
the device to optimally compensate for
frequency-dependent attenuation across a wide variety
of channels, data rates, and encoding schemes. For the
reference channels plotted in Figure 2, Table 3 shows the
optimal boost setting when transmitting a PRBS-7 signal.
The optimal boost setting is defined as the equalizing
filter setting that minimizes the output residual jitter of
the QLx4600. The settings in Table 3 represent the
optimal settings for the QLx4600C across an ambient
temperature range of 0°C to +70°C. The optimal setting
at room temperature (+20°C to +40°C) is generally one
to two settings lower than the values listed in Table 3.
15
FN6981.1
November 19, 2009
QLx4600-SL30
TABLE 4. DESCRIPTION OF INTERNAL SERIAL REGISTERS
REGISTER
EQUALIZER
CHANNEL
1
1-4
2
1
DESCRIPTION
CP control override – Use registers 2 through 21 (rather than CP pins) to establish the boost
levels when this bit is set.
Equalizer setting bit 0 (LSB).
3
Equalizer setting bit 1.
4
Equalizer setting bit 2.
5
Equalizer setting bit 3.
6
Equalizer setting bit 4 (MSB).
7
2
Equalizer setting bit 0 (LSB).
8
Equalizer setting bit 1.
9
Equalizer setting bit 2.
10
Equalizer setting bit 3.
11
Equalizer setting bit 4 (MSB).
12
3
Equalizer setting bit 0 (LSB).
13
Equalizer setting bit 1.
14
Equalizer setting bit 2.
15
Equalizer setting bit 3.
16
Equalizer setting bit 4 (MSB).
17
4
Equalizer setting bit 0 (LSB).
18
Equalizer setting bit 1.
19
Equalizer setting bit 2.
20
Equalizer setting bit 3.
21
Equalizer setting bit 4 (MSB).
Serial Bus Programming
Pins 16 (DI), 45 (ENB), and 46 (CLK) are used to
program the registers inside the QLx4600-SL30.
Figure 27 shows an exemplary timing diagram for the
signals on these pins. The serial bus can be used to
program a single QLx4600-SL30 according to the
following steps:
1. The ENB pin is pulled ‘LOW’.
- While this pin is ‘LOW’, the data input on DI are
read into registers but not yet latched.
- A setup time of tSCK is needed between ENB going
‘LOW’ and the first rising clock edge.
2. At least 21 values are read from DI on the rising
edge of the CLK signal.
- If more than 21 values are passed in, then only the
last 21 values are kept in a FIFO fashion.
- The data on DI should start by sending the value
destined for register 21 and finish by sending the
value destined for register 1.
- A range of clock frequencies can be used. A typical
rate is 10MHz. The clock should not exceed 20MHz.
- Setup (tSDI) and hold (tHDI) times are needed
around the rising clock edge.
3. The ENB pin is pulled ‘HIGH’ and the contents of the
registers are latched and take effect.
- After clocking in the last data bit, an additional
tHEN should elapse before pulling the ENB signal
‘HIGH’.
- After completing these steps, the new values will
affect within tD.
16
FN6981.1
November 19, 2009
QLx4600-SL30
ENB
tSCK
tHEN
CLK
tSDI tHDI
DI
R21
R20
R19
R1
FIGURE 27. TIMING DIAGRAM FOR PROGRAMMING THE INTERNAL REGISTERS OF THE QLx4600-SL30
Programming Multiple QLx4600-SL30
Devices
DI/DO Carryover
The DO pin (pin 17) can be used to daisy-chain the serial
bus among multiple QLx4600-SL30 chips. The DO pin
outputs the overflow data from the DI pin. Specifically, as
data is pipelined into a QLx4600-SL30, it proceeds
according to the following flow. First, a bit goes into
shadow register 1. Then, with each clock cycle, it shifts
over into subsequent higher numbered registers. After
shifting into register 21, it is output on the DO pin on the
same clock cycle. Thus, the DO signal is equal to the DI
signal, but delayed by 20 clock cycles. The timing
diagram for the DO pin is shown in Figure 27 where the
first 20 bits output from the DO are indefinite and
subsequent bits are the data fed into the DI pin. The
delay between the rising clock edge and the data
transition is tCQ.
The serial bus interface provides a simple means of
setting the equalizer boost levels with a minimal amount
of board circuitry. Many of the serial interface signals can
be shared among the QLx4600-SL30 devices on a board
and two options are presented in this section. The first
uses common clock and serial data signals along with
separate ENB signals to select which QLx4600-SL30
accepts the programmed changes. The second method
uses a common ENB signal as the serial data is
carried-over from one QLx4600-SL30 to the next.
Separate ENB Signals
Multiple QLx4600-SL30 devices can be programmed
from a common serial data stream as shown in
Figure 28. Here, each QLx4600-SL30 is provided its own
ENB signal, and only one of these ENB signals is pulled
‘LOW’, and hence accepting the register data, at a time.
In this situation, the programming of each equalizer
follows the steps outlined in Figure 29.
A diagram for programming multiple QLx4600-SL30s is
shown in Figure 30. It is noted that the board layout
should ensure that the additional clock delay experienced
between subsequent QLx4600-SL30s should be no more
than the minimum value of tCQ, i.e. 12ns.
Serial
Register
Data
QLx4600-SL30
(A)
DI
QLx4600-SL30
(B)
DI
ENB
CLK
QLx4600-SL30
(C)
DI
ENB
DO
CLK
QLx4600-SL30
(D)
DI
ENB
DO
CLK
ENB
DO
CLK
DO
Clock
ENB (A)
ENB (B)
ENB (C)
ENB (D)
FIGURE 28. SERIAL BUS PROGRAMMING MULTIPLE QLx4600-SL30 DEVICES USING SEPARATE ENB SIGNALS
17
FN6981.1
November 19, 2009
QLx4600-SL30
ENB
20 Clock Cycles
21st Rising Edge
tSCK
CLK
t CQ
First Bit from DI
DO
FIGURE 29. TIMING DIAGRAM FOR DI/DO CARRYOVER
Serial
Register
Data
QLx4600-SL30
(A)
ENB
DI
QLx4600-SL30
(B)
ENB
DI
QLx4600-SL30
(C)
ENB
DI
QLx4600-SL30
(D)
ENB
DI
CLK
CLK
CLK
CLK
DO
DO
DO
DO
Clock
ENB
FIGURE 30. SERIAL BUS PROGRAMMING MULTIPLE QLx4600-SL30 DEVICES USING DI/DO CARRYOVER
ENB
tSCK
tHEN
CLK
tSDI tHDI
DI
R21
R20
QLx4600-SL30 (D)
R1
R21
R1
QLx4600-SL30 (C)
R21
R1
QLx4600-SL30 (B)
R21
R1
QLx4600-SL30 (A)
FIGURE 31. TIMING DIAGRAM FOR PROGRAMMING MULTIPLE QLx4600-SL30 DEVICES USING DI/DO CARRYOVER
18
FN6981.1
November 19, 2009
QLx4600-SL30
Detection Threshold (DT) Pin Functionality
The QLx4600-SL30 is capable of maintaining periods of
line silence on any of its four channels by monitoring
each channel for loss of signal (LOS) conditions and
subsequently muting the outputs of a respective channel
when such a condition is detected. A reference current
applied to the detection threshold (DT) pin is used to set
the LOS threshold of the internal signal detection
circuitry. Current control on the DT pin is done via one or
two external resistors. Nominally, both a pull-up and
pull-down resistor are tied to the DT pin (Figure 32A),
but if adequate control of the supply voltage is
maintained to within ±3% of 1.2V, then a simple
pull-down resistor is adequate (as in Figure 32B).
Resistors used should be at least 1/16W, with ±1%
precision.
FIGURE 32A.
The internal bias point of the DT pin, nominally 1.05V, is
used in conjunction with the voltage divider (R1 and R2)
shown in Figure 32A to set the reference current on the
DT pin.
Case 1: Channels with less than or equal to 25dB loss at
2.5GHz (1Gb/s to 6Gb/s):
For signals transmitted on channels having less than
or equal to 25dB of loss at 2.5GHz, the optimal DT
reference current is 0µA. This optimal reference
current may be achieved by either leaving the DT pin
floating, or tying the DT pin to ground (GND) with a
10MΩ resistor
FIGURE 32B.
Case 2: Channels with greater 25dB loss at 2.5GHz
(1Gb/s to 6Gb/s):
For channels exhibiting more than 25dB of total loss
(this includes cable or FR-4 loss) the DT pin should
be configured for a reference sink current (coming
out of the DT pin) of approximately 2µA. A typical
configuration for a 2µA sink current is given in
Figure 32C. If the configuration in Figure 32B is
utilized, a 525kΩ resistor would be used.
FIGURE 32C.
FIGURE 32.
19
FN6981.1
November 19, 2009
QLx4600-SL30
Typical Application Reference Designs
Figures 33 and 34 show reference design schematics for a QLx4600-SL30 evaluation board with an SMA connector
interface. Figure 33 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 34
shows the schematic for the case when the level is set via the serial bus interface.
CP2[C]
39
CP2[B]
40
CP2[A]
41
CP1[B]
CP1[C]
42
44
43
NC
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
CP4[B]
OUT1[N]
1.2V
OUT2[P]
OUT2[N]
1.2V
OUT3[P]
OUT3[N]
1.2V
OUT4[P]
OUT4[N]
LOS3
LOS4
MODE
EQ Boost Control
for Channels 3 and 4
(See pages 15-17)
= SMA Connector
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin)
A
OUT1[P]
CP4[C]
DI
BGREF
23
8
22
32
21
7
NC
100pF*
10nF
1.2V
CP1[A]
NC
33
20
GND
34
6
16
Loss of signal indicator (Channels 1 and 2)
QLx4600-SL30
5
CP4[A]
LOS2
35
CP3[C]
LOS1
4
19
IN4[N]
36
18
1.2V
IN4[P]
3
CP3[B]
IN3[N]
37
CP3[A]
1.2V
IN3[P]
2
17
IN2[P]
IN2[N]
6kO
38
DO
1.2V
EQ Boost Control
for Channels 1 and 2
(See pages 15-17)
1
NC
IN1[N]
ENB
CLK
IN1[P]
46
DT
45
Detection threshold
reference current
100k
47nF
42.2k
1.2V
A) DC Blocking Capacitors = X7R or COG
0.1µF (>4GHz bandwidth)
Loss of signal indicator (Channels 3 and 4)
MODE at 1.2V: Serial Control Mode
MODE at GND: Binary Control Mode
QLx4600-SL30
LANE EXTENDER
Reference
Control Pin Mode
Quellan, Inc.
FIGURE 33. APPLICATION CIRCUIT FOR THE QLx4600-SL30 EVALUATION BOARD USING THE CONTROL PINS FOR
SETTING THE EQUALIZER COMPENSATION LEVEL
20
FN6981.1
November 19, 2009
QLx4600-SL30
Typical Application Reference Designs (Continued)
Enable Active Low
CP2[C]
39
CP2[B]
40
41
CP2[A]
CP1[C]
42
CP1[B]
43
CP1[A]
30
10
29
11
28
12
27
13
26
14
25
15
24
BGREF
A
OUT1[P]
OUT1[N]
1.2V
OUT2[P]
OUT2[N]
1.2V
OUT3[P]
OUT3[N]
1.2V
OUT4[P]
OUT4[N]
LOS3
LOS4
MODE
CP4[C]
23
9
22
31
21
8
DI
Bypass circuit for each VDD pin: 4, 7, 10, 29, 32, 35
(*100pF capacitor should be positioned closest to the pin)
45
32
Serial Data In
100pF*
10nF
1.2V
44
7
CP4[B]
GND
33
16
Loss of signal indicator (Channels 1 and 2)
34
6
CP4[A]
LOS2
QLx4600-SL30
5
20
LOS1
35
CP3[C]
IN4[P]
IN4[N]
4
19
1.2V
36
CP3[B]
IN3[N]
3
18
1.2V
IN3[P]
37
17
IN2[P]
IN2[N]
2
CP3[A]
1.2V
6kO
38
Serial Data Out
IN1[N]
46
CLK
IN1[P]
NC
1
DO
DT
ENB
Detection threshold
reference current
100k
47nF
42.2k
1.2V
Serial Clock In
Figures 33 and 34 show reference design schematics for a QLx4600-SL30 evaluation board with an SMA connector
interface. Figure 33 shows the schematic for the case when the equalizer boost level is set via the CP pins. Figure 34
shows the schematic for the case when the level is set via the serial bus interface.
NC
= SMA Connector
A) DC Blocking Capacitors = X7R or COG
0.1µF (>4GHz bandwidth)
Loss of signal indicator (Channels 3 and 4)
MODE at 1.2V: Serial Control Mode
MODE at GND: Binary Control Mode
QLx4600-SL30
LANE EXTENDER
Reference
Serial Control Mode
Quellan, Inc.
FIGURE 34. APPLICATION CIRCUIT FOR THE QLx4600-SL30 EVALUATION BOARD USING THE SERIAL BUS
INTERFACE FOR SETTING THE EQUALIZER COMPENSATION LEVEL
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FN6981.1
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QLx4600-SL30
About Q:ACTIVE®
Intersil has long realized that to enable the complex
server clusters of next generation datacenters, it is
critical to manage the signal integrity issues of electrical
interconnects. To address this, Intersil has developed its
groundbreaking Q:ACTIVE® product line. By integrating
its analog ICs inside cabling interconnects, Intersil is able
to achieve unsurpassed improvements in reach, power
consumption, latency, and cable gauge size as well as
increased airflow in tomorrow’s datacenters. This new
technology transforms passive cabling into intelligent
“roadways” that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing
cabling while reducing the need for thicker cables. This
significantly reduces cable weight and clutter, increases
airflow, and reduces power consumption.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
22
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QLx4600-SL30
Package Outline Drawing
L46.4x7
46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN)
Rev 0, 9/09
2.80
4.00
42X 0.40
A
B
46
39
6
PIN 1
INDEX AREA
7.00
38
5.50 ±0.1
Exp. DAP
5.60
15
24
(4X)
6
PIN 1
INDEX AREA
1
0.05
46X 0.20 4
0.10 M C A B
SIDE VIEW
TOP VIEW
16
23
2.50 ±0.1
Exp. DAP
46X 0.40
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.70 ±0.05
C
SEATING PLANE
0.05 C
SIDE VIEW
C
0.152 REF
5
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
( 6.80 )
( 42X 0.40)
( 5.50 )
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
(46X 0.20)
either a mold or mark feature.
( 46 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
23
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