CYPRESS CY23S08ZXC-1H

CY23S08
3.3V Zero Delay Buffer
Features
■
Zero input output propagation delay, adjustable by capacitive
load on FBK input
■
Multiple configurations (see Table 3 on page 3)
■
Multiple low-skew outputs
❐ 45 ps typical output-output skew (–1)
❐ Two banks of four outputs, three-stateable by two select
inputs
■
10 MHz to 140 MHz operating range
■
65 ps typical cycle-cycle jitter (–1, –1H)
■
Advanced 0.65 μm CMOS technology
■
Space saving 16-pin, SOIC and TSSOP packages
■
3.3V operation
■
Spread Aware
The CY23S08 has two banks of four outputs each, which can be
controlled by the Select inputs as shown in Table 2 on page 3. If
all output clocks are not required, Bank B can be three-stated.
The select inputs also enable the input clock to be directly
applied to the output for chip and system testing purposes.
The CY23S08 PLL enters a power down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
50 μA of current draw. The PLL shuts down in two additional
cases as shown in Table 2 on page 3.
Multiple CY23S08 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY23S08 is available in five different configurations, as
shown in Table 3 on page 3. The CY23S08–1 is the base part,
where the output frequencies equal the reference if there is no
counter in the feedback path. The CY23S08–1H is the high drive
version of the –1, and rise and fall times on this device are much
faster.
The CY23S08–2 enables the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the feedback
pin. The CY23S08–2H is the high drive version of the –2, and
rise and fall times on this device are much faster.
Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The CY23S08–3 enables the user to obtain 4X and 2X
frequencies on the outputs.
The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback must be driven into
the FBK pin, and obtained from one of the outputs. The
input-to-output propagation delay is less than 350 ps, and
output-to-output skew is less than 250 ps.
The CY23S08–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is versatile, and can be used in a variety
of applications.
Logic Block Diagram
/2
FBK
PLL
REF
MUX
CLKA1
CLKA2
Extra Divider (–3, –4)
CLKA3
CLKA4
S2
Select Input
Decoding
S1
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –2H, –3)
Cypress Semiconductor Corporation
Document #: 38-07265 Rev. *I
•
198 Champion Court
CLKB4
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 16, 2009
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CY23S08
Pinouts
Figure 1. 16-Pin Package
Top View
REF
CLKA1
1
16
2
15
CLKA2
VDD
3
14
4
13
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
FBK
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
Table 1. Pin Definition - 16-Pin Package
Pin
Signal
Description
1
REF[1]
Input reference frequency, 5V tolerant input
2
CLKA1[2]
Clock output, Bank A
3
CLKA2[2]
Clock output, Bank A
4
VDD
3.3V supply
5
GND
Ground
6
CLKB1[2]
Clock output, Bank B
7
CLKB2[2]
Clock output, Bank B
8
S2[3]
Select input, bit 2
9
S1[3]
Select input, bit 1
10
CLKB3[2]
Clock output, Bank B
11
CLKB4[2]
Clock output, Bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[2]
Clock output, Bank A
15
CLKA4[2]
Clock output, Bank A
16
FBK
PLL feedback input
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
Document #: 38-07265 Rev. *I
Page 2 of 11
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CY23S08
Table 2. Select Input Decoding
S2
S1
CLOCK A1–A4
CLOCK B1–B4
Output Source
PLL Shutdown
0
0
Three-State
Three-State
PLL
Y
0
1
Driven
Three-State
PLL
N
1
0
Driven
Driven
Reference
Y
1
1
Driven
Driven
PLL
N
Table 3. Available CY23S08 Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
CY23S08–1
Bank A or Bank B
Reference
Reference
CY23S08–1H
Bank A or Bank B
Reference
Reference
CY23S08–2
Bank A
Reference
Reference/2
CY23S08–2H
Bank A
Reference
Reference/2
CY23S08–2
Bank B
2 X Reference
Reference
CY23S08–2H
Bank B
2 X Reference
Reference
CY23S08–3
Bank A
2 X Reference
Reference or Reference[4]
CY23S08–3
Bank B
4 X Reference
2 X Reference
CY23S08–4
Bank A or Bank B
2 X Reference
2 X Reference
Spread Aware
Many systems designed now use the Spread Spectrum Frequency Timing Generation (SSFTG) technology. Cypress is one of the
pioneers of SSFTG development, and designed this product so as not to filter off the Spread Spectrum feature of the Reference input,
assuming it exists. When a zero delay buffer does not pass through the SS feature, the result is a significant amount of tracking skew
which may cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology, please see Cypress’s application note EMI Suppression Techniques with
Spread Spectrum Frequency Timing Generator (SSFTG) ICs.
Note
4. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23S08–2.
Document #: 38-07265 Rev. *I
Page 3 of 11
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CY23S08
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
Max Soldering Temperature (10 sec.) ........................ 260°C
DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V
Junction Temperature ................................................. 150°C
DC Input Voltage REF ........................................... –0.5 to 7V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
Storage Temperature ................................. –65°C to +150°C
Operating Conditions for CY23S08SC-XX Commercial Temperature Devices
Parameter[5]
Description
Min
Max
Unit
3.0
3.6
V
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance, below 100 MHz
—
30
pF
Load Capacitance, from 100 MHz to 140 MHz
—
15
pF
—
7
pF
CIN
Input
Capacitance[6]
Electrical Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
Input LOW Voltage
—
0.8
V
VIH
Input HIGH Voltage
2.0
—
V
IIL
Input LOW Current
VIN = 0V
—
50.0
μA
IIH
Input HIGH Current
VIN = VDD
—
100.0
μA
VOL
Output LOW Voltage[7]
IOL = 8 mA (–1, –2, –3, –4)
IOL = 12 mA (-1H, -2H)
—
0.4
V
VOH
Output HIGH Voltage[7]
IOH = –8 mA (–1, –2, –3, –4)
IOH = –12 mA (–1H, –2H)
2.4
—
V
IDD (PD mode) Power down Supply Current
REF = 0 MHz
—
12.0
μA
IDD
Unloaded outputs, 100 MHz REF, Select
inputs at VDD or GND
—
45.0
mA
—
70.0
(–1H, –2H)
mA
Unloaded outputs, 66 MHz REF
(–1,–2,–3,–4)
—
32.0
mA
Unloaded outputs, 33 MHz REF
(–1,–2,–3,–4)
—
18.0
mA
Supply Current
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices
Parameter[8]
Name
Test Conditions
Min
Typ.
Max
Unit
t1
Output Frequency
30 pF load, –1, –1H, –2, –3 devices
10
—
100
MHz
t1
Output Frequency
30 pF load, –4 devices
15
—
100
MHz
t1
Output Frequency
20 pF load, –1H device
10
—
133.3
MHz
t1
Output Frequency
15 pF load, –1, –2, –3, devices
10
—
140.0
MHz
t1
Output Frequency
15 pF load, –4 devices
15
—
140.0
MHz
Duty
= t2 ÷ t1
(–1,–2,–3,–4,–1H, -2H)
Measured at VDD/2, FOUT = 66.66 MHz
30-pF load
40.0
50.0
60.0
%
Duty Cycle[7] = t2 ÷ t1
(–1,–2,–3,–4,–1H, -2H)
Measured at VDD/2, FOUT <66.66 MHz
15 pF load
45.0
50.0
55.0
%
Cycle[7]
Notes
5. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. Applies to both Ref Clock and FBK.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters are specified with loaded outputs.
Document #: 38-07265 Rev. *I
Page 4 of 11
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CY23S08
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)
Parameter[8]
Name
Test Conditions
Min
Typ.
Max
Unit
t3
Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30 pF
load
—
—
2.20
ns
t3
Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15 pF
load
—
—
1.50
ns
t3
Rise Time[7] (–1H, -2H)
Measured between 0.8V and 2.0V, 30 pF
load
—
—
1.50
ns
t4
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30 pF
load
—
—
2.20
ns
t4
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15 pF
load
—
—
1.50
ns
t4
Fall Time[7] (–1H, 2H)
Measured between 0.8V and 2.0V, 30 pF
load
—
—
1.25
ns
t5
Output to Output Skew on
same Bank (–1)[7]
All outputs equally loaded
45
200
ps
Output to Output Skew on
same Bank
(–1H,–2,–2H,–3)[7]
All outputs equally loaded
—
105
150
ps
Output to Output Skew on
same Bank (–4)[7]
All outputs equally loaded
—
70
100
ps
Output to Output Skew
(–1H, -2H)
All outputs equally loaded
—
—
200
ps
Output Bank A to Output
Bank B Skew (–1,–2, –3)
All outputs equally loaded
—
—
300
ps
Output Bank A to Output
Bank B Skew (–4)
All outputs equally loaded
—
—
215
ps
Output Bank A to Output
Bank B Skew (–1H)
All outputs equally loaded
—
—
250
ps
–250
—
+275
ps
700
ps
t6
Delay, REF Rising Edge to Measured at VDD/2
FBK Rising Edge[7]
t7
Device to Device Skew[7]
Measured at VDD/2 on the FBK pins of
devices
—
—
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on –1H,
–2H device using Test Circuit #2
1
—
tJ
Cycle to Cycle Jitter[7]
(–1, –1H)
Measured at 66.67 MHz, loaded outputs, 15,
30 pF loads: 133 MHz, 15 pF load
—
65
125
ps
Cycle to Cycle Jitter[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
15 pF load
—
85
300
ps
Cycle to Cycle Jitter[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
—
—
400
ps
tJ
Cycle to Cycle Jitter[7]
(–3,–4)
Measured at 66.67 MHz, loaded outputs
15, 30 pF loads
—
—
200
ps
tLOCK
PLL Lock Time[7]
Stable power supply, valid clocks presented
on REF and FBK pins
—
—
1.0
ms
Document #: 38-07265 Rev. *I
V/ns
Page 5 of 11
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CY23S08
Switching Waveforms
Figure 2. Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
Figure 3. All Outputs Rise and Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
3.3V
0V
t4
t3
Figure 4. Output-Output Skew
OUTPUT
1.4V
1.4V
OUTPUT
t5
Figure 5. Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
FBK
t6
Figure 6. Device-Device Skew
VDD/2
FBK, Device 1
VDD/2
FBK, Device 2
t7
Document #: 38-07265 Rev. *I
Page 6 of 11
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CY23S08
Test Circuits
Figure 7. Test Circuit 1
VDD
0.1 μF
CLK OUT
OUTPUTS
C LOAD
V DD
0.1 μF
GND
GND
Test Circuit for all parameters except t8
Figure 8. Test Circuit 2
Test Circuit # 2
V DD
0.1 μF
1 KΩ
CLK out
OUTPUTS
1 KΩ
10 pF
V DD
0.1 μF
GND
GND
Test Circuit for t8, Output slew rate on –1H device
Document #: 38-07265 Rev. *I
Page 7 of 11
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CY23S08
Ordering Information
Ordering Code
Package Type
Operating Range
Pb-free
CY23S08SXC–1
16-pin 150-mil SOIC
Commercial
CY23S08SXC–1T
16-pin 150-mil SOIC–Tape and Reel
Commercial
CY23S08SXI–1H
16-pin 150-mil SOIC
Industrial
CY23S08SXI–1HT
16-pin 150-mil SOIC–Tape and Reel
Industrial
CY23S08ZXC-1H
16-pin 4.4mm TSSOP
Commercial
CY23S08ZXC-1HT
16-pin 4.4mm TSSOP
Commercial
CY23S08SXC–2
16-pin 150-mil SOIC
Commercial
CY23S08SXC–2T
16-pin 150-mil SOIC–Tape and Reel
Commercial
CY23S08SXC–2H
16-pin 150-mil SOIC
Commercial
CY23S08SXC–2HT
16-pin 150-mil SOIC–Tape and Reel
Commercial
CY23S08SXI–2
16-pin 150-mil SOIC
Industrial
CY23S08SXI–2T
16-pin 150-mil SOIC–Tape and Reel
Industrial
CY23S08SXC-4
16-pin 150-mil SOIC
Commercial
CY23S08SXC-4T
16-pin 150-mil SOIC–Tape and Reel
Commercial
CY23S08SXI-4
16-pin 150-mil SOIC
Industrial
CY23S08SXI-4T
16-pin 150-mil SOIC–Tape and Reel
Industrial
Document #: 38-07265 Rev. *I
Page 8 of 11
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CY23S08
Package Drawings and Dimensions
Figure 9. 16-Pin (150-mil) SOIC S16
PIN 1 ID
8
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
REFERENCE JEDEC MS-012
PACKAGE WEIGHT 0.15gms
0.150[3.810]
0.157[3.987]
0.230[5.842]
0.244[6.197]
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
9
16
0.386[9.804]
0.393[9.982]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.016[0.406]
0.035[0.889]
0°~8°
0.0138[0.350]
0.0192[0.487]
0.004[0.102]
0.0098[0.249]
0.0075[0.190]
0.0098[0.249]
51-85068-*B
Figure 10. 16-Pin Thin Shrunk Small Outline Package (4.40 mm Body) Z16
PIN 1 ID
1
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
Document #: 38-07265 Rev. *I
Page 9 of 11
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CY23S08
Document History Page
Document Title: CY23S08 3.3V Zero Delay Buffer
Document Number: 38-07265
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
110530
SZV
12/02/01
Change from Spec number: 38-01107 to 38-07265
*A
122863
RBI
12/20/02
Added power up requirements to operating conditions information.
*B
130951
RGL
11/26/03
Corrected the Switching Characteristics parameters to reflect the W152 device
and new characterization.
*C
204201
RGL
See ECN
Corrected the Block Diagram
*D
231100
RGL
See ECN
Fixed Typo in table 2.
*E
378878
RGL
See ECN
Added Industrial Temp and Pb Free Devices
Added typical char data
Removed “Preliminary”
*F
391564
RGL
See ECN
Changed output-to-output skew typical value from 90ps to 45ps
Added cycle-to-cycle jitter (-2) typical value of 85ps
*G
1442823
WWZ/AESA
See ECN
Updated ordering info with status update. Added new Pb-free part numbers.
*H
2600345
WWZ/PYRS
11/03/08
Updated max frequency number from 133 MHz to 140 MHz on page 1 and page
4 load capacitance description
*I
2658081
KVM/PYRS
02/16/09
Corrected TSSOP package size (from 150 mil to 4.4 mm) in Ordering Information Table. Removed references to SOIC in the pinout drawing and pin
description table on page 2.
Added CY23S08ZXC-1HT to the Ordering Information Table.
Updated Ordering Information Table to remove obsolete devices. Removed
Status column.
Document #: 38-07265 Rev. *I
Page 10 of 11
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CY23S08
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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psoc.cypress.com/solutions
psoc.cypress.com/low-power
wireless.cypress.com
Precision Analog
memory.cypress.com
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psoc.cypress.com/lcd-drive
CAN 2.0b
psoc.cypress.com/can
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© Cypress Semiconductor Corporation, 2001-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07265 Rev. *I
Revised February 16, 2009
Page 11 of 11
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