SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Product List
Feature
SM8951BL25, 25 MHz 4KB internal memory MCU
SM8951BC25, 25 MHz 4KB internal memory MCU
SM8951BC40, 40 MHz 4KB internal memory MCU
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General Description
The SM8951B series product is an 8-bits single
chip micro controller with 4KB flash embedded. It
provides hardware features and a powerful
instruction set, necessary to make it a versatile
and cost effective controller for those applications
demand up to 32 I/O pins or need up to 4KB flash
memory either for program or for data or mixed.
To program the flash block, a commercial
programmer is cap-able to do it.
Ordering Information
SM8951BihhkL
yymmv
i: process identifier {L=3.0V~3.6V,C=4.5V~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
yy: year,
mm: month
v: version identifier {, A, B,...}
L:PB Free identifier
{No text is Non-PB Free，”P” is PB Free}
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
General 8051 family compatible
12 clocks per machine cycle
4KB internal flash memory
128 bytes data RAM
Two 16 bit timers/counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instruction
Industrial Level
8-bit unsigned division
8-bit unsigned multiply
BCD arithmetic
Direct addressing
Indirect addressing
Nested interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and power down mode
Code protection function
Strong Noise immunity
One watch dog timer (WDT)
Reduce EMI (inhibit ALE)
Taiwan
6F, No.10-2 Li- Hsin 1st Road ,
Science-based Industrial Park,
Hsinchu, Taiwan 30078
Pin / Pad Configuration
Page 2
Page 3
Page 4
TEL: 886-3-567-1820
886-3-567-1880
FAX: 886-3-567-1891
886-3-567-1894
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
1
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Pin Configuration
1
40
VDD
P1.1
2
39
P0.0/AD0
P1.2
3
38
P0.1/AD1
P1.3
4
37
P0.2/AD2
P1.4
5
36
P0.3/AD3
P1.5
6
35
P0.4/AD4
P1.6
7
34
P0.5/AD5
P1.7
8
33
P0.6/AD6
RESET
9
32
P0.7/AD7
RXD/P3.0
10
31
EA
TXD/P3.1
11
30
ALE
INT0/P3.2
12
29
PSEN
INT1/P3.3
13
28
P2.7/A15
T0/P3.4
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
WR/P3.6
16
25
P2.4/A12
RD/P3.7
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
P2.0/A8
SyncMOS
P1.0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
2
06/2009
SyncMOS Technologies International, Inc.
SM8951B
39
38
P0.3/AD3
P2.7/A15
T0/P3.4
P2.6/A14
T1/P3.5
P2.5/A13
18
19
20
21
22
23
24
25
26
27
28
A12/P2.4
37
P0.2/AD2
INT1/P3.3
A11/P2.3
36
P0.1/AD1
PSEN
A10/P2.2
35
P0.0/AD0
INT0/P3.2
A9/P2.1
34
VDD
ALE
A8/P2.0
TXD/P3.1
33
NC
NC
NC
NC
32
P1.0
EA
VSS
RXD/P3.0
31
P1.1
P0.7/AD7
XTAL1
RESET
30
P1.2
P0.6/AD6
XTAL2
P1.7
P1.6
RD/P3.7
P0.5/AD5
P1.5
WR/P3.6
P0.4/AD4
29
P1.3
40
7
41
8
42
9
43
10
44
11
1
12
2
13
3
14
4
15
5
16
6
17
P1.4
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
3
06/2009
SyncMOS Technologies International, Inc.
SM8951B
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NC
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
33
32
31
30
29
28
27
26
25
24
23
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
17
NC
P1.0
40
16
VSS
P1.1
41
15
XTAL1
P1.2
42
14
XTAL2
P1.3
43
13
P3.7/RD
P1.4
44
12
P3.6/WR
11
39
T1/P3.5
NC
10
P2.0/A8
T0/P3.4
18
9
38
INT1/P3.3
VDD
8
P2.1/A9
INT0/P3.2
19
7
37
TXD/P3.1
AD0/P0.0
6
P2.2/A10
NC
20
5
36
RXD/P3.0
AD1/P0.1
4
P2.3/A11
RESET
21
3
35
P1.7
AD2/P0.2
2
P2.4/A12
P1.6
22
1
34
P1.5
AD3/P0.3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
4
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Block Diagram
Timer 1
Timer 0
Decoder &
Register
Stack
Pointer
128
bytes RAM
Buffer
WDT
RES
Reset
Circuit
Vdd
Vss
Power
Circuit
to pertinent blocks
DPTR
Acc
PC
Incrementer
to whole chip
Buffer2
Interrupt
Circuit
Buffer1
to pertinent blocks
Program
Counter
ALU
Register
PSW
to whole system
Timing
Generator
4K
bytes
Instruction
Flash
Regist er
Port 0
Latch
Port 0
Driver & Mux
8
Port 1
Latch
Port 2
Latch
Port 3
Latch
Memory
Port 1
Port 2
Port 3
Driver & Mux Driver & Mux Driver & Mux
8
8
8
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
5
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Pin Description
40L
PDIP
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
44L
PQFP
Pin
40
41
42
43
44
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
19
20
21
22
23
24
25
26
27
29
44L
PLCC
Pin
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
24
25
26
27
28
29
30
31
32
33
35
Symbol
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RES
P3.0/RXD
P3.1/TXD
P3.2/#INT0
P3.3/#INT1
P3.4/T0
P3.5/T1
P3.6/#WR
P3.7/#RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
#PSEN
ALE
#EA
32
33
34
35
36
37
38
39
40
30
31
32
33
34
35
36
37
38
36
37
38
39
40
41
42
43
44
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
Active
H
L/ L/ -
L/ L/ -
L
L
I/O
Names
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
i
bit 0 of port 1
bit 1 of port 1
bit 2 of port 1
bit 3 of port 1
bit 4 of port 1
bit 5 of port 1
bit 6 of port 1
bit 7 of port 1
Reset
bit 0 of port 3 & Receive data
bit 1 of port 3 & Transmit data
bit 2 of port 3 & low true interrupt 0
bit 3 of port 3 & low true interrupt 1
bit 4 of port 3Timer 0
bit 5 of port 3 & Timer 1
bit 6 of port 3 & external memory write
bit 7 of port 3 & external memory read
Crystal out
Crystal in
Sink Voltage, Ground
bit 0 of port 2 & bit 8 of external memory address
bit 1 of port 2 & bit 9 of external memory address
bit 2 of port 2 & bit 10 of external memory address
bit 3 of port 2 & bit 11 of external memory address
bit 4 of port 2 & bit 12 of external memory address
bit 5 of port 2 & bit 13 of external memory address
bit 6 of port 2 & bit 14 of external memory address
bit 7 of port 2 & bit 15 of external memory address
Program Storage Enable
Address Latch Enable
External Access(If you are not using external memory,
please keep this pin to VCC)
bit 7 of port 0 & data/address bit 7 of external memory
bit 6 of port 0 & data/address bit 6 of external memory
bit 5 of port 0 & data/address bit 5 of external memory
bit 4 of port 0 & data/address bit 4 of external memory
bit 3 of port 0 & data/address bit 3 of external memory
bit 2 of port 0 & data/address bit 2 of external memory
bit 1 of port 0 & data/address bit 1 of external memory
bit 0 of port 0 & data/address bit 0 of external memory
Drive Voltage, Vcc
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
o
o
i
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
6
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Table 1 SFR Map
$F8
$F0
$FF
B
0000 0000
$F7
$E8
$E0
$EF
ACC
0000 0000
$E7
$D8
$D0
$DF
PSW
0000 0000
$D7
$C8
$CF
$C0
$C7
$B8
$B0
$A8
$A0
$98
$90
$88
$80
IP
0000 0000
P3
1111 1111
IE
0000 0000
P2
1111 1111
SCON
0000 0000
P1
1111 1111
TCON
0000 0000
P0
1111 1111
SCONF
0000 0000
$BF
$B7
$AF
$A7
SBUF
xxxx xxxx
WDTC
0000 0000
$9F
$97
TMOD
0000 0000
SP
0000 0111
TL0
0000 0000
DPL
0000 0000
TL1
0000 0000
DPH
0000 0000
TH0
0000 0000
(Reserved)
TH1
0000 0000
$8F
PCON
0000 0000
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
7
06/2009
$87
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Target Spec.
Absolute Rating
Symbol
Description
Min.
Typ.
Max.
Unit.
Remarks
TA
VCC5
VCC3.3
Fosc 25
Fosc 40
Operating temperature
Supply voltage
Supply voltage
Oscillator Frequency
Oscillator Frequency
-40
4.5
3.0
25
5.0
3.3
85
5.5
3.6
25
40
℃
V
V
MHz
MHz
Ambient temperature under bias
For 3.3V application
For 5.0V application
DC Characteristic
VCC = 5V (±10%), VSS=0V TA= -40℃ to 85℃
SYMBOL
VCC
TEST
CONDITIONS
PARAMETER
Supply Voltage
ICC
Supply current operating
IID
Supply current IDLE Mode
IPD
Supply current Power-Down MODE
LIMITS
MIN
UNIT
MAX
4.5
See notes 1
fCLK = 12MHz VCC = 5.5V
See note 2
fCLK = 12MHz VCC = 5.5V
See note 3；VCC (= 5.5V)
5.5
V
20
mA
6.5
mA
30
μA
0.8
0.8
Vcc+0.5
Vcc+0.5
-75
-650
±10
V
V
V
V
μA
μA
μA
0.45
0.45
V
V
V
V
kΩ
pF
INPUT
VIL1
VIL2
VIH1
VIH2
IIL
ITL
ILI
Input LOW voltage, P0, P1, P2, P3, /EA
Input LOW voltage, RES, XTAL1
Input HIGH voltage, P0, P1, P2, P3, /EA
Input HIGH voltage, RES, XTAL1
Input current LOW level Port 1,2,3
Transition current High to Low Port 1,2,3
Input leakage current ,Port 0
VOL1
VOL2
VOH1
VOH2
RRST
CIO
Output LOW voltage, Port 0,ALE, /PSEN
Output LOW voltage, Port 1, 2, 3
Output High voltage Port0 ALE, /PSEN
Output High voltage Port 1,2,3
Internal RESET pull-down resistor
Pin capacitance
-0.5
0
2.0
70%VCC
VIN = 0.45V
VIN = 2.0 V
0.45V < VIN < VCC-0.3V
OUTPUT
IOL = 8mA，VCC=5.0V
IOL = 6.5mA，VCC =5.0V
IOH = -800uA，VCC =5.0V
IOH = -60μA，VCC =5.0V
2.4
2.4
50
300
10
Test freq=1MHz, TA=25℃
VCC = 3.3V (±10%), VSS=0V , TA= -40℃ to 85℃
SYMBOL
VCC
TEST
CONDITIONS
PARAMETER
Supply Voltage
ICC
Supply current operating
IID
Supply current IDLE Mode
IPD
Supply current Power-Down MODE
LIMITS
MIN
3.0
See note 1
fCLK = 12MHz VCC = 3.6V
See note 2
fCLK = 12MHz VCC = 3.6V
See note 3；VCC (= 3.6V)
3.6
V
10
mA
5
mA
20
μA
INPUT
VCC = 3.6V
0
0.2 VCC -0.2
VCC = 3.6V
0
0.2 VCC -0.2
VCC = 3.6V
0
0.2 VCC -0.2
VCC = 3.6V
2.0
VCC + 0.2
VCC = 3.6V
2.0
VCC + 0.2
VCC = 3.6V
0.8 VCC
VCC + 0.2
VCC = 3.0V ~3.6V,
IIN1
Input current LOW level Port 1,2,3
-10
50
VIN = 0.45V.
Specifications subject to change without notice contact your sales representatives for the most recent information.
VIL1
VIL2
VIL3
VIH1
VIH2
VIH3
Input LOW voltage, P0, P1, P2, P3, /EA
Input LOW voltage, RST
Input LOW voltage, XTAL1
Input HIGH voltage, P0, P1, P2, P3, /EA
Input HIGH voltage, RST
Input HIGH voltage, XTAL1
ISSFD-M022Ver:BSM8951B
8
UNIT
MAX
V
V
V
V
V
V
μA
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
ITL
Transition current High to Low Port 1,2,3
ILI
Input leakage current P0, /EA
VOL1
VOL2
VOH1
VOH2
ISK1
ISK2
ISR1
ISR2
RRST
CIO
Output LOW voltage, Port 0,ALE, /PSEN
Output Low voltage Port 1,2,3
Output High voltage Port0, ALE, /PSEN
Output High voltage Port 1,2,3
Sink Current Port 1, 2, 3
Sink Current Port 0,ALE, /PSEN
Source Current Port 1, 2, 3
Source Current Port 0,ALE, /PSEN
Internal RESET pull-down resistor
Pin capacitance
See note 4
VCC = 3.6V, VIN = 2.0 V
VCC = 3.0V ~3.6V,
0.45V<VIN<VCC
OUTPUT
IOL = 6mA，VCC =3.3V
IOL = 5mA，VCC =3.3V
IOH =-300uA，VCC =3.3V
IOH =-20μA，VCC =3.3V
VCC = 3.3V, VIN = 0.4 V
VCC = 3.3V, VIN = 0.4 V
VCC = 3.3V, VIN = 2.4 V
VCC = 3.3V, VIN = 2.4 V
-75
400
μA
-10
10
μA
0.4
0.4
V
V
V
V
mA
mA
uA
mA
kΩ
pF
2.4
2.4
50
Test freq=1MHz, TA=25℃
6
8
-80
-8
300
10
NOTES FOR DC ELECTRICAL CHARACTERISTICS
1.
The operating supply current is measured with all output disconnected;
XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect;
/EA=RST=Port0=VDD;
2.
The IDLE MODE supply current is measured with all output pins disconnected;
XTAL1 driven with tr = tf = 5ns; VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect;
/EA=Port0=VDD;
3.
The POWER-DOWN MODE supply current is measured with all output pins disconnected;
VIL = VSS+0.5V; VIH=VCC-0.5V; XTAL2 not connect; /EA= Port0=VDD;
4.
Port 1, 2, 3, and 4 sources a transition current when they are being externally driven from HIGH to LOW. The transition current reaches its
maximum value when VIN is approximately 2V.
5.
Capacities loading on port 0 and 2 may cause spurious noise to be superimposed on VOL of ALE and port 1, 3, and 4. The noise is due to external
bus capacitance discharging into port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases
(capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt
Trigger, or use an address latch with a Schmitt trigger STROBE input.
ICC Active mode test circuit
ICC
Vcc
Vcc
VCC
RST
SM8951B
(NC)
Clock Signal
PO
EA
8
XTAL2
XTAL1
VSS
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
9
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
AC Characteristic
VCC=5.0V±10%, VSS=0V, tclk min = 1/ fmax(maximum operating frequency)
TA= -40℃ to +85℃
CL=100pF for Port0, ALE and /PSEN; CL=80pF for all other outputs unless otherwise specified.
Symbol
FIGURE
PARAMETER
MIN
MAX
UNIT
40(1)
20
20
3.33
10
10
-
ns
ns
ns
ns
ns
Ns
MIN
MAX
UNIT
3.0
2tCLK-40
tCLK-40
tCLK-30
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
External Clock drive into XTAL1
tCLK
4
tCLKH
4
tCLKL
4
tCLKR
4
tLLIV
4
tCYC
4
NOTES:
1. Operating at 25MHz.
Xtal1 Period
Xtal1 HIGH time
Xtal1 LOW time
XTAL1 rise time
XTAL1 fall time
Controller cycle time = tCLK / 4
Symbol
FIGURE
PARAMETER
1/tCLK
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
7
7
7
7
7
7
7
7
7
7
7
7
System clock frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE LOW to valid instruction in
ALE LOW to /PSEN LOW
/PSEN pulse width
/PSEN LOW to valid instruction in
Input instruction hold after /PSEN
Input instruction float after /PSEN
Address to valid instruction in
/PSEN low to address float
tAVLL
tLLAX
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
8,9
8,9
8
9
8
8
8
8
8
8,9
8,9
9
9
9
8
8,9
Address valid to ALE LOW
Address hold after ALE LOW
/RD pulse width
/WR pulse width
/RD LOW to valid data in
Data hold after /RD
Data float after /RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to /RD or /WR LOW
Address valid to /WR or /RD LOW
Data valid to /WR transition
Data before /WR
Data hold after /WR
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
10
10
10
10
10
Serial port clock time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Program Memory
4tCLK-100
tCLK-30
3tCLK-45
3tCLK-105
0
tCLK -25
5tCLK-105
10
Data Memory
tCLK-40
tCLK-35
6tCLK-100
6tCLK-100
0
tCLK+40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10tCLK-133
ns
ns
ns
ns
ns
5tCLK-165
0
3tCLK-50
4tCLK-130
tCLK-50
7tCLK-150
tCLK-50
tCLK-40
2tCLK-70
8tCLK-150
9tCLK-165
3tCLK+50
UART
12tCLK
10tCLK-133
2tCLK-117
0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
10
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
tCLKH
tCLKR
tLLIV
VIH1
0.8V
tCLKL
tCLK
Figure 4 External Clock Drive waveform
2.0V
2.0V
Test Points
0.8V
0.8V
Notes:
AC inputs during testing are driven at 2.4V for logic
“HIGH” and 0.45V for logic “LOW”. Timing
measurements are at 2.0V for logic “HIGH” and 0.8V
Figure 5 AC Testing Input/Output
Floating
2.0V
2.0V
0.8V
0.8V
Notes:
The float state is define as the point which PORT 0
pins sinks 3.2mA or source 400μA at the voltage
test level.
Figure 6 AC Testing, Floating Waveform
t LHLL
ALE
t LLPL
t PLPH
t AVLL
t PLIV
/PSEN
t PLAZ
t LLAX
t PXIZ
t LLIV
PORT0
t PXIX
A0-A7
INSTR IN
A0-A7
t AVIV
PORT2
A8-A15
A8-A15
A8-A15
Figure 7 External Program Memory Read Cycle
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
11
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
ALE
t WHLH
/PSEN
t LLDV
t LLWL
t RLRH
/RD
t AVLL
t RLDV
t LLAX
PORT0
t RHDZ
t RLAZ
t RHDX
DATA IN
A0 - A7 (RI or DPL)
A0 - A7 (PCL)
INSTR IN
t AVDV
t AVWL
PORT2
A8 - A15 of DPH or PORT2
A8 - A15 (PCH)
Figure 8 External Data Memory read cycle
ALE
tWHLH
/PSEN
tLLWL
tWLWH
/WR
tQVWH
tAVLL
PORT0
tLLAX
tQVWX
tWHQX
DATA OUT
A0 - A7 (RI or DPL)
A0 - A7 (PCL)
INSTR IN
tAVWL
A8 - A15 of DPH or PORT2
PORT2
A8 - A15 (PCH)
Figure 9 External Data Memory write cycle
Instruction
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tQVXH
TXD
tXHQX
0
1
tXHDV
RxD
VALID
2
3
4
5
6
tXHDX
VALID
7
Set_RI
VALID
VALID
VALID
VALID
VALID
VALID
Figure10 UART waveform in Shift Register MODE
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
12
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Instruction Set
The SM8951B uses the powerful instruction set of 80C51. It consists of 49 single-byte, 42 two-byte, and 15 threebyte instructions. Among them 63 instruction are executed in 1 machine-cycle, 46 instructions in 2 machine-cycles,
and the multiply, 2 instructions in 4 machine-cycles.
A summary of the instruction set is given in Table 3.
Addressing Mode
Notes on instruction set and address modes:
Rn
direct
Register R7-R0 of the currently selected register bank.
8-bits internal data location’s address. This could be internal DATA RAM location (0-127) or a
SFR [i.e., I/O port, control register, status register, etc. (128-255)]
8-bits RAM location addressed indirectly through register R1 or R0 of the actual register bank
8-bits constant included in the instruction
16-bits constant included in the instruction
11-bits destination address. Used by ACALL and AJMP. The branch can be anywhere within the
same 2 Kbytes page of program memory as the first byte of the following instruction.
Signed (2’s complement) 8-bits offset byte. Used by SJMP and all conditional jumps. Range is
-128 to +127 bytes relative to first byte of the following instruction.
Direct addressed bit in internal data RAM or SFR
@Ri
#data
#data16
addr11
rel
bit
Table 3: A Summary of the instruction set
Mnemonic
Arithmetic Instructions
ADD
A,Rn
ADD
A,direct
ADD
A,@Ri
ADD
A,#data
ADDC
A,Rn
ADDC
A,direct
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
DEC
DEC
DEC
DEC
INC
MUL
DIV
A,@Ri
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
A
Rn
direct
@Ri
DPTR
AB
AB
DA
A
Logical Instructions
ANL
A,Rn
ANL
A,direct
ANL
A,@Ri
ANL
A,#data
ANL
direct,A
ANL
direct,#data
ORL
A,Rn
ORL
A,direct
ORL
A,@Ri
OPERATION
BYTE
CYCLE
A = A + Rn
A = A + direct
A = A + <@Ri>
A = A + #data
A = A + Rn + C
A = A + direct + C
1
2
1
2
1
2
1
1
1
1
1
1
A = A + @Ri + C
A = A + #data + C
A = A － Rn － C
A = A － direct － C
A = A － <@Ri> － C
A = A－#data － C
A=A+1
Rn = Rn + 1
direct = direct + 1
<@Ri> = <@Ri> + 1
A=A － 1
Rn = Rn － 1
direct = direct － 1
<@Ri> = <@Ri> － 1
DPTR = DPTR － 1
B:A = A × B
A = INT (A/B)
B = MOD (A/B)
Decimal adjust ACC
1
2
1
2
1
2
1
1
2
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
4
4
1
1
A .AND. Rn
A .AND. direct
A .AND. <@Ri>
A .AND. #data
direct .AND. A
direct .AND. #data
A .OR. Rn
A .OR. direct
A .OR. <@Ri>
1
2
1
2
2
3
1
2
1
1
1
1
1
1
2
1
1
1
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
13
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
ORL
A,#data
ORL
direct,A
ORL
direct,#data
XRL
A,Rn
XRL
A,direct
XRL
A,@Ri
XRL
A,#data
XRL
direct,A
XRL
direct,#data
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP
A
Data Transfers Instructions
MOV
A,Rn
MOV
A,direct
MOV
A,@Ri
MOV
A,#data
MOV
Rn,A
MOV
Rn,direct
MOV
Rn,#data
MOV
direct,A
MOV
direct,Rn
MOV
direct,direct
MOV
direct,@Ri
MOV
direct,#data
MOV
@Ri,A
MOV
@Ri,direct
MOV
@Ri,#data
MOV
DPTR,#data16
MOVC
A,@A+DPTR
MOVC
A,@A+PC
MOVX
A,@Ri
MOVX
A,@DPTR
MOVX
@Ri,A
MOVX
@DPTR,A
PUSH
direct
POP
direct
XCH
A,Rn
XCH
A,direct
XCH
A,@Ri
XCHD
A,@Ri
Boolean Instructions
CLR
C
CLR
bit
SETB
C
SETB
bit
CPL
C
CPL
bit
ANL
C,bit
ANL
C,/bit
ORL
C,bit
ORL
C,/bit
MOV
C,bit
MOV
bit,C
JC
rel
JNC
rel
JB
bit,rel
JNB
bit,rel
JBC
bit,rel
Jump Instructions
ACALL
addr11
LCALL
addr16
A .OR. #data
direct .OR. A
direct .OR. #data
A .XOR. Rn
A .XOR. direct
A .XOR. <@Ri>
A .XOR. #data
direct .XOR. A
direct .XOR. #data
A=0
A = /A
Rotate ACC Left 1 bit
Rotate Left through Carry
Rotate ACC Right 1 bit
Rotate Right through Carry
Swap Nibbles in A
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
A = Rn
A = direct
A = <@Ri>
A = #data
Rn = A
Rn = direct
Rn = #data
direct = A
direct = Rn
direct = direct
direct = <@Ri>
direct = #data
<@Ri> = A
<@Ri> = direct
<@Ri> = #data
DPTR = #data16
A = code memory[A+DPTR]
A = code memory[A+PC]
A = external memory[Ri] (8-bits address)
A = external memory[DPTR] (16-bits address)
external memory[Ri] = A (8-bits address)
external memory[DPTR] = A (16-bits address)
INC SP: MOV “@’SP’, < direct >
MOV < direct >, “@SP”: DEC SP
ACC and < Rn > exchange data
ACC and < direct > exchange data
ACC and < Ri > exchange data
ACC and @Ri exchange low nibbles
1
2
1
2
1
2
2
2
2
3
2
2
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
1
1
2
1
1
2
2
2
1
1
2
1
2
2
2
2
2
2
2
2
2
1
1
1
1
C=0
bit = 0
C=1
bit = 1
C = /C
bit = /bit
C = C .AND. bit
C = C .AND. /bit
C = C .OR. bit
C = C .OR. /bit
C = bit
bit = C
Jump if C= 1
Jump if C= 0
Jump if bit = 1
Jump if bit = 0
Jump if C = 1
1
2
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
1
1
1
1
1
1
2
2
2
2
1
2
2
2
2
2
2
Call Subroutine only at 2k bytes Address
Call Subroutine in max 64K bytes Address
2
3
2
2
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
14
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
RET
RETI
AJMP
LJMP
SJMP
JMP
JZ
JNZ
CJNE
CJNZ
CJNZ
CJNZ
DJNZ
DJNZ
NOP
addr11
addr16
rel
@A+DPTR
rel
rel
A, direct,rel
A, #data,rel
Rn, #data,rel
@Ri, #data,rel
Rn,rel
direct,rel
Return from subroutine
Return from interrupt
Jump only at 2k bytes Address
Jump to max 64K bytes Address
Jump on at 256 bytes
Jump to A+ DPTR
Jump if A = 0
Jump if A ≠ 0
Jump if A ≠ < direct >
Jump if A ≠ < #data >
Jump if Rn ≠ < #data >
Jump if @Ri ≠ < #data >
Decrement and jump if Rn not zero
Decrement and jump if direct not zero
No Operation
1
1
2
3
2
1
2
2
3
3
3
3
2
3
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bits free-running counter that generate reset signal if the counter overflows.
The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing
software dead loop or runaway. The WDT function can help user software recover form abnormal software condition.
The WDT is different from Timer0, Timer1 of general 8051. To prevent a WDT reset can be done by software
periodically clearing the WDT counter.
The SM8951B WDT has selectable divider input for the time base source clock. To select the divider input, the
setting of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bits counter
starts to count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when
overflows. The WDTE bit will be cleared to 0 automatically when SM8951B been reset, either hardware reset or
WDT reset.
To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bits
counter and let the counter re-start to count from the beginning.
Watch Dog Timer Registers- WDT Control Register
WDTC ($9F)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
WDTE
Unused
CLEAR
Unused
Unused
PS2
PS1
PS0
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer clear bit
If set the CLEAR bit, Watch Dog Timer will be re-start. then this bit will be clear automaticlly .
PS2~PS0: Clock sourer divider bit
PS [2:0]
Divider (OSC in) Time Period (ms) @40MHZ
000
8
13.1
001
16
26.21
010
32
52.42
011
64
104.8
100
128
209.71
101
256
419.43
110
512
838.86
111
1024
1677.72
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
15
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Watch Dog Timer Register - System Control Register
SCONF ($BFH)
Bit7
WDR
Bit6
Unused
Bit5
Unused
Bit4
Unused
Bit3
Unused
Bit2
Unused
Bit1
Unused
Bit0
ALEI
WDR : Watch Dog Timer Reset Flag. When system reset by Watch Dog Timer overflow, WDR will be set to 1.
ALEI : ALE output inhibit bit. It can reduce EMI.
The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened.
Reduce EMI Function
The SM8951B allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This
function will inhibit the clock signal in Fosc/6 Hz output to the ALE pin. This function is available when there is no
external program memory or no external data RAM in the system.
Application Reference
Valid for SM8951B
X'tal
C1
C2
R
3MHz
6MHz
9MHz
12MHz
30 pF
30 pF
open
30 pF
30 pF
open
30 pF
30 pF
open
22 pF
22 pF
open
X'tal
C1
C2
R
16MHz
25MHz
33MHz
40MHz
22 pF
22 pF
open
15 pF
15 pF
5 pF
5 pF
2 pF
2 pF
62KΩ
6.8KΩ
4.7KΩ
Note:
Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each
crystal or ceramic resonator has its own characteristics.
User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
XI
X'tal
SM8951B
R
X2
C1
C2
Power Saving Mode
The SM8951B has several features that help the user to control the power consumption of the device. The powers
saving features are basically the Power Down mode, Economy mode and the Idle mode of operation.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
16
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
Idle Mode:
The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the idle bit is the
last instruction that will be executed before the device goes into Idle Mode. In the Idle Mode, the clock to the CPU is
halted, but not to the Interrupt, Timer and Serial port blocks. This forces the CPU state to be frozen; the Program
counter, the Stack Pointer, the Program Status Word, the Accumulator and the other registers hold their contents. The
ALE and PSEN pins are held high during the idle state. The port pins hold the logical states they had at the time idle
was activated. The idle mode can be terminated in two ways. Since the interrupt controller is still active, the activation
of any enabled interrupt can wake up the processor. This will automatically clear the idle bit, terminate the idle mode,
and the Interrupt Service Routine (ISR) will be executed. After the ISR, execution of the program will continue from
the instruction that put the device into idle mode.
The Idle mode can also be exited by activating the reset. The device can be put into reset either applying a high on the
external RST pin or a Power on reset condition. The external reset pin has to be held high for at least two machine
cycles to be recognized as a valid reset. In the reset condition the program counter is reset to 0000H and all the SFRs
are set to the reset condition. Since the clock is already running there is no delay and execution start immediately.
When the SM8951B is exiting from an idle mode with a reset, the instruction following the one that put the device
into idle mode is not executed. So there is no danger of unexpected writes.
Power Down Mode:
The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does this will be the
last instruction to be executed before the device goes into Power Down mode. In the Power Down mode, all the
clocks are stopped and the device comes to a halt. All activity is completely stopped and the power consumption is
reduced to the lowest possible value. In this state the ALE and PSEN pins are pull low. The port pins output the
values held by their respective SFRs.
The status of external pins during Idle and Power Down:
Mode
Idle
Idle
Power Down
Power Down
Program
Memory
Internal
External
Internal
External
ALE
/PSEN
PORT0
PORT1
PORT2
PORT3
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Data
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
17
06/2009
SyncMOS Technologies International, Inc.
SM8951B
8-Bits Micro-controller
With4KBFlashROM&128bytesRAM embedded
MCU writer list
Company
Advantech
7F, No.98, Ming-Chung Rd., Shin-Tien City,
Taipei, Taiwan, ROC
Web site:
http://www.aec.com.tw
Contact info
Tel:02-22182325
Fax:02-22182435
E-mail:
[email protected]
Programmer Model Number
Lab Tool - 48XP/UXP
Lab Tool – 848/848XP
Hi-Lo
4F.,No.18,Lane 79,Rueiguang
Rd.,Neihu,Taipei,Taiwan R.O.C.
Web site:
http://www.hilosystems.com.tw
Tel: 02-87923301
Fax:02-87923285
E-mail:
[email protected]
All - 100 series
Leap
6th F1-4, Lane 609,
Chunghsin Rd., Sec. 5, Sanchung, Taipei ,
Taiwan, ROC
Web site:
http://www.leap.com.tw
Tel: 886-2-29991860
Fax:02-29990015
E-mail:
[email protected]
Leap-48
Xeltek Electronic Co., Ltd
Bldg 6-31 Meizhiguo garden, #2 Jiangjun
Ave., Jiangning, Nanjing, China 211100
Web site:
http://www.xeltek-cn.com
Tel: + 86-25-52765201,
E-mail:
[email protected]
[email protected]
Superpro 280U
Superpro 580U
Superpro 3000U
Superpro 9000U
Guangzhou Zhiyuan Electronic Co.,Ltd
Floor 2,No.7 building,Huangzhou Industrial
Estate,Chebei Road,Tianhe
district,Guangzhou,China 510660
Web site:
http://www.embedtools.com/
TEL: +86-20-28872449
E-mail:
[email protected]
SmartPRO 5000U/X8
TianJin Weilei technology ltd
Rm 357,Venturetech Center,12 Keyan West
Road Nankai District,Tianjin,P.R.C, 300192
Web site:
http://www.weilei.com.cn/
TEL: + 86-22-87891218#801
E-mail:
[email protected]
[email protected]
VP-890;VP-980;VP-880;VP-680
VP-480;VP-380;VP-280;VP-190
GuangZhou Chang Xingjinggong
Technology Development Co ., Ltd.
Room 102 , No.167 , CuiJing street ,
ChangXing road , TianHe district ,
GuangZhou.
Web site:
http://www.top2048.com/
TEL: + 86-20-61391469
E-mail:
[email protected]
TOP-2007
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M022Ver:BSM8951B
18
06/2009