CY26580 PacketClock™ Network Applications Clock Features Benefits • Integrated phase-locked loop (PLL) • Low-jitter, high-accuracy outputs • 3.3V operation • Internal PLL with precision operation • Meets critical timing requirements in complex system designs • Enables application compatibility Frequency Table Part Number Outputs Input Frequency Output Frequencies CY26580-1 2 125MHz or 25-MHz driven 100 MHz, 133.33 MHz Logic Block Diagram CLK Q OSC. Φ VCO OUTPUT MULTIPLEXER AND DIVIDERS P 133.33 MHz 100 MHz PLL SEL_25 SEL_CLK VDD VDD GND GND Pin Configuration CY26580 20-pin SSOP (QSOP) NC 1 20 NC NC 2 19 CLK 3 18 VDD 4 17 SEL_CLK NC 100 MHz NC GND 5 16 VDD 6 15 NC NC 7 NC 8 14 13 GND NC NC 9 10 133 MHz 12 11 NC SEL_25 Input Select Options SEL_25 SEL_CLK X 0 Input Type 0 1 Driven 125 1 1 Driven 25 Cypress Semiconductor Corporation Document #: 38-07536 Rev. *B Input Frequency CLK1 CLK2 Unit 133.33 100 MHz 133.33 100 MHz Do not use • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 03, 2004 CY26580 Pin Description Pin Name Pin Number Pin Description NC 1 No Connect NC 2 No Connect CLK 3 Reference Input VDD 4 Voltage Supply NC 5 No Connect GND 6 Ground NC 7 No Connect NC 8 No Connect NC 9 No Connect 133 MHz 10 133.33-MHz Clock Output SEL_25 11 Reference Frequency Select Input; 0 = 125 MHz, 1 = 25 MHz, weak internal pull-up NC 12 No Connect NC 13 No Connect GND 14 Ground NC 15 No Connect VDD 16 Voltage Supply 100 MHz 17 100-MHz Clock Output NC 18 No Connect SEL_CLK 19 Reference Select Input; Set to 1 = Driven, weak internal pull-up NC 20 No Connect Document #: 38-07536 Rev. *B Page 2 of 5 CY26580 Absolute Maximum Conditions[1] Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj = 125°C................................> 10 years Supply Voltage (VDD) ........................................–0.5 to +7.0V Package Power Dissipation...................................... 350 mW DC Input Voltage........................................ –0.5V to VDD+0.5 ESD (Human Body Model) MIL-STD-883.................... 2000V Storage Temperature (Non-condensing)..... –55°C to +125°C Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit VDD Supply Voltage 3.14 3.3 3.47 V TA, I-grade Ambient Temperature, Industrial –40 – 85 °C CLOAD Max. Load Capacitance – – 15 pF fREF Reference Frequency – 125, 25 – MHz DC Electrical Specifications Parameter[2] Description Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 – mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 – mA IIH Input High Current VIH = VDD – 5 10 µA IIL Input Low Current VIL = 0V – – 50 µA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – – VDD VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3 VDD IDD Supply Current VDD Current, no load – 35 50 mA RUP Pull-up resistor on Inputs VDD = 3.14 to 3.47V, measured VIN = 0V – 100 150 kΩ AC Electrical Specifications Parameter[2] Ferror Description Conditions Frequency Error Min. Typ. All clocks Max. Unit 0 ppm DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 2 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 2 V/ns t9 Clock Jitter CLK1, CLK2 Peak-Peak period jitter – 100 – ps t10 PLL Lock Time – – 3 ms Test and Measurement Set-up VDDs Outputs 0.1 µF DUT CLOAD GND Notes: 1. Above which the useful life may be impaired. For user guidelines, not tested. 2. Guaranteed by characterization, not 100% tested. Document #: 38-07536 Rev. *B Page 3 of 5 CY26580 Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t4 t3 V DD 80% of V DD 20% of VDD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY26580OI–1 20-pin SSOP (QSOP) Industrial 3.3V CY26580OI–1T 20-pin SSOP (QSOP) – Tape and Reel Industrial 3.3V Package Drawing and Dimensions 20-lead QSOP O201 51-85054-*B PacketClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07536 Rev. *B Page 4 of 5 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. CY26580 Document History Page Document Title: CY26580 PacketClock™ Network Applications Clock Document #: 38-07536 Rev. *B REV. ECN NO. Issue Date Orig. of Change ** 127357 06/17/03 RGL *A 128564 09/12/03 IJA *B 216828 See ECN RGL Document #: 38-07536 Rev. *B Description of Change New Data Sheet Change pin 1 to NC and pin 3 to CLK Removed Preliminary Page 5 of 5