ST
Sitronix
ST7626
65K Color Dot Matrix LCD Controller/Driver
1. INTRODUCTION
The ST7626 is a driver & controller LSI for 65K color graphic dot-matrix liquid crystal display systems. It generates 294
Segment and 68 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral
Interface (SPI) or 8-bit/16-bit parallel display data and stores in an on-chip display data RAM. It performs display data RAM
read/write operation with no external operating clock to minimize power consumption. In addition, because it contains
power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Driver Output Circuits
♦ 294 Segment Outputs / 68 Common Outputs
Applicable Duty Ratios
♦ Various Partial Display
♦ Partial Window Moving & Data Scrolling
♦ On-chip Voltage Converter (x2, x3, x4, x5) with internal
booster capacitors.
♦ Extremely Few Outsider Compoment. (Minimum required
outsider compoments: One Capacitor).
♦ On-chip Voltage Regulator (Temperature gradient =
-0.065%/°C)
Gray-Scale Display
♦ On-chip Electronic Contrast Control Function (406 steps)
♦ 4FRC & 31 PWM function circuit to display
♦ Voltage Follower (LCD bias: 1/5 to 1/12)
♦ 64 gray-scale display.
Operating Voltage Range
On-chip Display Data RAM
♦ Supply Digital Voltage (VDD, VDD1): 1.8 to 3.3V
♦ Capacity: 98 x 68 x 16 =106,624 bits
♦ Supply Analog Voltage (VDD2, VDD3, VDD4, VDD5): 2.4
♦ 4K colors (RGB)=(444) mode
to 3.3V
♦ 65K colors (RGB)=(565) mode
♦ LCD Driving Voltage (VOP = V0 - VSS): 3.76V to 18V
♦ Truncated 262K colors (RGB)=(666) mode
♦ The suggested value of V0 is under 11 V with bias =1/9.
♦ Truncated 16M colors (RGB)=(888) mode
LCD Driving Voltage (EEPROM)
Microprocessor Interface
♦ Contrast Adjustment Value is stored in the Built-In
♦ 8/16-bit parallel bi-directional interface with 6800-series
EEPROM for better display quility.
LCM Performance Adjustment (EEPROM)
or 8080-series
♦ 4-line serial interface (4-line-SIF)
♦ 3-line serial interface (3-line-SIF)
♦ Adjustment Value for best Display Performance is stored
in the Built-In EEPROM.
On-chip Low Power Analog Circuit
Package Type
♦ On-chip Oscillator Circuit
♦ Application for COG
ST7626
Ver 1.5
6800 , 8080 ,4-Line , 3-Line interface
1/94
2007/01/20
ST7626
3. ST7626 Pad Arrangement (COG)
Chip Size : 9,717 um x 1,352.7 um
Bump Pitch :
PAD NO.1~328, 412~445 : 31 um (COM/SEG)
PAD NO.329~341, 342~411, : 110 um (I/O)
PAD NO.341~342 : 114.7 um (I/O)
Bump Size :
PAD NO.1~328, 412~445 : 16 um(x) X 118 um(y)
PAD NO.329~411 : 95 um(x) X 50 um(y)
Bump Height : 15 um
Chip Thickness : 400 um
x
y
20 um
20 um
52 um
(x , y) =
(4762.7 um,580.35 um)
52 um
20 um
(x , y) =
(-4778.7 um,596.35 um)
52 um
20 um
52 um
Ver 1.5
2/94
2007/01/20
ST7626
4. Pad Center Coordinates
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
001
SEG[293]
4541.5
545.35
034
SEG[260]
3518.5
545.35
002
SEG[292]
4510.5
545.35
035
SEG[259]
3487.5
545.35
003
SEG[291]
4479.5
545.35
036
SEG[258]
3456.5
545.35
004
SEG[290]
4448.5
545.35
037
SEG[257]
3425.5
545.35
005
SEG[289]
4417.5
545.35
038
SEG[256]
3394.5
545.35
006
SEG[288]
4386.5
545.35
039
SEG[255]
3363.5
545.35
007
SEG[287]
4355.5
545.35
040
SEG[254]
3332.5
545.35
008
SEG[286]
4324.5
545.35
041
SEG[253]
3301.5
545.35
009
SEG[285]
4293.5
545.35
042
SEG[252]
3270.5
545.35
010
SEG[284]
4262.5
545.35
043
SEG[251]
3239.5
545.35
011
SEG[283]
4231.5
545.35
044
SEG[250]
3208.5
545.35
012
SEG[282]
4200.5
545.35
045
SEG[249]
3177.5
545.35
013
SEG[281]
4169.5
545.35
046
SEG[248]
3146.5
545.35
014
SEG[280]
4138.5
545.35
047
SEG[247]
3115.5
545.35
015
SEG[279]
4107.5
545.35
048
SEG[246]
3084.5
545.35
016
SEG[278]
4076.5
545.35
049
SEG[245]
3053.5
545.35
017
SEG[277]
4045.5
545.35
050
SEG[244]
3022.5
545.35
018
SEG[276]
4014.5
545.35
051
SEG[243]
2991.5
545.35
019
SEG[275]
3983.5
545.35
052
SEG[242]
2960.5
545.35
020
SEG[274]
3952.5
545.35
053
SEG[241]
2929.5
545.35
021
SEG[273]
3921.5
545.35
054
SEG[240]
2898.5
545.35
022
SEG[272]
3890.5
545.35
055
SEG[239]
2867.5
545.35
023
SEG[271]
3859.5
545.35
056
SEG[238]
2836.5
545.35
024
SEG[270]
3828.5
545.35
057
SEG[237]
2805.5
545.35
025
SEG[269]
3797.5
545.35
058
SEG[236]
2774.5
545.35
026
SEG[268]
3766.5
545.35
059
SEG[235]
2743.5
545.35
027
SEG[267]
3735.5
545.35
060
SEG[234]
2712.5
545.35
028
SEG[266]
3704.5
545.35
061
SEG[233]
2681.5
545.35
029
SEG[265]
3673.5
545.35
062
SEG[232]
2650.5
545.35
030
SEG[264]
3642.5
545.35
063
SEG[231]
2619.5
545.35
031
SEG[263]
3611.5
545.35
064
SEG[230]
2588.5
545.35
032
SEG[262]
3580.5
545.35
065
SEG[229]
2557.5
545.35
033
SEG[261]
3549.5
545.35
066
SEG[228]
2526.5
545.35
Ver 1.5
3/94
2007/01/20
ST7626
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
067
SEG[227]
2495.5
545.35
102
SEG[192]
1410.5
545.35
068
SEG[226]
2464.5
545.35
103
SEG[191]
1379.5
545.35
069
SEG[225]
2433.5
545.35
104
SEG[190]
1348.5
545.35
070
SEG[224]
2402.5
545.35
105
SEG[189]
1317.5
545.35
071
SEG[223]
2371.5
545.35
106
SEG[188]
1286.5
545.35
072
SEG[222]
2340.5
545.35
107
SEG[187]
1255.5
545.35
073
SEG[221]
2309.5
545.35
108
SEG[186]
1224.5
545.35
074
SEG[220]
2278.5
545.35
109
SEG[185]
1193.5
545.35
075
SEG[219]
2247.5
545.35
110
SEG[184]
1162.5
545.35
076
SEG[218]
2216.5
545.35
111
SEG[183]
1131.5
545.35
077
SEG[217]
2185.5
545.35
112
SEG[182]
1100.5
545.35
078
SEG[216]
2154.5
545.35
113
SEG[181]
1069.5
545.35
079
SEG[215]
2123.5
545.35
114
SEG[180]
1038.5
545.35
080
SEG[214]
2092.5
545.35
115
SEG[179]
1007.5
545.35
081
SEG[213]
2061.5
545.35
116
SEG[178]
976.5
545.35
082
SEG[212]
2030.5
545.35
117
SEG[177]
945.5
545.35
083
SEG[211]
1999.5
545.35
118
SEG[176]
914.5
545.35
084
SEG[210]
1968.5
545.35
119
SEG[175]
883.5
545.35
085
SEG[209]
1937.5
545.35
120
SEG[174]
852.5
545.35
086
SEG[208]
1906.5
545.35
121
SEG[173]
821.5
545.35
087
SEG[207]
1875.5
545.35
122
SEG[172]
790.5
545.35
088
SEG[206]
1844.5
545.35
123
SEG[171]
759.5
545.35
089
SEG[205]
1813.5
545.35
124
SEG[170]
728.5
545.35
090
SEG[204]
1782.5
545.35
125
SEG[169]
697.5
545.35
091
SEG[203]
1751.5
545.35
126
SEG[168]
666.5
545.35
092
SEG[202]
1720.5
545.35
127
SEG[167]
635.5
545.35
093
SEG[201]
1689.5
545.35
128
SEG[166]
604.5
545.35
094
SEG[200]
1658.5
545.35
129
SEG[165]
573.5
545.35
095
SEG[199]
1627.5
545.35
130
SEG[164]
542.5
545.35
096
SEG[198]
1596.5
545.35
131
SEG[163]
511.5
545.35
097
SEG[197]
1565.5
545.35
132
SEG[162]
480.5
545.35
098
SEG[196]
1534.5
545.35
133
SEG[161]
449.5
545.35
099
SEG[195]
1503.5
545.35
134
SEG[160]
418.5
545.35
100
SEG[194]
1472.5
545.35
135
SEG[159]
387.5
545.35
101
SEG[193]
1441.5
545.35
136
SEG[158]
356.5
545.35
Ver 1.5
4/94
2007/01/20
ST7626
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
137
SEG[157]
325.5
545.35
172
SEG[122]
-759.5
545.35
138
SEG[156]
294.5
545.35
173
SEG[121]
-790.5
545.35
139
SEG[155]
263.5
545.35
174
SEG[120]
-821.5
545.35
140
SEG[154]
232.5
545.35
175
SEG[119]
-852.5
545.35
141
SEG[153]
201.5
545.35
176
SEG[118]
-883.5
545.35
142
SEG[152]
170.5
545.35
177
SEG[117]
-914.5
545.35
143
SEG[151]
139.5
545.35
178
SEG[116]
-945.5
545.35
144
SEG[150]
108.5
545.35
179
SEG[115]
-976.5
545.35
145
SEG[149]
77.5
545.35
180
SEG[114]
-1007.5 545.35
146
SEG[148]
46.5
545.35
181
SEG[113]
-1038.5 545.35
147
SEG[147]
15.5
545.35
182
SEG[112]
-1069.5 545.35
148
SEG[146]
-15.5
545.35
183
SEG[111]
-1100.5 545.35
149
SEG[145]
-46.5
545.35
184
SEG[110]
-1131.5 545.35
150
SEG[144]
-77.5
545.35
185
SEG[109]
-1162.5 545.35
151
SEG[143]
-108.5
545.35
186
SEG[108]
-1193.5 545.35
152
SEG[142]
-139.5
545.35
187
SEG[107]
-1224.5 545.35
153
SEG[141]
-170.5
545.35
188
SEG[106]
-1255.5 545.35
154
SEG[140]
-201.5
545.35
189
SEG[105]
-1286.5 545.35
155
SEG[139]
-232.5
545.35
190
SEG[104]
-1317.5 545.35
156
SEG[138]
-263.5
545.35
191
SEG[103]
-1348.5 545.35
157
SEG[137]
-294.5
545.35
192
SEG[102]
-1379.5 545.35
158
SEG[136]
-325.5
545.35
193
SEG[101]
-1410.5 545.35
159
SEG[135]
-356.5
545.35
194
SEG[100]
-1441.5 545.35
160
SEG[134]
-387.5
545.35
195
SEG[99]
-1472.5 545.35
161
SEG[133]
-418.5
545.35
196
SEG[98]
-1503.5 545.35
162
SEG[132]
-449.5
545.35
197
SEG[97]
-1534.5 545.35
163
SEG[131]
-480.5
545.35
198
SEG[96]
-1565.5 545.35
164
SEG[130]
-511.5
545.35
199
SEG[95]
-1596.5 545.35
165
SEG[129]
-542.5
545.35
200
SEG[94]
-1627.5 545.35
166
SEG[128]
-573.5
545.35
201
SEG[93]
-1658.5 545.35
167
SEG[127]
-604.5
545.35
202
SEG[92]
-1689.5 545.35
168
SEG[126]
-635.5
545.35
203
SEG[91]
-1720.5 545.35
169
SEG[125]
-666.5
545.35
204
SEG[90]
-1751.5 545.35
170
SEG[124]
-697.5
545.35
205
SEG[89]
-1782.5 545.35
171
SEG[123]
-728.5
545.35
206
SEG[88]
-1813.5 545.35
Ver 1.5
5/94
2007/01/20
ST7626
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
207
SEG[87]
-1844.5 545.35
242
SEG[52]
-2929.5 545.35
208
SEG[86]
-1875.5 545.35
243
SEG[51]
-2960.5 545.35
209
SEG[85]
-1906.5 545.35
244
SEG[50]
-2991.5 545.35
210
SEG[84]
-1937.5 545.35
245
SEG[49]
-3022.5 545.35
211
SEG[83]
-1968.5 545.35
246
SEG[48]
-3053.5 545.35
212
SEG[82]
-1999.5 545.35
247
SEG[47]
-3084.5 545.35
213
SEG[81]
-2030.5 545.35
248
SEG[46]
-3115.5 545.35
214
SEG[80]
-2061.5 545.35
249
SEG[45]
-3146.5 545.35
215
SEG[79]
-2092.5 545.35
250
SEG[44]
-3177.5 545.35
216
SEG[78]
-2123.5 545.35
251
SEG[43]
-3208.5 545.35
217
SEG[77]
-2154.5 545.35
252
SEG[42]
-3239.5 545.35
218
SEG[76]
-2185.5 545.35
253
SEG[41]
-3270.5 545.35
219
SEG[75]
-2216.5 545.35
254
SEG[40]
-3301.5 545.35
220
SEG[74]
-2247.5 545.35
255
SEG[39]
-3332.5 545.35
221
SEG[73]
-2278.5 545.35
256
SEG[38]
-3363.5 545.35
222
SEG[72]
-2309.5 545.35
257
SEG[37]
-3394.5 545.35
223
SEG[71]
-2340.5 545.35
258
SEG[36]
-3425.5 545.35
224
SEG[70]
-2371.5 545.35
259
SEG[35]
-3456.5 545.35
225
SEG[69]
-2402.5 545.35
260
SEG[34]
-3487.5 545.35
226
SEG[68]
-2433.5 545.35
261
SEG[33]
-3518.5 545.35
227
SEG[67]
-2464.5 545.35
262
SEG[32]
-3549.5 545.35
228
SEG[66]
-2495.5 545.35
263
SEG[31]
-3580.5 545.35
229
SEG[65]
-2526.5 545.35
264
SEG[30]
-3611.5 545.35
230
SEG[64]
-2557.5 545.35
265
SEG[29]
-3642.5 545.35
231
SEG[63]
-2588.5 545.35
266
SEG[28]
-3673.5 545.35
232
SEG[62]
-2619.5 545.35
267
SEG[27]
-3704.5 545.35
233
SEG[61]
-2650.5 545.35
268
SEG[26]
-3735.5 545.35
234
SEG[60]
-2681.5 545.35
269
SEG[25]
-3766.5 545.35
235
SEG[59]
-2712.5 545.35
270
SEG[24]
-3797.5 545.35
236
SEG[58]
-2743.5 545.35
271
SEG[23]
-3828.5 545.35
237
SEG[57]
-2774.5 545.35
272
SEG[22]
-3859.5 545.35
238
SEG[56]
-2805.5 545.35
273
SEG[21]
-3890.5 545.35
239
SEG[55]
-2836.5 545.35
274
SEG[20]
-3921.5 545.35
240
SEG[54]
-2867.5 545.35
275
SEG[19]
-3952.5 545.35
241
SEG[53]
-2898.5 545.35
276
SEG[18]
-3983.5 545.35
Ver 1.5
6/94
2007/01/20
ST7626
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
277
SEG[17]
-4014.5 545.35
312 COM[51] COM[33] -4727.7
-57.35
278
SEG[16]
-4045.5 545.35
313 COM[52] COM[31] -4727.7
-88.35
279
SEG[15]
-4076.5 545.35
314 COM[53] COM[29] -4727.7 -119.35
280
SEG[14]
-4107.5 545.35
315 COM[54] COM[27] -4727.7 -150.35
281
SEG[13]
-4138.5 545.35
316 COM[55] COM[25] -4727.7 -181.35
282
SEG[12]
-4169.5 545.35
317 COM[56] COM[23] -4727.7 -212.35
283
SEG[11]
-4200.5 545.35
318 COM[57] COM[21] -4727.7 -243.35
284
SEG[10]
-4231.5 545.35
319 COM[58] COM[19] -4727.7 -274.35
285
SEG[9]
-4262.5 545.35
320 COM[59] COM[17] -4727.7 -305.35
286
SEG[8]
-4293.5 545.35
321 COM[60] COM[15] -4727.7 -336.35
287
SEG[7]
-4324.5 545.35
322 COM[61] COM[13] -4727.7 -367.35
288
SEG[6]
-4355.5 545.35
323 COM[62] COM[11] -4727.7 -398.35
289
SEG[5]
-4386.5 545.35
324 COM[63] COM[9]
-4727.7 -429.35
290
SEG[4]
-4417.5 545.35
325 COM[64] COM[7]
-4727.7 -460.35
291
SEG[3]
-4448.5 545.35
326 COM[65] COM[5]
-4727.7 -491.35
292
SEG[2]
-4479.5 545.35
327 COM[66] COM[3]
-4727.7 -522.35
293
SEG[1]
-4510.5 545.35
328 COM[67] COM[1]
-4727.7 -553.35
294
SEG[0]
-4541.5 545.35
329
V0IN
-4510.0 -575.35
295 COM[34] COM[67] -4727.7 469.65
330
V0IN
-4400.0 -575.35
296 COM[35] COM[65] -4727.7 438.65
331
V0IN
-4290.0 -575.35
297 COM[36] COM[63] -4727.7 407.65
332
V0IN
-4180.0 -575.35
298 COM[37] COM[61] -4727.7 376.65
333
V0IN
-4070.0 -575.35
299 COM[38] COM[59] -4727.7 345.65
334
V0IN
-3960.0 -575.35
300 COM[39] COM[57] -4727.7 314.65
335
V0OUT
-3850.0 -575.35
301 COM[40] COM[55] -4727.7 283.65
336
V0OUT
-3740.0 -575.35
302 COM[41] COM[53] -4727.7 252.65
337
V1
-3630.0 -575.35
303 COM[42] COM[51] -4727.7 221.65
338
V2
-3520.0 -575.35
304 COM[43] COM[49] -4727.7 190.65
339
V3
-3410.0 -575.35
305 COM[44] COM[47] -4727.7 159.65
340
V4
-3300.0 -575.35
306 COM[45] COM[45] -4727.7 128.65
341
VREF
-3190.0 -575.35
307 COM[46] COM[43] -4727.7
97.65
342
CL
-3075.3 -575.35
308 COM[47] COM[41] -4727.7
66.65
343
CLS
-2965.3 -575.35
309 COM[48] COM[39] -4727.7
35.65
344
VSS
-2855.3 -575.35
310 COM[49] COM[37] -4727.7
4.65
345
VDD
-2745.3 -575.35
311 COM[50] COM[35] -4727.7
-26.35
346
A0
-2635.3 -575.35
Ver 1.5
7/94
2007/01/20
ST7626
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
347
RW_WR
-2525.3 -575.35
382
VSS
1324.7 -575.35
348
D0
-2415.3 -575.35
383
VSS
1434.7 -575.35
349
D1
-2305.3 -575.35
384
VSS2
1544.7 -575.35
350
D2
-2195.3 -575.35
385
VSS2
1654.7 -575.35
351
D3
-2085.3 -575.35
386
VSS2
1764.7 -575.35
352
D4
-1975.3 -575.35
387
VSS2
1874.7 -575.35
353
D5
-1865.3 -575.35
388
VSS2
1984.7 -575.35
354
D6
-1755.3 -575.35
389
VSS2
2094.7 -575.35
355
D7
-1645.3 -575.35
390
VSS2
2204.7 -575.35
356
D8
-1535.3 -575.35
391
VSS2
2314.7 -575.35
357
D9
-1425.3 -575.35
392
VSS4
2424.7 -575.35
358
D10
-1315.3 -575.35
393
VDD4
2534.7 -575.35
359
D11
-1205.3 -575.35
394
VDD3
2644.7 -575.35
360
D12
-1095.3 -575.35
395
VDD2
2754.7 -575.35
361
D13
-985.3
-575.35
396
VDD2
2864.7 -575.35
362
D14
-875.3
-575.35
397
VDD2
2974.7 -575.35
363
D15
-765.3
-575.35
398
VDD2
3084.7 -575.35
364
VSS
-655.3
-575.35
399
VDD2
3194.7 -575.35
365
VDD
-545.3
-575.35
400
VDD5
3304.7 -575.35
366
E_RD
-435.3
-575.35
401
VDD5
3414.7 -575.35
367
RST
-325.3
-575.35
402
VDD5
3524.7 -575.35
368
CSEL
-215.3
-575.35
403
TCAP
3634.7 -575.35
369
IF1
-105.3
-575.35
404
VLCDIN
3744.7 -575.35
370
IF2
4.7
-575.35
405
VLCDIN
3854.7 -575.35
371
IF3
114.7
-575.35
406
VLCDIN
3964.7 -575.35
372
VSS
224.7
-575.35
407
VLCDIN
4074.7 -575.35
373
VDD
334.7
-575.35
408
VLCDIN
4184.7 -575.35
374
SI
444.7
-575.35
409
VLCDIN
4294.7 -575.35
375
SCL
554.7
-575.35
410
VLCDOUT
4404.7 -575.35
376
/CS
664.7
-575.35
411
VLCDOUT
4514.7 -575.35
377
VDD
774.7
-575.35
412
COM[0]
COM[0] 4727.7 -553.35
378
VDD
884.7
-575.35
413
COM[1]
COM[2] 4727.7 -522.35
379
VDD1
994.7
-575.35
414
COM[2]
COM[4] 4727.7 -491.35
380
VSS1
1104.7 -575.35
415
COM[3]
COM[6] 4727.7 -460.35
381
VSS
1214.7 -575.35
416
COM[4]
COM[8] 4727.7 -429.35
Ver 1.5
8/94
2007/01/20
ST7626
PIN Name
PAD
No. CSEL=0 CSEL=1
X
Y
417
COM[5] COM[10] 4727.7 -398.35
418
COM[6] COM[12] 4727.7 -367.35
419
COM[7] COM[14] 4727.7 -336.35
420
COM[8] COM[16] 4727.7 -305.35
421
COM[9] COM[18] 4727.7 -274.35
422 COM[10] COM[20] 4727.7 -243.35
423 COM[11] COM[22] 4727.7 -212.35
424 COM[12] COM[24] 4727.7 -181.35
425 COM[13] COM[26] 4727.7 -150.35
426 COM[14] COM[28] 4727.7 -119.35
427 COM[15] COM[30] 4727.7
-88.35
428 COM[16] COM[32] 4727.7
-57.35
429 COM[17] COM[34] 4727.7
-26.35
430 COM[18] COM[36] 4727.7
4.65
431 COM[19] COM[38] 4727.7
35.65
432 COM[20] COM[40] 4727.7
66.65
433 COM[21] COM[42] 4727.7
97.65
434 COM[22] COM[44] 4727.7
128.65
435 COM[23] COM[46] 4727.7
159.65
436 COM[24] COM[48] 4727.7
190.65
437 COM[25] COM[50] 4727.7
221.65
438 COM[26] COM[52] 4727.7
252.65
439 COM[27] COM[54] 4727.7
283.65
440 COM[28] COM[56] 4727.7
314.65
441 COM[29] COM[58] 4727.7
345.65
442 COM[30] COM[60] 4727.7
376.65
443 COM[31] COM[62] 4727.7
407.65
444 COM[32] COM[64] 4727.7
438.65
445 COM[33] COM[66] 4727.7
469.65
Ver 1.5
9/94
2007/01/20
ST7626
5. BLOCK DIAGRAM
SEG0 TO SEG293
COM0 TO COM67
VDD1
VDD
V0IN
V1
V2
V3
V4
VSS
SEGMENT DRIVERS
DATA LATCHES
V/F
Circuit
FRC/PWM FUNCTION
CIRCUIT
V0OUT
V/R
Circuit
DISPLAY DATA RAM
(DDRAM)
[98 X 68 X 16]
CSEL
COMMON
OUTPUT
CONTROLLER
CIRCUIT
CL
RESET
OSCILLATOR
VLCDIN
VLCDOUT
VDD2
VDD3
VDD4
VDD5
VSS2
VSS4
COMMON DRIVERS
CLS
TIMING
GENERATOR
DISPLAY
ADDRESS
COUNTER
V/C
Circuit
VSS
ADDRESS COUNTER
EEPROM
DATA
REGISTER
INSTRUCTION
REGISTER
BUS
HOLDER
INSTRUCTION
DECODER
MPU INTERFACE(PARALLEL & SERIAL)
VSS1
10/94
TCAP
D0 to D15
SI
SCL
E_RD
RW_WR
A0
/CS
/RST
IF3
IF2
IF1
Ver 1.5
2007/01/20
ST7626
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Name
I/O
Description
VDD
Supply
Power supply for logic circuit
VDD1
Supply
Power supply for OSC circuit
VDD2
Supply
Power supply for Booster Circuit
VDD3
Supply
Power supply for LCD.
VDD4
Supply
Power supply for LCD.
VDD5
Supply
Power supply for LCD.
VSS
Supply
Ground for logic circuit. Ground system should be connected together.
VSS1
Supply
Ground for OSC circuit. Ground system should be connected together.
VSS2
Supply
Ground for Booster Circuit. Ground system should be connected together.
VSS4
Supply
Ground for LCD. Ground system should be connected together.
6.2 LCD Power Supply Pins
VLCDOUT
O
VLCDIN
I
If the internal voltage generator is used, the VLCDIN & VLCDOUT must be connected together.
If an external supply is used, this pin must be left open.
An external LCD supply voltage can be supplied using the VLCDIN pin. In this case, VLCDOUT has to
be left open, and the internal voltage generator has to be programmed to zero. (SET register VC=0)
LCD driver supply voltages
V0in & V0out should be connected together.
V0IN
Voltages should have the following relationship;
V0OUT
V1
V2
V0 ( V0in ) ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ VSS.
I/O
When the internal power circuit is active, these voltages are generated as following table according
to the state of LCD bias.
V3
V4
LCD bias
V1
V2
V3
V4
1/N bias
(N-1) / N x V0
(N-2) / N x V0
(2/N) x V0
(1/N) x V0
NOTE: N = 5 to 12
6.3 SYSTEM CONTROL
Name
I/O
CLS
I
CL
I/O
Description
When using internal clock oscillator, connect CLS to VDD.
When using external clock oscillator, connect CLS to VSS.
When using internal clock oscillator, it’s oscillator output.
When using external clock oscillator, it’s clock input.
Select Common output direction.
CSEL
I
CSEL=”L”, COM0~COM33 is in one side, COM34~COM67 is in the opposite side.
CSEL=”H”, COM2n(even number) is in the one side, COM2n+1 (odd number) is in the opposite side.
TCAP
I/O
Test pin. Left it opens.
VREF
O
Reference voltage output for monitor only. Left it opened. Do NOT connect this PAD.
Ver 1.5
11/94
2007/01/20
ST7626
6.4 MICROPROCESSOR INTERFACE
Name
I/O
RST
I
Description
Reset input pin. When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input
IF[3:1]
I
IF1
IF2
IF3
MPU interface type
H
H
H
80 series 16-bit parallel
H
H
L
80 series 8-bit parallel
H
L
L
68 series 16-bit parallel
L
H
H
68 series 8-bit parallel
L
L
H
9-bit serial (3 line)
L
L
L
8-bit serial (4 line)
Chip select input pins
/CS
I
Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D15
become high impedance.
Register select input pin
A0
I
A0 = "H": D0 to D15 or SI are display data
A0 = "L": D0 to D15 or SI are control data
In 3-line interface not let it floating, connect it to ”H” level.
Read / Write execution control pin
MPU type
RW_WR
Description
Read / Write control input pin
6800-series
RW_WR
RW
RW = “H” : read
I
RW = “L” : write
Write enable clock input pin
8080-series
/WR
The data on D0 to D15 are latched at the
rising edge of the /WR signal.
When in the serial interface, connect it to ”H” level.
Read / Write execution control pin
MPU Type
E_RD
Description
Read / Write control input pin
RW = “H”: When E is “H”, D0 to D15 are in an output
E_RD
I
6800-series
E
status.
RW = “L”: The data on D0 to D15 are latched at the
falling edge of the E signal.
8080-series
/RD
Read enable clock input pin
When /RD is “L”, D0 to D15 are in an output status.
When in the serial interface, connect it to ”H” level .Signals Explaination Chart：see page 17
Ver 1.5
12/94
2007/01/20
ST7626
They connect to the standard 8-bit or 16 bit MPU bus via the 8/16 –bit bi-directional bus.
When the following interface is selected and the /CS pin is high, the following pins become high
D15 to D0
I/O
impedance.
1.
In 8-bit parallel: D15-D8 pins are in the state of high impedance should connect to ”H” level.
2.
In Serial interface: D15-D0 pins are in the state of high impedance should connect to ”H”
level.
SI
I
This pin is used to input serial data when the serial interface is selected.(3 line and 4 line)
When not use connect it to ”H” level.
This pin is used to input serial clock when the serial interface is selected.
SCL
I
The data is converted in the rising edge. (3 line and 4 line)
When not use connect it to ”H” level.
NOTE:
Microprocessor interfece pins should not be floating in any operation mode.
6.5 LCD DRIVER OUTPUTS
Name
I/O
Description
LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.
SEG0
to
O
SEG293
Display data
M (Internal)
H
Segment driver output voltage
Normal display
Reverse display
H
V0
V2
H
L
VSS
V3
L
H
V2
V0
L
L
V3
VSS
VSS
VSS
Sleep-In mode
LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.
COM0
to
COM67
O
Scan data
M (Internal)
Common driver output voltage
H
H
VSS
H
L
V0
L
H
V1
L
L
V4
Sleep-In mode
Ver 1.5
VSS
13/94
2007/01/20
ST7626
ST7626 I/O PIN ITO Resister Limitation
Pin Name
ITO Resister
TCAP, CL
Floating
IF[3:1],CLS,CSEL
No Limitation
VDD, VDD1~VDD5, VSS,VSS1,VSS2,VSS4,VLCDIN, VLCDOUT
<100Ω
V0IN, V0OUT, V1, V2, V3, V4
<100Ω
A0, E_RD, RW_WR, /CS, D0 …D15, SCL, SI
<1KΩ
RST
<10KΩ
NOTE:
Make sure that the ITO resistance of COM0 ~ COM67 is equal, and so is it of SEG0 ~ SEG293.
Vref sould not connect to external. Therefore, no ITO resistance value listed.
Ver 1.5
14/94
2007/01/20
ST7626
7. FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
/CS pin is for chip selection. The ST7626 can function with an MPU when /CS is "L". In case of serial interface, the internal
shift register and the counter are reset.
7.1.1 Selecting Parallel / Serial Interface
ST7626 has six types of interface with an MPU, which are two serial and four parallel interfaces. This parallel or serial
interface is determined by IF pin as shown in table 7.1.1.
Table 7.1.1 Parallel / Serial Interface Mode
I/F Mode
IF1 IF2 IF3
H
H
H
H
H
L
H
L
L
L
H
H
L
L
L
L
L
H
I/F Description
80 serial 16-bit parallel
80 serial 8-bit parallel
68 serial 16-bit parallel
68 serial 8-bit parallel
8-bit SPI mode (4 line)
9-bit SPI mode (3 line)
/CS
/CS
/CS
/CS
/CS
/CS
/CS
A0
A0
A0
A0
A0
A0
--
E_RD
/RD
/RD
E
E
---
Pin Assignment
RW_WR D15 to D8
/WR
D15 ~ D8
/WR
-R/W
D15 ~ D8
R/W
------
D7 to D0
D7 ~ D0
D7 ~ D0
D7 ~ D0
D7 ~ D0
---
SI
----SI
SI
SCL
----SCL
SCL
NOTE: When these pins are set to any other combination, A0, E_RD and RW_WR inputs are disabled and D0 to D15 are
to be high impedance.
7.1.2 8-bit or 16-bit Parallel Interface
The ST7626 identifies the type of the data bus signals according to the combination of A0, /RD (E) and /WR (W/R) signals,
as shown in table 7.1.2.
Table 7.1.2 Parallel Data Transfer
Common
6800-series
8080-series
Description
A0
R/W
E
/RD
/WR
H
H
H
L
H
Display data read out
H
L
H
H
L
Display data write
L
H
H
L
H
Register status read
L
L
H
H
L
Writes to internal register (instruction)
Ver 1.5
15/94
2007/01/20
ST7626
Figure 7.1.2 Parallel Data Transfer Example Chart
Relation between Data Bus and Gradation Data
ST7626 offers 4096 color display, 65K color display, truncated 262K color display, and truncated 16M color display.
When using 4096, 65K, 262K, and 16M color display; you can specify color for each of R, G, B using the palette function.
Use the command for switching between these modes.
(1) 4096-color display
(1-1) Type A 4096 color display
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGG
1st write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBRRRR
2nd write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB
3rd write
2 pixels of data are read after the third write operation as shown, and it is written in the display RAM.
Ver 1.5
16/94
2007/01/20
ST7626
2. 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGGBBBBXXXX
Data is acquired through signal write operation and then written to the display RAM.
“XXXX” are dummy bits, and they are ignored for display.
(1-2) Type B 4096 color display
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRR
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB
2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRRGGGGBBBB
A single pixel of data is read and written in the display RAM in a single write operation.
“XXXX” are dummy bits, and they are ignored for display.
(2) 65K color input mode
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGG
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGBBBBB
2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGGGGGBBBBB (16 bits)
Data is acquired through signal write operation and then written to the display RAM.
(3) Truncated 262K color input mode
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXX
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGXX
2nd write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXX
3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
“X” is dummy bit, and it is ignored for display.
2. 16 bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXXGGGGGGXX
1st write
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXXXXXXXXXXXX
2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
Ver 1.5
17/94
2007/01/20
ST7626
(4) Truncated 16M color input mode
1. 8-bit mode
D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRR
1st write
D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGGG
2nd write
D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBB
3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM.
2. 16 bit mode
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRRGGGGGGGG
1st write
D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBBXXXXXXXX
2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
7.1.3 8- and 9-bit Serial Interface
The 8-bit serial interface uses four pins /CS, SI, SCL, and A0 to enter commands and data. Meanwhile, the 9-bit serial
interface uses three pins /CS, SI and SCL for the same purpose.
Data read is not available in the serial interface. Data entered must be 8 bits. Refer to the following chart for entering
commands, parameters or gray-scale data.
The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode
at every gradation.
(1) 8-bit serial interface (4-line)
th
When entering data (parameters): A0= HIGH at the rising edge of the 8 SCL.
Figure 7.1.3 4-line explaination chart when entering data
Ver 1.5
18/94
2007/01/20
ST7626
th
When entering command: A0= LOW at the rising edge of the 8 SCL
Figure 7.1.4 4-line explaination chart when entering command
(2) 9-bit serial interface (3-line)
st
When entering data (parameters): SI= HIGH at the rising edge of the 1 SCL.
Figure 7.1.5 3-line explaination chart when entering data
st
When entering command: SI= LOW at the rising edge of the 1 SCL.
Figure 7.1.6 3-line explaination chart when entering command
z
If /CS is set to HIGH while the 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering
succeeding sets of data, you must correctly input the data concerned again.
z
In order to avoid data transfer error due to incoming noise, it is recommended to set /CS at HIGH on byte basis to
initialize the serial-to-parallel conversion counter and the register.
z
th
When executing the command RAMWR, set /CS to HIGH after writing the last address (after starting the 9 pulse in
th
case of 9-bit serial input or after starting the 8 pulse in case of 8-bit serial input).
Ver 1.5
19/94
2007/01/20
ST7626
7.2 ACCESS TO DDRAM AND INTERNAL REGISTERS
ST7626 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus
holder attached to the internal, requiring the cycle time alone without needing the wait time.
For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the
DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is
dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus
in the succeeding read cycle. Figure 7.2.1 illustrates these relations.
In 80-series interface mode:
M P U sig nal
W rite
O peratio n
A0
/W R
N
DATA
D (N )
D (N + 1)
D (N + 2)
D (N + 3)
Interna l signals
/W R
B U S H O LD E R
N
AD DRESS CO U NTER
D (N )
N
D (N + 2)
D (N + 1)
N+1
N+2
D (N + 3)
N+3
M PU signal
Read
O peration
A0
/W R
/R D
N
D ATA
D um m y
D (N )
D (N +1)
Internal signals
/W R
/R D
BU S H O LD ER
AD D R ESS C O U N TE R
N
D (N )
D (N )
D (N +1)
D (N +2)
D (N +1)
D (N +2)
D (N +3)
Figure 7.2.1 Access DDRAM chart
Ver 1.5
20/94
2007/01/20
ST7626
7.3 DISPLAY DATA RAM (DDRAM)
7.3.1 DDRAM
It is 98 X 68 X 16 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page
address and column address. Since display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels of
RGB, data transfer related restrictions are reduced, realizing the display flexing.
The RAM on ST7626 is separated to a block per 4 lines to allow the display system to process data on the block basis.
MPU’s read and write operations to and from the RAM are performed via the I/O buffer circuit; Reading of the RAM for the
liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM
configuration.
Memory Map (When using the Type A 4096 color. 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
15
16
SEGout
Ver 1.5
P10:0
P10:1
(DATCTL)
(DATCTL)
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_7
D0_3
D1_7
D1_3
D2_7
D2_3
D146_3
D147_7
D147_3
D0_6
D0_2
D1_6
D1_2
D2_6
D2_2
D146_2
D147_6
D147_2
D0_5
D0_1
D1_5
D1_1
D2_5
D2_1
D146_1
D147_5
D147_1
D0_4
D0_0
D1_4
D1_0
D2_4
D2_0
D146_0-
D147_4
D147_0
0
1
2
3
4
5
291
292
293
21/94
2007/01/20
ST7626
Memory Map (When using the Type A 4096 color. 16-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
15
16
SEGout
Ver 1.5
P10:0
P10:1
(DATCTL)
(DATCTL)
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_15
D0_11
D0_7
D1_15
D1_11
D1_7
D97_15
D97_11
D97_7
D0_14
D0_10
D0_6
D1_14
D1_10
D1_6
D97_14
D97_10
D97_6
D0_13
D0_9
D0_5
D1_13
D1_9
D1_5
D97_13
D97_9
D97_5
D0_12
D0_8
D0_4
D1_12
D1_8
D1_4
D97_12
D97_8
D97_4
0
1
2
3
4
5
291
292
293
22/94
2007/01/20
ST7626
Memory Map (When using the Type B 4096 color. 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
15
16
SEGout
P10:0
P10:1
(DATCTL)
(DATCTL)
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_3
D1_7
D1_3
D2_3
D3_7
D3_3
D146_3
D147_7
D147_3
D0_2
D1_6
D1_2
D2_2
D3_6
D3_2
D146_2
D147_6
D147_2
D0_1
D1_5
D1_1
D2_1
D3_5
D3_1
D146_1
D147_5
D147_1
D0_0
D1_4
D1_0
D2_0
D3_4
D3_0
D146_0
D147_4
D147_0
0
1
2
3
4
5
291
292
293
Note:
You can change position of R and B with DATACTL command.
Ver 1.5
23/94
2007/01/20
ST7626
Memory Map (When using the Type B 4096 color. 16-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
15
16
SEGout
P10:0
P10:1
(DATCTL)
(DATCTL)
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_11
D0_7
D0_3
D1_11
D1_7
D1_3
D97_11
D97_7
D97_3
D0_10
D0_6
D0_2
D1_10
D1_6
D1_2
D97_10
D97_6
D97_2
D0_9
D0_5
D0_1
D1_9
D1_5
D1_1
D97_9
D97_5
D97_1
D0_8
D0_4
D0_0
D1_8
D1_4
D1_0
D97_8
D97_4
D97_0
0
1
2
3
4
5
291
292
293
Note:
You can change position of R and B with DATACTL command.
Ver 1.5
24/94
2007/01/20
ST7626
Memory Map (When using the 65Kcolor. 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_7
D0_2
D1_4
D2_7
D2_2
D3_4
D146_7
D146_2
D147_4
D0_6
D0_1
D1_3
D2_6
D2_1
D3_3
D146_6
D146_1
D147_3
D0_5
D0_0
D1_2
D2_5
D2_0
D3_2
D146_5
D146_0
D147_2
D1_7
D1_1
D2_4
D3_7
D3_1
D146_4
D147_7
D147_1
D1_6
D1_0
D2_3
D3_6
D3_0
D146_3
D147_6
D147_0
P10:0
P10:1
D0_4
(DATCTL)
(DATCTL)
D0_3
D1_5
0
1
15
16
SEGout
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
D3_5
2
3
4
D147_5
5
291
292
293
Note:
You can change position of R and B with DATACTL command.
Ver 1.5
25/94
2007/01/20
ST7626
Memory Map (When using the 65K color. 16-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_15
D0_10
D0_4
D1_15
D1_10
D1_4
D97_15
D97_10
D97_4
D0_14
D0_9
D0_3
D1_14
D1_9
D1_3
D97_14
D97_9
D97_3
D0_13
D0_8
D0_2
D1_13
D1_8
D1_2
D97_13
D97_8
D97_2
D0_7
D0_1
D1_12
D1_7
D1_1
D97_12
D97_7
D97_1
D0_6
D0_0
D1_11
D1_6
D1_0
D97_11
D97_6
D97_0
P10:0
P10:1
D0_12
(DATCTL)
(DATCTL)
D0_11
D0_5
0
1
15
16
SEGout
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
D1_5
2
3
4
D97_5
5
291
292
293
Note:
You can change position of R and B with DATACTL command.
Ver 1.5
26/94
2007/01/20
ST7626
Memory Map (When using the 262K/16Mcolor. 8-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
15
16
SEGout
P10:0
P10:1
(DATCTL)
(DATCTL)
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_7
D1_7
D2_7
D3_7
D4_7
D5_7
D291_7
D292_7
D293_7
D0_6
D1_6
D2_6
D3_6
D4_6
D5_6
D291_6
D292_6
D293_6
D0_5
D1_5
D2_5
D3_5
D4_5
D5_5
D291_5
D292_5
D293_5
D0_4
D1_4
D2_4
D3_4
D4_4
D5_4
D291_4
D292_4
D293_4
D0_3
D1_3
D2_3
D3_3
D4_3
D5_3
D291_3
D292_3
D293_3
D0_2
D1_2
D2_2
D3_2
D4_2
D5_2
D291_2
D292_2
D293_2
D0_1
D1_1
D2_1
D3_1
D4_1
D5_1
D291_1
D292_1
D293_1
D0_0
D1_0
D2_0
D3_0
D4_0
D5_0
D291_0
D292_0
D293_0
0
1
2
3
4
5
291
292
293
Note:
You can change position of R and B with DATACTL command.
Ver 1.5
27/94
2007/01/20
ST7626
Memory Map (When using the 16 gray-scale, 262K/16M color. 16-bit mode)
RGB alignment (Command of data control parameter2=000)
Data control command (BCH)
Column
P11:0(DATCTL)
LCD
read
P11:1(DATCTL)
direction
Color
Data
Page
Block
0
1
15
16
SEGout
P10:0
P10:1
(DATCTL)
(DATCTL)
0
67
1
66
2
65
3
64
4
63
5
62
6
61
7
60
60
7
61
6
62
5
63
4
64
3
65
2
66
1
67
0
0
1
97
97
96
0
R
G
B
R
G
B
R
G
B
D0_15
D0_7
D1_15
D1_7
D2_15
D2_7
D146_7
D147_15
D147_7
D0_14
D0_6
D1_14
D1_6
D2_14
D2_6
D146_6
D147_14
D147_6
D0_13
D0_5
D1_13
D1_5
D2_13
D2_5
D146_5
D147_13
D147_5
D0_12
D0_4
D1_12
D1_4
D2_12
D2_4
D146_4
D147_12
D147_4
D0_11
D0_3
D1_11
D1_3
D2_11
D2_3
D146_3
D147_11
D147_3
D0_10
D0_2
D1_10
D1_2
D2_10
D2_2
D146_2
D147_10
D147_2
D0_9
D0_1
D1_9
D1_1
D2_9
D2_1
D146_1
D147_9
D147_1
D0_8
D0_0
D1_8
D1_0
D2_8
D2_0
D146_0
D147_8
D147_0
0
1
2
3
4
5
291
292
293
Note:
You can change position of R and B with DATACTL command.
Ver 1.5
28/94
2007/01/20
ST7626
7.3.2 Page Address Control Circuit
This circuit is used to control the address in the page direction when MPU accesses the DDRAM or when reading the
DDRAM to display image on the LCD.
You can specify a scope of the page address with page address set command. When the page-direction scan is specified
with DATACTL command and the address are incremented from the start up to the end page, the column address is
incremented by 1 and the page address returns to start page.
The DDRAM supports up to 68 lines, and thus the total page becomes 68.
In the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page
address is returned to start page.
Using the address normal/inverse parameter of DATACTL command allows you to inverse the correspondence between
the DDRAM address and command output.
7.3.3 Column Address Control Circuit
This circuit is used to control the address in the column direction when MPU accesses the DDRAM. You can specify a
scope of the column address using column address set command. When the column-direction scan is specified with
DATACTL command and the address are incremented from the start up to the end page, the page address is incremented
by 1 and the column address returns to start column.
In the read operation, too, the column address is automatically incremented by 1 and returned to start page as the end
column is reached.
Just like the page address control circuit, using the column address normal/inverse parameter of DATACTL command
enables to inverse the correspondence between the DDRAM column address and segment output. This arrangement
relaxes restrictions in the chip layout on the LCD module.
7.3.4 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU’s read or write of DDRAM is
performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM when the
LCD is turned on does not cause troubles such as flicking of the display images.
7.3.5 Block Address Circuit
The circuit associates pages on DDRAM with COM output. ST7626 processes signals for the liquid crystal display on
4-page basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in
block.
7.3.6 Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display
normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in
the DDRAM.
Ver 1.5
29/94
2007/01/20
ST7626
7.4 Area Scroll Display
Using area scroll set and scroll start set commands allows you to scroll the display screen partially. You can select any one
of the following four scroll patterns.
Fixed area
Scroll area
Figure 7.4.1 Scroll Mode explaination chart
Example：In the center screen scroll of 1/48 duty (display range: 48 lines = 12 blocks)
z
Set Area Scroll
command (0x00AA)
z
Block 0 and block 1 (8-lines) are specified for the top fixed area.
Top Block Address = Number of the top fixed area
= 8 / 4 = 2 (0x0002)
parameter (0x0002)
z
Block 15 & block 16 (8-lines) are specified for the bottom fixed area.
z
Block 10 to block 14 (20-lines) are specified for the background area.
Bottom Block Address = Number of Background area + Bottom Block Address
= (20 / 4) + 9 = 14 (0x000E)
z
parameter (0x000E)
Block 2 to Block 9 (32-lines) are specified for the scroll area
Number of Specified Blocks = ((Top Fix Area + Scroll Area) – 1)
= (2 + (12 - 2 - 2)) - 1 = 9 (0x000E)
z
Set area acroll mode – Center Screen Mode
Ver 1.5
parameter (0x0009)
parameter (0x0000)
30/94
2007/01/20
ST7626
98 x 68 DDRAM
Top Fix (2 Blocks)
Scroll Area (7 Blocks)
Background Area (5 Blocks)
Bottom Fix (2 Blocks)
98 x 48(Lines) LCD Panel
Time
0
1
:
:
:
:
9
10
:
15
16
DDRAM
LCD Panel
0
1
2
12 blocks
=48 lines
9
10
Fixed area
14
Scroll area
15
16
Background area
Figure 7.4.2 Reference Example for Scroll Display
Ver 1.5
31/94
2007/01/20
ST7626
7.5 Partial Display
Using partial in command allows you turn on the partial display (division by line) of the screen. This mode requires less
current consumption than the whole screen display, making it suitable for the equipment in the standby state.
: Display area (partial display area)
: Non-display area
Figure 7.5.1 Partial Mode explaination chart
If the partial display region is out of the Max. Display range, it would be no operation
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 7.5.2 Reference Example for Partial Display
Ver 1.5
32/94
2007/01/20
ST7626
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 7.5.3 Partial Display (Partial Display Duty=16, initial COM0=0)
-COM0
-COM1
-COM2
-COM3
-COM4
-COM5
-COM6
-COM7
-COM8
-COM9
-COM10
-COM11
-COM12
-COM13
-COM14
-COM15
-COM16
-COM17
-COM18
-COM19
-COM20
-COM21
-COM22
-COM23
Figure 7.5.4 Moving Display (Partial Display Duty=16, initial COM0=8)
7.6 Gary-Scale Display
ST7626 incorporates a 4FRC & 31 PWM function circuit to display a 64 gray-scale display.
7.7 Oscillation circuit
This is on-chip Oscillator without external resistor. When the internal oscillator is used, CLS must connect to VDD; when
the external oscillator is used, CL could be input pin. This oscillator signal is used in the voltage converter and display
timing generation circuit.
Ver 1.5
33/94
2007/01/20
ST7626
7.8 Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is
generated in synchronization with the display clock and the display data latch circuit latches the 68-bits display data in
synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the
access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M), which
enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start
signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving
waveform and internal timing signal are shown in Figure 7.8.1.
Figure 7.8.1 2-frame AC Driving Waveform (Duty Ratio: 1/68)
63
64
1
2
3
4
5
6
7
8
9
10
11
12
55
56
57
58
59
60
61
62
63
64
1
2
3
4
CL(Internal)
FR(Internal)
M(Internal)
VLCD
V1
V2
V3
V4
Vss
COM0
VLCD
V1
V2
V3
V4
Vss
COM1
VLCD
V1
V2
V3
V4
Vss
SEGn
Figure 7.8.2 N-Line Inversion Driving Waveform (N=5, Duty Ratio=1/64)
Ver 1.5
34/94
2007/01/20
ST7626
7.9 Liquid Crystal drive Circuit
This driver circuit is configured by 68-channel common drivers and 294-channel segment drivers. This LCD panel driver
voltage depends on the combination of display data and M signal.
VDD
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
M
COM0
COM1
COM0
COM2
COM3
COM4
COM5
COM6
COM1
COM7
COM8
COM9
COM2
COM10
COM11
COM12
COM13
COM14
SEG0
SEG 0
1
2
3
4
SEG1
Figure 7.9.1 LCD Driving Waveform
Ver 1.5
35/94
2007/01/20
ST7626
7.10 Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage
follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table
7.10.1 shows the referenced combinations in using Power Supply circuits.
Table 7.10.1 Recommended Power Supply Combinations
Power
User setup
control
(VC VR VF)
Only the internal power
supply circuits are used
V/C
V/R
V/F
circuits
circuits
circuits
VLCD
V0
V1 to V4
a capacitor
111
ON
ON
ON
is series to
Open*1
Open*1
Open*1
Open*1
GND
Only the voltage
regulator circuits and
voltage follower circuits
External
011
OFF
ON
ON
001
OFF
OFF
ON
Open
External input
Open*1
000
OFF
OFF
OFF
Open
External input
External input
input
are used
Only the voltage follower
circuits are used
Only the external power
supply circuits are used
*1 : ST7626 only needs one capacitor series VLCD to GND in normal situation. Add series-capacitors from
V0~V4 to GND will improve display performance.
7.10.1 Voltage Converter Circuits
There is a built-in DC-DC voltage converter circuits in ST7626 for generating VLCDOUT. Multiple of voltage converter is 2、
3、4、5 times of Vdd2 toward positive side, and it can be controlled by software(Command ANASET). Please make sure that
VLCDOUT must below 20V after turn on voltage converter circuit.
7.10.2 Voltage Regulator Circuits
There is a built-in voltage regulaor circuits in ST7626 for generating V0OUT. After VLCDOUT is regulated by voltage regulator
circuit, V0OUT is generated. Users also can use VOP function to program the optimum LCD supply voltage V0 by software
(Command SETVOP). Detail explaination of VOP-set is listed below:
SETVOP
Reset state of Vop[8:0] is 160DEC = 10.00V.
The VOP value is programmed via the Vop[8:0] register.
V0=a+( Vop[8:6]Vop[5:0])．b
Ver 1.5
36/94
2007/01/20
ST7626
Ex:VOP[5:0]=100000, VOP[8:6]=010
→ Vop [8:0]=010100000
→ 3.6+210x0.04=10.00
z
a is a fixed constant value (see table 7.10.2).
z
b is a fixed constant value (see table 7.10.2).
z
VOP[8:0] is the programmed VOP value. The programming range for VOP[8:0] is 5 to 410 (19Ahex).
z
VOP[5:0] is the set-contrast value which can be set via the command SETVOP and EEPROM.(See command
VOLUP & VOLDOWN)
z
The suggested value of V0 is under 11 V with bias =1/9.
Table 7.10.2
SYMBOL
VALUE
UNIT
a
3.6
V
b
0.04
V
The VOP[8:0] value must be in the VOP programming range as given in Figure 7.10.2. Evaluating equation (1), values
outside the programming range indicated in Figure 7.10.2 may result. Calculated values below 4 will be mapped to
VOP[8:0] = 4, resulting VOP[8:0] values higher than 410 will be mapped to VOP[8:0] = 410. Sitronix suggestes Vop range
equals 4.5V to 18V.
Figure 7.10.2 VOP programming range
Ver 1.5
37/94
2007/01/20
ST7626
As the programming range for the internally generated V0 voltage is above the limited V0 (18V), users has to ensure while
setting the VOP register that under all conditions and including all tolerances that the V0 voltage remains below 18V.
Table 7.10.3
Par no.
Equipment Type
Thermal Gradient
ST7626
Internal Power Supply
-0.065%/ C @ V0=10.52V, 25 C
0
0
7.10.3 Voltage Follower Circuits
There is a built-in voltage follower circuits in ST7626 for generating V1、V2、V3 and V4. These voltages are decided by bias
ratio selection circuitry which is set by users with software to control 1/5 to 1/12 bias ratios to match the optimum display
performance of LCD panel. Bias driving rule is listed below:
Table 7.10.4
LCD bias
V1
V2
V3
V4
1/N bias
(N-1) / N x V0
(N-2) / N x V0
(2/N) x V0
(1/N) x V0
N=5 to 12
7.10.4 The Set-up Power Circuits
The ST7626 series has two modes of power circuit. One is 1 CAP with VLCDout, the other is 6 CAP with
VLCDout/V0/V1/V2/V3/V4 (depend on panel loading). The detail circuit is as below.
ST7626
Figure 7.10.3
(a) 1 CAP power circuit
(b) 6 CAP power circuit
Notes: 1. VLCDout: 1.0~2.2uF/25V
2. V0~V4:0.1~1.0uF/25V
Ver 1.5
38/94
2007/01/20
ST7626
7.10.5 EEPROM Setting Flow
♦
EEPROM Setting Flow
ST7626 provide the Write and Read function to write the Electronic Control value and Built-in resistance ratio into and read
them from the built-in EEPROM. Using the Write and Read functions, you can store these values appropriate to each LCD
panel. This function is very convenient for user in setting from some different panel’s voltage.
Figure 7.10.5 EC value control for different modules by loading EEPROM offset
Note1: This setting flow is used for LCM assembler.
Note2: EEPROM shouldn’t be written without preceding loading correctly from EEPROM to avoid some
errors during IC operation.
Note3: When writing value to EEPROM, the voltage of VLCDin must be more than 18V.
Note4: When writing value to EEPROM, the voltage of VDD2~VDD5 must be 2.8~3.3V.
Note5: When writing value to EEPROM, the Regulator and Follower must turn OFF, and Display also
must turn OFF.
Note6: If the EEPROM is exposed to a high temperature for hours, data in the memory cell may
probably be lost before the data retention guarantee period. To retain data in the memory cell,
keep the mamory cell below 90℃. The data retention guarantee period is specified including
the retention period.
Ver 1.5
39/94
2007/01/20
ST7626
♦
EEPROM Flow Chart
RESET
Internal Initialize
Write( COMMAND , 0x31);
Write( COMMAND , 0xF4);
A：Initial Flow
Write( DATA , 0x58);
Show Test Pattern
B：Adjust Vop Offset
C：Write EEPROM
EEPROM Operation
and Booster : ON, Regulator: OFF,
Follower: OFF, Display OFF
Load EEPROM
RESET
NG
Internal Initialize
Write( COMMAND , 0x31);
Write( COMMAND , 0xF4);
A：Initial Flow
Write( DATA , 0x58);
Show Test Pattern
Check If Write
Successfully?
OK
Finish
Ver 1.5
40/94
2007/01/20
ST7626
♦
Software Program
A. Initial Flow
void ST7626_Init( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0x04 );
Write( DATA, 0x3e );
Ver 1.5
// Ext = 0
// Sleep In/Out Preparation
// Sleep In/Out Sequencing
Write( COMMAND, 0x31 );
Write( COMMAND, 0xf4 );
Write( DATA, 0x58 );
// Ext = 1
// Internal Initialize Preparation
// Internal Initialize Sequencing
Write( COMMAND, 0x30 );
Write( COMMAND, 0x94 );
Write( COMMAND, 0xd1 );
Write( COMMAND, 0xca );
Write( DATA, 0x00 );
Write( DATA, 0x10 );
Write( DATA, 0x00 );
// Ext = 0
// Sleep Out
// Internal OSC on
// Display Control
// CL divisions Ratio
// Duty Setting (= 68)
// N-Line Inverse-set value
Write( COMMAND, 0x31 );
Write( COMMAND, 0x32 );
Write( DATA, 0x00 );
Write( DATA, 0x02 );
Write( DATA, 0x03 );
Write( DATA, 0x04 );
// Ext = 1
// Analog Setting
// OSC Freqency adjustment
// Booster Efficiency Setting = Level 3
// Bias Setting (=1/9)
// Booster X 5
Write( COMMAND, 0x30 );
Write( COMMAND, 0x81 );
Write( DATA, 0x2d );
Write( DATA, 0x02 );
Write( COMMAND, 0x20 );
Write( DATA, 0x0b );
// Ext = 0
// Electronic Volume Control
// EV:Vop[5:0]_6bit
// EV:Vop[8:6]_3bit
// Vop is 10.52V under this condition for example
// Power Control
// B/F/R = On/On/On
delay(50000);
LoadEEPROM();
LoadPaint();
// Delay 50ms
// Load EEPROM (refer page 68)
// Load Gamma Table Parameter (refer page 64)
Write( COMMAND, 0x30 );
Write( COMMAND, 0xa7 );
Write( COMMAND, 0xbb );
Write( DATA, 0x01 );
Write( COMMAND, 0xbc );
Write( DATA, 0x00 );
Write( DATA, 0x00 );
Write( DATA, 0x01 );
// Ext = 0
// Inverse Display
// Com Scan Direction
// 0~33 / 67~34
// Data Scan Direction
// Page / Column Address Setting
// RGB arrangement (0:RGB 1:BGR)
// Gray-scale setup ( 64-gray: 01H)
Write( COMMAND, 0x75 );
Write( DATA, 0x00 );
Write( DATA, 0x43 );
Write( COMMAND, 0x15 );
Write( DATA, 0x00 );
Write( DATA, 0x5f );
// Page address set
// From page address 0
// to page address 67
// Column address set
// From column address 0
// to column address 97
41/94
2007/01/20
ST7626
Write( COMMAND, 0xaf );
Write( COMMAND, 0x30 );
// Display On
// Ext = 0
}
B. Adjust Vop Offset
void adj_Vop_offset(void)
{
int i,j=1;
while(j)
{
if (KeyScan1==0)i=1;
if (KeyScan2==0)i=2;
if (KeyScan3==0)i=3;
if (KeyScan1==1 & KeyScan2==1 & KeyScan3==1)i=4;
switch (i)
{
Case 1:
Write( COMMAND, 0xd6 );
break;
case 2:
Write( COMMAND, 0xd7 );
break;
case 3:
write_7626eeprom();
j=0;
break;
default:
break;
}
}
}
// Define KeyScan1 for “D6” use
// Define KeyScan2 for “D7” use
// Define KeyScan3 for “write” use
// Jump to break
// Vop Offset +1 step
// Vop Offset -1 step
// Write EEPROM Flow
C. Write EEPROM
void write_7626eeprom(void)
{
Write( COMMAND, 0x30 );
Ver 1.5
// EXT=0
Write( COMMAND, 0xae );
Write( COMMAND, 0x20 );
Write( DATA, 0x08 );
// Display Off
// Power Control
// B/F/R = ON/OFF/OFF
Write( COMMAND, 0x31 );
Write( COMMAND, 0xCD );
Write( DATA, 0x20 );
delay(50000);
// EXT=1
// Enable EEPORM Write Mode
//
//Delay 50 ms, the range is delay≥50ms
Write( COMMAND, 0xeb );
Write( DATA, 0x00 );
Write( COMMAND, 0xfc );
delay(50000);
// Select EEPROM
// EEPROM 1st byte
// Write Data to EEPROM
// Delay 50ms, the range is 10ms < delay < 80ms
Write( COMMAND, 0xeb );
Write( DATA, 0x01 );
// Select EEPROM
// EEPROM 2nd byte
42/94
2007/01/20
ST7626
Write( COMMAND, 0xfc );
delay(50000);
// Write Data to EEPROM
Write( COMMAND, 0xeb );
Write( DATA, 0x02 );
Write( COMMAND, 0xfc );
delay(50000);
// Select EEPROM
// EEPROM 3rd byte
// Write Data to EEPROM
// Delay 50ms, the range is 10ms < delay < 80ms
Write( COMMAND, 0xeb );
Write( DATA, 0x03 );
Write( COMMAND, 0xfc );
delay(50000);
// Select EEPROM
// EEPROM 4th byte
// Write Data to EEPROM
// Delay 50ms, the range is 10ms < delay < 80ms
Write( COMMAND, 0xeb );
Write( DATA, 0x04 );
Write( COMMAND, 0xfc );
delay(50000);
// Select EEPROM
// EEPROM 5th byte
// Write Data to EEPROM
// Delay 50ms, the range is 10ms < delay < 80ms
Write( COMMAND, 0xcc );
delay(50000);
// Cancel EEPROM
// Delay 50ms
Write( COMMAND, 0x30 );
Write( COMMAND, 0x20 );
Write( DATA, 0x0b );
Write( COMMAND, 0xaf );
// EXT=0
// Power Control
// B/F/R = On/On/On
// Display On
//Delay 50 ms, the range is delay≥50ms
}
Ver 1.5
43/94
2007/01/20
ST7626
7.11 RESET CIRCUIT
When the RST pin reveives a negative reset pulse all internal circuitry will start to initialize. The minimum pulse width for
completing the reset sequence is 3 us at Vdd=1.8V. The ststus of ST7626 after reset flow is listed below:
When Power is turned on
Input power (VDD1~VDD5)
↓
Be sure to apply POWER-ON RESET (RESET=LOW)
↓
< Display Setting 1 >
<< State after reset >>
Display control (DISCTL)
Setting clock dividing ratio:
2 divisions
Duty setting:
1/4
Setting reverse rotation number of line:
11H reverse rotations
Common scan direction (COMSCN)
Setting scan direction:
COM0ÆCOM33, COM34ÆCOM67
Oscillation on (OSCON):
Oscillation off
↓
Sleep-in
Sleep-out (SLIPOUT):
↓
< Power Supply Setting >
<< State after reset >>
Electronic volume control (VOLCTR)
Setting volume value:
0
Setting built-in resistance value:
0 (3.76)
Power control (PWRCTR)
Setting operation of power supply circuit:
ALL OFF
↓
< Display Setting 2 >
<< State after reset >>
Normal rotation of display (DISNOR) / inversion of display (DISINV):
Normal rotation of display
Partial-in (PTLIN) / Partial-out (PLOUT):
Partial-out
Setting fix area:
0
Area scroll set (ASCSET)
Setting area scroll region:
0
Setting area scroll type:
Full-screen scroll
Scroll start set (SCSTART)
Setting scroll start address:
0
↓
< Display Setting 3 >
<< State after reset >>
Data control (DATCTL)
Ver 1.5
44/94
2007/01/20
ST7626
Setting normal radiation / inversion of page address:
Normal rotation
Setting normal radiation / inversion of column address:
Normal rotation
Setting direction of address scanner:
Column direction
Setting RGB arrangement:
RGB
Setting gradation:
65K
65K-color position set (RGBSET8)
All 0
Setting color position at 65K-color:
↓
<< State after reset >>
< RAM Setting >
Page address set (PASET)
Setting start page address:
0
Setting end page address:
0
Column address set (PASET)
Setting start column address:
0
Setting end column address:
0
↓
<< State after reset >>
< RAM Write >
Memory write command (RAMWR)
Writing displayed data: repeat as many as the number needed and
exit by entering other command.
↓
< Waiting (approximately 100ms) >
Wait until the power supply voltage has stabilized.
Enter the power supply control command first, then wait at least
100ms before entering the Display ON command when the built-in
power supply circuit operates. If you do not wait, an unwanted
display may appear on the liquid crystal panel.
↓
Display off
Display on (DISON):
Note: If changes are unnecessary after reset, command input is unnecessary.
Ver 1.5
45/94
2007/01/20
ST7626
8. COMMANDS
8.1 Command table
Ext=0
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
DISON
0
1
0
1
0
1
0
1
1
1
1
Display On
AF
None
1
DISOFF
0
1
0
1
0
1
0
1
1
1
0
Display Off
AE
None
2
DISNOR
0
1
0
1
0
1
0
0
1
1
0
Normal Display
A6
None
3
DISINV
0
1
0
1
0
1
0
0
1
1
1
Inverse Display
A7
None
4
COMSCN
0
1
0
1
0
1
1
1
0
1
1
Com Scan Direction
BB
1 byte
5
DISCTR
0
1
0
1
1
0
0
1
0
1
0
Display Control
CA
3 byte
6
SLPP
0
1
0
0
0
0
0
0
1
0
0
Sleep In/Out Preparation
04
1 byte
7
SLPIN
0
1
0
1
0
0
1
0
1
0
1
Sleep In
95
None
8
SLPOUT
0
1
0
1
0
0
1
0
1
0
0
Sleep Out
94
None
9
PASET
0
1
0
0
1
1
1
0
1
0
1
Page Address Set
75
2 byte
10
CASET
0
1
0
0
0
0
1
0
1
0
1
Column Address Set
15
2 byte
11
DATCTL
0
1
0
1
0
1
1
1
1
0
0
Data Scan Direction
BC
3 byte
12
RAMWR
0
1
0
0
1
0
1
1
1
0
0
Writing to Memory
5C
Data
13
RAMRD
0
1
0
0
1
0
1
1
1
0
1
Reading from Memory
5D
Data
14
PLTIN
0
1
0
1
0
1
0
1
0
0
0
Partial display in
A8
2 byte
15
PLTOUT
0
1
0
1
0
1
0
1
0
0
1
Partial display out
A9
None
16
RMWIN
0
1
0
1
1
1
0
0
0
0
0
Read Modify Write In
E0
None
17
RMWOUT
0
1
0
1
1
1
0
1
1
1
0
Read Modify Write Out
EE
None
18
ASCSET
0
1
0
1
0
1
0
1
0
1
0
Area Scroll Set
AA
4 byte
19
SCSTART
0
1
0
1
0
1
0
1
0
1
1
Scroll Start Set
AB
1 byte
20
OSCON
0
1
0
1
1
0
1
0
0
0
1
Internal OSC on
D1
None
21
OSCOFF
0
1
0
1
1
0
1
0
0
1
0
Internal OSC off
D2
None
22
PWRCTL
0
1
0
0
0
1
0
0
0
0
0
Power Control
20
1 byte
23
VOLCTR
0
1
0
1
0
0
0
0
0
0
1
EC control
81
2 byte
24
VOLUP
0
1
0
1
1
0
1
0
1
1
0
EC increase 1
D6
None
25
VOLDOWN
0
1
0
1
1
0
1
0
1
1
1
EC decrease 1
D7
None
26
STREAD
0
0
1
EPSRRD1
0
1
0
0
1
1
1
1
1
0
0
READ Register1
7C
None
28
EPSRRD2
0
1
0
0
1
1
1
1
1
0
1
READ Register2
7D
None
29
NOP
0
1
0
0
0
1
0
0
1
0
1
NOP Instruction
25
None
30
EEOK
0
1
0
0
0
0
0
0
1
1
1
EEPROM Function Start
07
1 byte
31
RESERVED
0
1
0
1
0
0
0
0
0
1
0
Not Use
82
Ver 1.5
Status Read
Function
Hex Parameter Index
Status Read
46/94
32
2007/01/20
ST7626
Ext=1
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Frame1 Set
0
1
0
0
0
1
0
0
0
0
0
FRAME 1 PWM Set
20
16 byte
1
Frame2 Set
0
1
0
0
0
1
0
0
0
0
1
FRAME 2 PWM Set
21
16 byte
2
Frame3 Set
0
1
0
0
0
1
0
0
0
1
0
FRAME 3 PWM Set
22
16 byte
3
Frame4 Set
0
1
0
0
0
1
0
0
0
1
1
FRAME 4 PWM Set
23
16 byte
4
ANASET
0
1
0
0
0
1
1
0
0
1
0
Analog Set
32
3 byte
5
EPCTIN
0
1
0
1
1
0
0
1
1
0
1
Control EEPROM
CD
1 byte
6
EPCOUT
0
1
0
1
1
0
0
1
1
0
0
Cancel EEPROM
CC
None
7
EPMWR
0
1
0
1
1
1
1
1
1
0
0
Write to EEPROM
FC
None
8
EPMRD
0
1
0
1
1
1
1
1
1
0
1
Read from EEPROM
FD
None
9
DISPADJ
0
1
0
1
1
1
1
1
0
1
0
FA
1 byte
10
IIPP
0
1
0
1
1
1
1
0
1
0
0
F4
1 byte
11
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Ext In
0
1
0
0
0
1
1
0
0
0
0
Ext=0 Set
30
None
--
Ext Out
0
1
0
0
0
1
1
0
0
0
1
Ext=1 Set
31
None
--
Display Performance
Adjustment
Internal Initialize
Preparation
Hex Parameter Index
Ext=1 or Ext=0
Command
Ver 1.5
47/94
Function
Hex Parameter Index
2007/01/20
ST7626
8.2 EXT=”0” Function Description
(1) Display ON (DISON) Command: 1; Parameter: None (AFH)
It is used to turn the display on. When the display is turned on, segment outputs and common outputs are generated at the
level corresponding to the display data and display timing. You can’t turn on the display as long as the sleep mode is
selected. Thus, whenever using this command, you must cancel the sleep mode first.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
1
(2) Display OFF (DISOFF) Command: 1; Parameter: None (AEH)
It is used to forcibly turn the display off. As long as the display is turned off, every on segment and common outputs are
forced to VSS level.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
0
(3) Normal display (DISNOR) Command: 1; Parameter: None (A6H)
It is used to normally highlight the display area without modifying contents of the display data RAM.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
1
0
(4) Inverse display (DISINV) Command: 1; Parameter: None (A7)
It is used to inversely highlight the display area without modifying contents of the display data RAM. This command does
not invert non-display areas in case of using partial display.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
1
1
(5) Common scan (COMSCAN) Command: 1; Parameter: 1 (BBH)
It is used to specify the common output direction in the pin of CSEL = L. This command helps increasing degrees of
freedom of wiring on the LCD panel.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
1
1
1
0
1
1
－
Parameter1 (P1)
１
１
0
*
*
*
*
*
P12
P11
P10
Command Scan direction
When CSEL=0 configuration is selected, pins and common outputs are scanned in the order shown below.
Ver 1.5
Common scan direction
P12
P11
P10
0
0
0
0
Æ
33
34
Æ
67
0
0
1
0
Æ
33
67
Æ
34
0
1
0
33
Æ
0
34
Æ
67
0
1
1
33
Æ
0
67
Æ
34
COM0 pin
COM33 pin
48/94
COM34 pin
COM67 pin
2007/01/20
ST7626
Common scan direction
Original graphic:
Com0
Com34
Com33
Com67
P12:P11:P10:0:0:0 (0Æ33, 34Æ67)
P12:P11:P10:0:0:1 (0Æ33, 67Æ34)
Com0
Com34
Com0
Com33
Com67
Com67
Com33
Com34
P12:P11:P10:0:1:0 (33Æ0, 34Æ67)
P12:P11:P10:0:1:1 (33Æ0, 67Æ34)
Com33
Com34
Com33
Com67
Com0
Com67
Com0
Com34
(6) Display control (DISCTL) Command: 1; Parameter: 3 (CAH)
This command and succeeding parameters are used to perform the display timing-related setups. This command must be
selected before using SLPOUT. Don’t change this command while the display is turned on.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
1
0
0
1
0
1
0
－
Parameter1(P1)
1
1
0
*
*
*
P14
P13
P12
*
*
Parameter2(P2)
1
1
0
*
*
*
P24
P23
P22
P21
P20 Drive duty
Parameter3(P3)
1
1
0
0
P36
P35
P34
P33
P32
P31
P30 FR inverse-set value
Ver 1.5
49/94
CL dividing ratio, F1 and F2
drive pattern.
2007/01/20
ST7626
P1: it is used to specify the CL dividing ratio.
P14, P13, P12: CL dividing ratio. They are used to change number of dividing stages of external or internal clock.
P14
P13
P12
CL dividing ratio
0
0
0
Not divide
0
0
1
2 divisions
0
1
0
4 divisions
0
1
1
8 divisions
P2: It is used to specify the duty of the module on block basis.
Duty
*
*
*
P24
P23
P22
P21
P20
(Numbers of display lines)/4-1
Example: 1/68 duty
0
0
0
0
1
1
1
1
64/4-1=15
This will output driving voltage waveforms from com0 to com63.
P3: It is used to specify number of lines to be inversely highlighted on LCD panel from P36 to P30 (lines can be inversely
highlighted in the range of 2 to 64)
Inversely highlighted line
P37
P36
P35
P34
P33
P32
P31
P30
Inversely highlighted lines-1
Example: 0AH
0
0
0
0
1
0
1
0
11 (lines)-1 = 10 (lines)
Example: 7CH
0
1
1
1
1
1
0
0
61 (lines)-1 = 60 (lines)
P34=”0”: Frame inversion occurs every frame; P34=”1”: Independent from frames.
In the default, 0 inverse highlighted line is selected.
(7) Sleep In/Out Preparation (SLPP) Command: 1; Parameter: 1
Using this command to setup ready status for sleep-in or sleep out.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
0
0
0
1
0
0
－
Parameter(P1)
1
1
0
0
0
1
1
1
1
1
P10
Sleep in/out ready
P10 =” 1”: Ready for sleep in. P10 = “0”: Ready for sleep out.
Parameter 3FH is used to initialize sleep-in sequencing, and parameter 3EH is used to initialize sleep-out sequencing.
(8) Sleep in (SPLIN) Command: 1; Parameter: None (95H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
0
1
0
1
(9) Sleep out (SLPOUT) Command: 1; Parameter: None (94H)
Command
Ver 1.5
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
0
1
0
0
50/94
2007/01/20
ST7626
(10) Page address set (PASET) Command: 1; Parameter: 2 (75H)
When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the
page address area. As the addresses are incremented from the start to the end page in the page-direction scan, the
column address is incremented by 1 and the page address is returned to the start page.
Note: that the start and end page must be specified as a pair. Also, the relation “start page < end page” must be
maintained.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
1
1
1
0
1
0
1
－
Parameter1(P1)
1
1
0
*
P16
P15
P14
P13
P12
P11
P10
Start page
Parameter2(P2)
1
1
0
*
P26
P25
P24
P23
P22
P21
P20
End page
(11) Column address set (CASET) Command: 1; Parameter: 2 (15H)
When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the
column address area. As the addresses are incremented from the start to the end column in the column-direction scan, the
page address is incremented by 1 and the column address is returned to the start column.
Note: that the start and end column must be specified as a pair. Also, the relation “start column < end column” must be
maintained.
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
0
1
0
1
0
1
－
Parameter1(P1)
1
1
0
*
P16
P15
P14
P13
P12
P11
P10
Start address
Parameter2(P2)
1
1
0
*
P26
P25
P24
P23
P22
P21
P20
End address
(12) Data control (DATCTL) Command: 1; Parameter: 3 (BCH)
This command and succeeding parameters are used to perform various setups needed when MPU operates display data
stored on the built-in RAM.
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
0
1
0
1
1
1
1
0
0
－
Normal/inverse display of
Parameter1(P1)
1
1
0
*
*
*
*
*
P12
P11
P10 page/column address and
address scan direction.
Parameter2(P2)
1
1
0
*
*
*
*
*
*
*
P20 RGB arrangement
Parameter3(P3)
1
1
0
*
*
*
*
*
P32
P31
P30 Gray-scale setup
P1: It is used to specify the normal or inverse display of the page / column address and also to specify the address
scanning direction.
P10: Normal/inverse display of the page address. P10=0: Normal and P10=1: Inverse
P11: Normal/reverse turn of column address. P11=0: Normal rotation and P11=1: Reverse rotation.
P12: Address-scan direction. P12=0: In the column direction and P12=1: In the page direction.
Ver 1.5
51/94
2007/01/20
ST7626
Page address and page-address scan direction
P12=0 Column direction
P11=0
P11=1
P10=0
0
1
2
P10=1
67
66
65
65
66
67
2
1
0
0
97
1
96
2
95
95
2
96
1
97
0
0
97
1
96
2
95
95
2
96
1
97
0
P12=1 Page direction
P11=0
P11=1
P10=0
0
1
2
P10=1
67
66
65
65
66
67
2
1
0
P2: RGB arrangement. This parameter allows you to change RGB arrangement of data which is going to be written into
RAM, and therefore causes the inverse RGB rotation of the segment output of ST7626. You can fit RGB arrangement
on the LCD panel according to this parameter setting.
P20
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
…
SEG293
0
R
G
B
R
G
B
R
G
…
B
1
B
G
R
B
G
R
B
G
…
R
P3: Gray scale setup. Using this parameter, you can select the 4K, 65K, 262K, and 16M display mode depending on the
difference in RGB data arrangement.
P32
P31
P30
Numbers of gray-scale
0
0
1
64-gray 65K
0
1
0
64-gray 262K
1
0
0
64-gray 16M
1
0
1
16-gray 4K Type A
1
1
0
16-gray 4K Type B
Ver 1.5
52/94
2007/01/20
ST7626
(13) Memory write (RAMWR) Command: 1; Parameter: Numbers of data written (5CH)
When MPU writes data to the display memory, this command turns on the data entry mode. Entering this command always
sets the page and column address at the start address. You can rewrite contents of the display data RAM by entering data
succeeding to this command. At the same time, this operation increments the page or column address as applicable. The
write mode is automatically cancelled if any other command is entered.
1. 8-bit bus
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
1
0
1
1
1
0
0
－
Parameter
1
1
0
A0
RD
RW
D15
D14
…
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
*
*
…
*
*
0
1
0
1
1
1
0
0
Memory write
parameter
1
1
0
Data to be written
Data to be written
2. 16-bit bus
Data to be written
Write data
(14) Memory read (RAMRD) Command: 1; Parameter: Numbers of data read (5DH)
When MPU read data from the display memory, this command turns on the data read mode. Entering this command
always sets the page and column address at the start address. After entering this command, you can read contents of the
display data RAM. At the same time, this operation increments the page or column address as applicable. The data read
mode is automatically cancelled if any other command is entered.
1. 8-bit bus
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
1
0
1
1
1
0
1
－
Parameter
1
0
1
A0
RD
RW
D15
Command
0
1
0
*
parameter
1
0
1
Data to be read
Data to be read
2. 16-bit bus
D14
….
D9
D8
*
*
*
*
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
0
1
1
1
0
1
Memory read
Data to be read
Read data
(15) Partial in (PTLIN) Command: 1; Parameter: 2 (A8H)
This command and succeeding parameters specify the partial display area. This command is used to turn on partial display
of the screen (dividing screen by lines) in order to save power. Since ST7626 processes the liquid crystal display signal on
4-line basis (block basis), the display and non-display areas are also specified on 4-bit line (block basis).
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
1
0
1
0
0
0
－
Parameter(P1)
1
1
0
*
*
*
P14
P13
P12
P11
P10
Start block address
Parameter(P2)
1
1
0
*
*
*
P24
P23
P22
P21
P20
End block address
A block address that can be specified for the partial display must be the display one (don’t try to specify an address not to
be displayed when scrolled).
Ver 1.5
53/94
2007/01/20
ST7626
(16) Partial out (PTLOUT) Command: 1; Parameter: 0 (A9H)
This command is used to exit from the partial display mode.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
0
0
1
(17) Read modify write in (RMWIN) Command: 1; Parameter: 0 (E0H)
This command is used along with the column address set command, page address set command and read modify write out
command. This function is used when frequently modifying data to specify a specific display area such as blinking cursor.
First set a specific display area using the column and page address commands. Then, enter this command to set the
column and page addresses at the start address of the specific area. When this operation is complete, the column (page)
address won’t be modified by the display data read command. It is incremented only when the display data write command
is used. You can cancel this mode by entering the read modify write out or any other command.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
(18) Read modify write out (RMWOUT) Command: 1; Parameter: 0 (EEH)
Enter this command cancels the read modify write mode
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
(19) Area scroll set (ASCSET) Command: 1; Parameter: 4 (AAH)
It is used when scrolling only the specified portion of the screen (dividing the screen by lines). This command and
succeeding parameters specify the type of area scroll, fix area and scroll area.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
1
0
1
0
1
0
－
Parameter(P1)
1
1
0
*
*
*
P14
P13
P12
P11
P10
Top block address
Parameter(P2)
1
1
0
*
*
*
P24
P23
P22
P21
P20
Bottom block address
Parameter(P3)
1
1
0
*
*
*
P34
P33
P32
P31
P30
Number of specified blocks
Parameter(P4)
1
1
0
*
*
*
*
*
*
P41
P40
Area scroll mode
P4: It is used to specify an area scroll mode.
P41
P40
Type of area scroll
0
0
Center screen scroll
0
1
Top screen scroll
1
0
Bottom screen scroll
1
1
Whole screen scroll
Ver 1.5
54/94
2007/01/20
ST7626
Center screen scroll
Fixed area
Top screen scroll
Bottom screen scroll
Whole screen scroll
Scroll area
Since ST7626 processes the liquid crystal display signals on the four-line basis (block basis), FIX and scroll areas are also
specified on the four-line basis (block basis).
DDRAM address corresponding to the top FIX area is set in the block address incrementing direction starting with 0 block.
DDRAM address corresponding to the bottom FIX area is set in the block address decreasing direction starting with 16
st
block. Other DDRAM blocks excluding the top and bottom FIX areas are assigned to the scroll + background areas.
th
P1: It is used to specify the top block address of the scroll + background areas. Specify the 0 block for the top screen
scroll or whole screen scroll.
th
P2: It specifies the bottom address of the scroll+ background areas. Specify the 16 block for the bottom or whole screen
scroll.
Required relation between the start and end blocks (top block address<bottom block address) must be maintained.
P3: It specifies a specific number of blocks {Numbers of (Top FIX area +Scroll area) block-1}. When the bottom scroll or
whole screens scroll, the value is identical with P2.
You can turn on the area scroll function by executing the area scroll set command first and then specifying the display start
block of the scroll area with the scroll start set command.
[Area Scroll Setup Example]
In the center screen scroll of 1/48 duty (display range: 48 lines = 12 blocks), if 8 lines = 2 blocks and 8 lines = 2 blocks are
specified for the top and bottom FIX areas, 36 lines = 9 blocks is specified for the scroll areas, respectively, 16 lines = 4
blocks on the DDRAM are usable as the background area. Value of each parameter at this time is as shown below.
Ver 1.5
55/94
2007/01/20
ST7626
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
P1
1
1
0
*
*
*
0
0
0
1
0
Top block address = 02 H
P2
1
1
0
*
*
*
0
1
1
1
0
Bottom block address = 0E H
P3
1
1
0
*
*
*
0
1
1
0
0
Number of specific blocks = 09 H
P4
1
1
0
*
*
*
*
*
*
0
0
Area scroll mode = center
(20) Scroll start address set (SCSTART) Command:1 Parameter: 1 (ABH)
This command and succeeding parameters are used to specify the start block address of the scroll area.
Note: that you must execute this command after executing the area scroll set command. Scroll becomes available by
dynamically changing the start block address.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
1
0
1
0
1
1
－
Parameter(P1)
1
1
0
*
*
*
P14
P13
P12
P11
P10
Start block address
(21) Internal oscillation on (OSCON) Command: 1; Parameter: 0 (D1H)
This command turns on the internal oscillation circuit. It is valid only when the internal oscillation circuit of CLS = HIGH is
used.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
0
0
1
(22) Internal oscillation off (OSOFF) Command: 1; Parameter: 0 (D2H)
It turns off the internal oscillation circuit. This circuit is turned off in the reset mode.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
0
1
0
(23) Power control set (PWRCTR) Command: 1; Parameter: 1 (20H)
This command is used to turn on or off the Booster circuit, follower voltage, and voltage regulator circuit.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
1
0
0
1
0
0
0
0
0
Parameter(P1)
1
1
0
*
*
*
0
P13
0
P11
P10
Function
－
LCD drive power
P10: It turns on or off the voltage regulator voltage.
P10 = “1”: ON. P10 =” 0”: OFF
P11: It turns on or off the follower circuit.
P11 = “1”: ON. P11 =” 0”: OFF
P13:It turns on or off the Booster.
P13 = “1”: ON. P13 =” 0”: OFF
Ver 1.5
56/94
2007/01/20
ST7626
(24) Electronic volume control (VOLCTR) Command: 1; Parameter: 2 (81H)
The command is used to program the optimum LCD supply voltage VOP. Reference to 7.10.2
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
1
0
0
0
0
0
0
1
－
Parameter(P1)
1
1
0
*
*
P15
P14
P13
P12
P11
P10
Set Vop[5:0]
Parameter(P2)
1
1
0
*
*
*
*
*
P18
P17
P16
Set Vop[8:6]
(25) Increment electronic control (VOLUP) Command: 1; Parameter: 0 (D6H)
With the VOLUP and VOLDOWN command the VOP voltage and therewith the contrast of the LCD can be adjusted.
This command increments electronic control value Vop[5:0] of voltage regulator circuit by 1.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
1
1
0
If you set the electronic control value to 111111, the control value is set to 000000 after this command has been executed.
(26) Decrement electronic control (VOLDOWN) Command: 1; Parameter: 0 (D7H)
With the VOLUP and VOLDOWN command the VOP voltage and therewith the contrast of the LCD can be adjusted.
This command decrements electronic control value Vop[5:0] of voltage regulator circuit by 1.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
1
0
1
1
1
If you set the electronic control value to 000000, the control value is set to 111111 after this command has been executed.
Table 8.1.1 Possible Vop[5:0] values
Ver 1.5
Electronic Control Value
Decimal Equivalent
VOP Offset
111111
31
+1240 mV
111110
30
+1200 mV
111101
29
+1160 mV
…
…
…
000010
2
+80 mV
000001
1
+40 mV
000000
0
0 mV
111111
-1
-40 mV
111110
-2
-80 mV
…
…
…
100010
-30
-1200 mV
100001
-31
-1240 mV
100000
-32
-1280mV
57/94
2007/01/20
ST7626
(27) Status read (STREAD) Command: 1; Parameter: None
It is the command for reading the internal condition of the IC.
A0
RD
RW
0
0
1
Command
D7
D6
D5
D4
D3
D2
D1
D0
(8) Status data
Issue STREAD (Status Read) command is only for reading the internal condition of the IC. One status data can be
displayed depending on the setting. Issue the NOP command after the STREAD (Status Read) command.
The Status data will be composed of 8 bits below:
D7: Area scroll mode
Refer to P41 (ASCSET)
D6: Area scroll mode
Refer to P40 (ASCSET)
D5: RMW on/off
0 : Out
1 : In
D4: Scan direction
0 : Column
1 : Page
D3: Display ON/OFF
0 : OFF
1 : ON
D2: EEPROM access
0: OutAccess
1: InAccess
D1: Display normal/inverse
0 : Normal
1 : Inverse
D0: Partial display
0 : OFF
1 : ON
(28) Read Register 1 (EPSRRD1) Command: 1; Parameter: 0 (7CH)
It is the command for reading the Electronic Control values.
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
1
1
1
0
0
Issue the EPSRRD1 and then STREAD (Status Read) commands in succession to read the Electronic Control values. One
status data can be displayed depending on the setting. Also, always issue the NOP command after the STREAD (Status
Read) command.
The Status data will be composed of 8 bits below:
D7: 0
D6: 0
D[5:0]: Vop[5:0]
Ver 1.5
Refer to electronic volume control values Vop[5:0]
58/94
2007/01/20
ST7626
(29) Read Register 2 (EPSRRD2) Command: 1 ;Parameter: 0 (7DH)
It is the command for reading ID codes of the ST7626 and the built-in resistance ratio.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
1
1
1
1
0
1
Command
Issue the EPSRRD2 and then STREAD (Status Read) commands in succession to read IC’s ID and the built-in resistance
ratio. One status data can be displayed depending on the setting. Also, always issue the NOP command after the STREAD
(Status Read) command.
The Status data will be composed of 8 bits below:
D[7:3]: ST7626 ID codes
00010
D[2:0]: Vop[8:6]
Refer to the built-in resistance ratio Vop[8:6]
(30) Non-operating (NOP) Command: 1; Parameter: 0 (25H)
This command does not affect the operation.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
0
1
0
1
Command
This command, however, has the function of canceling the IC test mode. Thus, it is recommended to enter it periodically to
prevent malfunctioning due to noise and such.
(31) EEPROM Function Start (EEOK) Command:1;Parameter:1(07H)
In the EEPROM read/write flow, EEPROM is ready after issuing this command. Its parameter is set to 19H.
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
0
0
0
1
1
1
－
Parameter(P1)
1
1
0
0
0
0
1
1
0
0
1
19H
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
0
0
0
1
0
(32) Reserved (82H)
Do not use this command
Command
Ver 1.5
59/94
2007/01/20
ST7626
8.3 EXT=”1” Function Description
(1) Set Frame1 value (Frame1 set) Command: 1; Parameter: 16 (20H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Frame1 Set
0
1
0
0
0
1
0
0
0
0
0
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
1
0
0
0
0
0
－
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set RGB level 0 of 1st frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set RGB level 1 of 1st frame
Parameter15(P15)
1
1
0
*
*
*
P154 P153 P152 P151 P150 Set RGB level 14 of 1st frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set RGB level 15 of 1st frame
FRAME 1 PWM Set
(2)Set Frame2 value (Frame2 set) Command: 1; Parameter: 16 (21H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Frame2 Set
0
1
0
0
0
1
0
0
0
0
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
1
0
0
0
0
0
－
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set RGB level 0 of 2nd frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set RGB level 1 of 2nd frame
Parameter15(P15)
1
1
0
*
*
*
P154 P153 P152 P151 P150 Set RGB level 14 of 2nd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set RGB level 15 of 2nd frame
FRAME 2 PWM Set
(3) Set Frame3 value (Frame3 set) Command: 1; Parameter: 16 (22H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Frame3 Set
0
1
0
0
0
1
0
0
0
1
0
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
1
0
0
0
0
0
－
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set RGB level 0 of 3rd frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set RGB level 1 of 3rd frame
Parameter15(P15)
1
1
0
*
*
*
P154 P153 P152 P151 P150 Set RGB level 14 of 3rd frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set RGB level 15 of 3rd frame
Ver 1.5
60/94
Function
FRAME 3 PWM Set
2007/01/20
ST7626
(4) Set Frame4 value (Frame4 set) Command: 1; Parameter: 16 (23H)
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Frame4 Set
0
1
0
0
0
1
0
0
0
1
1
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
1
0
0
0
0
0
－
Parameter1(P1)
1
1
0
*
*
*
P14 P13 P12 P11 P10 Set RGB level 0 of 4th frame
Parameter2(P2)
1
1
0
*
*
*
P24 P23 P22 P21 P20 Set RGB level 1 of 4th frame
Parameter15(P15)
1
1
0
*
*
*
P154 P153 P152 P151 P150 Set RGB level 14 of 4th frame
Parameter16(P16)
1
1
0
*
*
*
P164 P163 P162 P161 P160 Set RGB level 15 of 4th frame
FRAME 4 PWM Set
The default value of RGB level set
FRAM1 SET
FRAM2 SET
FRAM3 SET
FRAME4 SET
RGB level0
00
00
00
00
RGB level1
02
02
02
02
RGB level2
04
04
04
04
RGB level3
06
06
06
06
RGB level4
08
08
08
08
RGB level5
0A
0A
0A
0A
RGB level6
0C
0C
0C
0C
RGB level7
0E
0E
0E
0E
RGB level8
10
10
10
10
RGB level9
12
12
12
12
RGB level10
14
14
14
14
RGB level11
16
16
16
16
RGB level12
18
18
18
18
RGB level13
1A
1A
1A
1A
RGB level14
1C
1C
1C
1C
RGB level15
1E
1E
1E
1E
All the modulation range of each level for each frame is from 00’H to 1F’H.
Example：Paint setup
void LoadPaint( void )
{
Write( COMMAND, 0x0031 );
Write( COMMAND, 0x0020 );
Write( DATA, 0x0000 );
Write( DATA, 0x0002 );
Write( DATA, 0x0005 );
Ver 1.5
// Ext = 1
// Palette FRC1 Setup
// RGB Level0 Setup
// RGB Level1 Setup
// RGB Level2 Setup
61/94
2007/01/20
ST7626
…….
Write( DATA, 0x001E );
…….
// RGB Level15 Setup
Write( COMMAND, 0x0021 );
Write( DATA, 0x0000 );
Write( DATA, 0x0002 );
Write( DATA, 0x0005 );
…….
Write( DATA, 0x001E );
// Palette FRC2 Setup
// RGB Level0 Setup
// RGB Level1 Setup
// RGB Level2 Setup
…….
// RGB Level15 Setup
Write( COMMAND, 0x0022 );
Write( DATA, 0x0000 );
Write( DATA, 0x0002 );
Write( DATA, 0x0005 );
…….
Write( DATA, 0x001E );
// Palette FRC3 Setup
// RGB Level0 Setup
// RGB Level1 Setup
// RGB Level2 Setup
…….
// RGB Level15 Setup
Write( COMMAND, 0x0023 );
Write( DATA, 0x0000 );
Write( DATA, 0x0002 );
Write( DATA, 0x0005 );
…….
Write( DATA, 0x001E );
// Palette FRC4 Setup
// RGB Level0 Setup
// RGB Level1 Setup
// RGB Level2 Setup
…….
// RGB Level15 Setup
Write( COMMAND, 0x0030 );
// Ext = 0
}
(5) Analog set (ANASET) Command 1; Parameter: 3 (32H)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Function
Command
0
1
0
0
0
1
1
0
0
1
0
Parameter1(P1)
1
1
0
*
*
*
*
*
P12
P11
P10 OSC frequency Adjustment
Parameter2(P2)
1
1
0
*
*
*
*
*
*
P21
P20 Booster Efficiency Set
Parameter3(P3)
1
1
0
*
*
*
*
*
P32
P31
P30 Bias setting
Parameter4(P4)
1
1
0
*
*
*
*
*
P42
P41
P40 Booster setting
－
P1: OSC frequency adjustment
P12
P10
P10
CL pin frequency ( KHz ) :
CL pin frequency ( KHz ) :
CL dividing ratio setting = 00H
CL dividing ratio setting = 04H
(No division)
(Divided by 2)
0
0
0
5.39
2.70
0
0
1
5.64
2.82
0
1
0
6.18
3.09
0
1
1
6.83
3.42
1
0
0
7.65
3.82
1
0
1
8.68
4.34
1
1
0
10.10
5.05
1
1
1
12.02
6.01
Ver 1.5
62/94
2007/01/20
ST7626
OSC frequency can be adjusted by P1 setting and command CAH, see page 46.
The default OSC frequency (CL pin frequency) is 5.39 KHz.
And the frame frequency is from OSC frequency and duty setting, as the formula shown below:
Frame frequency = OSC frequency/(Duty+1)
Example:
1.
duty=68, P1 setting=[000], frame frequency=5.39KHz/78.12Hz
2.
duty=64, P1 setting=[101], frame frequency=8.68KHz/133.53Hz
P2: Booster Efficiency set
P21
P20
Frequency ( Hz )
0
0
Level 1
0
1
Level 2
1
0
Level 3
1
1
Level 4
By Booster Stages (2X, 3X, 4X, 5X) and Booster Efficiency (Level1~4) commands, we could easily set the best Booster
performance with suitable current consumption. If the Booster Efficiency is set to lower level (level1 is higher than level4).
The Boost Efficiency is better than higher level, and it just need few more power consumption current.
P3: Select LCD bias ratio of the voltage required for driving the LCD.
P32
P31
P30
LCD bias
0
0
0
1/12
0
0
1
1/11
0
1
0
1/10
0
1
1
1/9
1
0
0
1/8
1
0
1
1/7
1
1
0
1/6
1
1
1
1/5
P4: Booster setting.
P42
P41
P40
0
0
0
Booster off
0
0
1
2 times boosting circuit
0
1
0
3 times boosting circuit
0
1
1
4 times boosting circuit
1
0
0
5 times boosting circuit
Ver 1.5
63/94
2007/01/20
ST7626
(6) Control EEPROM: 1; Parameter: 1 (CDH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
1
0
0
1
1
0
1
Parameter1(P1)
1
1
0
*
*
P15
*
*
*
*
*
P15: when setting “1” Î The Write Enable of EEPROM will be opened.
P15: when setting “0” Î The Read Enable of EEPROM will be opened.
(7) Cancel EEPROM Command: 1; Parameter: None (CCH)
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
0
1
1
0
0
(8) Write data to EEPROM (EPMWR) Command: 1; Parameter: None (FCH)
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
1
1
1
0
0
(9) Read data from EEPROM (EPMWR) Command: 1; Parameter: None (FDH)
Command
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
1
1
1
0
1
(10) Display performance adjustment (DISPADJ) Command: 1; Parameter: 1 (FAH)
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Command
0
1
0
1
1
1
1
1
0
1
0
Parameter1(P1)
1
1
0
*
*
*
P14
P13
P12
P11
Function
Display performance adjustment
P10 Fine tuning level set
ST7626 provide the function of 32 levels fine tuning to adjust best crosstalk performance for each module. Just like Vop
offset for different modules, the fine tuning level value can also be stored in EEPROM, and therefore each module can
have its individual setup for best display performance.
Due to IC and module process variation, it’s hard for all modules to have same display performance. By using this
command, different modules can adjust to the best performance by having different parameters of DISPADJ. When loading
EEPROM, this individual parameter can be loaded into IC and best display performance can be achieved. Detail using
method please refer ST7626 EEPROM User Manual guide.
(11) Internal Initialize Preparation (IIPP) Command: 1; Parameter: 1 (F4H)
Use this command to set internal initializing for ready status.
Command
Parameter(P1)
Ver 1.5
A0
RD
RW
D7
D6
D5
D4
D3
D2
D1
D0
Function
0
1
0
1
1
1
1
0
1
0
0
－
1
1
0
0
1
0
1
1
0
0
0
64/94
Internal initialize
sequencing
2007/01/20
ST7626
8.4 EXT=”0” or ”1” Function Description
(1) Extension instruction disable (EXT IN) Command:1 Parameter: None (30H)
Use the “Ext=0” command table
Command
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
0
0
0
0
(2) Extension instruction enable (EXT OUT) Command:1 Parameter: None (31H)
Use the extended command table (EXT=”1”)
Command
Ver 1.5
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
1
0
0
0
1
65/94
2007/01/20
ST7626
8.5 Referential Instruction Setup Flow
8.5.1 Initializing with the Built-in Power Supply Circuits
Power On
Keeping the /RES Pin = "L" ( t > tRW )
and waiting for stabilizing the Power
/RES Pin="H"
Wait a minute ( t > tR )
And execute below Instruction Immediately
Write (Command, 0x31);
Write (Command, 0xF4);
Write (data, 0x58);
User Application Setup by Internal Instructions
[Sleep Out: 94H]
[Internal OSC On: D1H]
[Display Control: CAH]
[COM Scan Direction: BBH]
User LCD Power Setup by Internal Instructions
[Analog Control - LCD Bias Select … : 32H]
[Electronic Volume Control: 81H]
[DC-DC Step-up Register Select: 20H]
Execute the “Load EEPROM Flow”
Execute the “Load Paint Flow”
( Adjust for Panel Characteristics )
[Normal / Inverse Display: A6H/A7H]
[Data Display Setting: BCH]
[Display On: AFH]
[Column Address Setting: 15H]
[Page Address Setting: 75H]
[Entry Data Write Mode: 5CH]
End of Initialization
Ver 1.5
66/94
2007/01/20
ST7626
Example：ST7626 Initial setting for 98X68
void ST7626_Init( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0x04 );
Write( DATA, 0x3e );
// Ext = 0
//Sleep In/Out Preparation
//Sleep In/Out Sequencing
Write( COMMAND, 0x31 );
Write( COMMAND, 0xf4 );
Write( DATA, 0x58 );
// Ext = 1
// Internal Initialize Preparation
// Internal Initialize Sequencing
Write( COMMAND, 0x30 );
Write( DATA, 0x10 );
Write( DATA, 0x00 );
// Ext = 0
// Duty Setting (= 68)
// N-Line Inverse-set value
Write( COMMAND, 0x31 );
Write( COMMAND, 0x32 );
Write( DATA, 0x00 );
Write( DATA, 0x02 );
Write( DATA, 0x03 );
Write( DATA, 0x04 );
// Ext = 1
// Analog Setting
// OSC Freqency adjustment
// Booster Efficiency Setting is level3
// Bias Setting (=1/9)
// Booster is X5
Write( COMMAND, 0x30 );
Write( COMMAND, 0x81 );
Write( DATA, 0x2D );
Write( DATA, 0x02 );
Write( COMMAND, 0x20 );
Write( DATA, 0x0b );
// Ext = 0
// Electronic Volume Control
// EV:Vop[5:0]_6bit
// EV:Vop[8:6]_3bit
// Vop is 10.52V under this condition for example
// Power Control
// B/F/R = On/On/On
delayms(50);
LoadEEPROM()
// Delay 50ms
// Load EEPROM example program (refer page 68)
LoadPaint();
// Load Gamma Table Parameter (refer page 61)
Write( COMMAND, 0x30 );
Write( COMMAND, 0xa7 );
Write( COMMAND, 0xbb );
Write( DATA, 0x01 );
Write( COMMAND, 0xbc );
Write( DATA, 0x00 );
Write( DATA, 0x00 );
Write( DATA, 0x01 );
// Ext = 0
// Inverse Display
// Com Scan Direction
// 0~33 / 67~34
// Data Scan Direction
// Page / Column Address Setting
// RGB arrangement (0:RGB 1:BGR)
// Gray-scale setup ( 64-gray: 01H)
Write( COMMAND, 0x75 );
Write( DATA, 0x00 );
Write( DATA, 67 );
Write( COMMAND, 0x15 );
Write( DATA, 0x00 );
Write( DATA, 97 );
// Page address set
// From page address 0
// to page address 67
// Column address set
// From column address 0
// to column address 97
Write( COMMAND, 0xaf );
Write( COMMAND, 0x30 );
// Display On
// Ext = 0
}
Ver 1.5
67/94
2007/01/20
ST7626
Example：Load EEPROM
void LoadEEPROM( void )
{
Write( COMMAND, 0x31 );
Write( COMMAND, 0xcd );
Write( DATA, 0x00 );
delayms(50);
Write( COMMAND, 0xfd );
delayms(50);
Write( COMMAND, 0xcc );
Write( COMMAND, 0x30 );
// Ext = 1
// Enable EEPROM
//
// Delay 50ms
// Load EEPROM
// Delay 50ms
// Disable EEPROM
// Ext = 0
}
8.5.2 Data Displaying
Normal State
Display Data RAM Addressing by Instruction
[Data Control: BCH]
[Set Page Address: 75H]
[Set Column Address: 15H]
[Entry Memory Write Mode: 5CH]
Display Data Write
[Display Data Write]
No
End of Display Data Write ?
Yes
End of Data Display
Figure 8.5.2.1 Data Displaying
Ver 1.5
68/94
2007/01/20
ST7626
Example：Display for 98X68
void Display( char *pattern )
{
unsigned char i, j;
Write( COMMAND, 0x30 );
Write( COMMAND, 0x15 );
Write( DATA, 0 );
Write( DATA, 97 );
Write( COMMAND, 0x75 );
Write( DATA, 0 );
Write( DATA, 67 );
Write( COMMAND, 0x5c )
for( j = 0; j < 68 ; j++ )
for( i = 0 ; i < 98 ; i++ )
Write( DATA, pattern[ j ][ i ] );
// Ext = 0
// Column address set
// From column address 0 to 97
// Page address set
// From page address 0 to 67
// Entry Memory Write Mode
// Display Data Write
}
8.5.3 Partial Display In/Out
Figure 8.5.3.1 Partial Display In/Out
Ver 1.5
69/94
2007/01/20
ST7626
Example：Partial Display In Operation
void PartailIn( unsigned char start_block, unsigned char end_block )
{
Write( COMMAND, 0x30 );
// Ext = 0
Write( COMMAND, 0xA8);
// Partial Display In Function
Write( DATA, start_block );
// Start Block
Write( DATA, end_block );
// End Block
}
void PartailOut( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xA9 );
}
// Ext = 0
// Partial Display Out Function
void main()
{
PartialIn( 11, 18 );
// entry partial display mode
Windowing( 0, 11*4, 131, 18*4 );
PartialDisplay( display_pattern );
.
.
.
PartialOut();
// set the page and column range
// Fill the data into partial display area
// Out of partial display mode
}
Ver 1.5
70/94
2007/01/20
ST7626
8.5.4 Scroll Display
Figure 8.5.4.1 Scroll Display
Example：Screen Scroll Operation
void CenterScreenScroll( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xAA);
Write( DATA, 0x0a );
Write( DATA, 0x14 );
Write( DATA, 0x14 );
Write( DATA, 0x00 );
ScrollUp() or ScrollDown();
// Ext = 0
// Partial Display In Function
// Top_Block=10
// Bottom_Block=20
// Number of Specified Blocks=Bottom_Block=20
// Area Scroll Type=Center Screen Scroll
// Scroll Up or Scroll Down
}
void TopScreenScroll( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xAA);
Write( DATA, 0x00 );
Write( DATA, 0x14 );
Write( DATA, 0x14 );
Write( DATA, 0x01 );
ScrollUp() or ScrollDown();
}
Ver 1.5
// Ext = 0
// Partial Display In Function
// Top_Block=0
// Bottom_Block=20
// Number of Specified Blocks=Bottom_Block=20
// Area Scroll Type=Top Screen Scroll
// Scroll Up or Scroll Down
71/94
2007/01/20
ST7626
void BottomScreenScroll( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xAA);
Write( DATA, 0x0a );
Write( DATA, 0x20 );
Write( DATA, 0x20 );
Write( DATA, 0x02 );
ScrollUp() or ScrollDown();
}
void WholeScreenScroll( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xAA);
Write( DATA, 0x00 );
Write( DATA, 0x20 );
Write( DATA, 0x20 );
Write( DATA, 0x03 );
ScrollUp() or ScrollDown();
}
void ScrollUp( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xAB);
Write( DATA, Top_Block);
Delay();
// Ext = 0
// Partial Display In Function
// Top_Block=10
// Bottom_Block=32
// Number of Specified Blocks=Bottom_Block=32
// Area Scroll Type=Bottom Screen Scroll
// Scroll Up or Scroll Down
// Ext = 0
// Partial Display In Function
// Top_Block=0
// Bottom_Block=32
// Number of Specified Blocks=Bottom_Block=32
// Area Scroll Type=Whole Screen Scroll
// Scroll Up or Scroll Down
// Ext = 0
// Scroll Start Set
// Start Block Address=Top_Block
// Delay
Write( COMMAND, 0x00AB);
Write( DATA, Top_Block +1 );
Delay();
// Scroll Start Set
// Start Block Address= Top_Block+1
// Delay
Write( COMMAND, 0x00AB);
Write( DATA, Top_Block +2 );
Delay();
……
……
Write( COMMAND, 0x00AB);
Write( DATA, Bottom_Block );
Delay();
// Scroll Start Set
// Start Block Address= Top_Block +2
// Delay
}
void ScrollDown( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0x00AB);
Write( DATA, Bottom_Block);
Delay();
// Scroll Start Set
// Start Block Address= Bottom_Block
// Delay
// Ext = 0
// Scroll Start Set
// Start Block Address= Bottom_Block
// Delay
Write( COMMAND, 0x00AB);
Write( DATA, Bottom_Block -1 );
Delay();
// Scroll Start Set
// Start Block Address= Bottom_Block -1
// Delay
Write( COMMAND, 0x00AB);
Write( DATA, Bottom_Block -2 );
Delay();
……
……
Write( COMMAND, 0x00AB);
Write( DATA, Top _Block );
Delay();
// Scroll Start Set
// Start Block Address= Bottom_Block -2
// Delay
// Scroll Start Set
// Start Block Address= Top_Block
// Delay
}
Ver 1.5
72/94
2007/01/20
ST7626
8.5.5 Read-Modify-Write Cycle
Figure 8.5.5.1 Read-Write-Modify Cycle
Example：Read-Write-Modify Cycle
void ReadModifyWriteIn( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xE0 );
}
void ReadModifyWriteOut( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xEE );
}
Ver 1.5
// Ext = 0
// Entry the Read-Modify-Write mode
// Ext = 0
// Out of partial display mode
73/94
2007/01/20
ST7626
extern unsigned char *display_pattern;
void main()
{
unsigned pixel, i;
Windowing( 11, 31, 80, 50 );
ReadModifyWriteIn();
// set the page and column range
// entry the Read-Modify-Write mode
for( i = 0 ; i < 1400 ; i++ )
{
Read( DATA );
pixel = Read( DATA );
pixel = pixel & 0x07ff;
Write( DATA, pixel );
}
// For dummy read
// Pixel read
// Pixel modify: red filter
ReadModifyWriteOut();
// Out of Read-Modify-Write mode
}
8.5.6 Power OFF
Power OFF
Normal State
Execute the “Sleep In Flow”
Keeping /RES Pin =“L”
Power Off (VDD-VSS)
End of Power OFF
VDD
/RES
tR > 12 ms
tR
Internal
State
Normal State
Reset
Power Off
Keep the /RES = Low
Figure 8.5.6.1 Power off
Ver 1.5
74/94
2007/01/20
ST7626
8.5.7 Sleep In/Out
Normal State
Sleep In Status
Start of Sleep In
Start of Sleep Out
Sleep In Sequencing :
[Display Off: AEH]
[Booster Off Only: 20H^03H]
[Set Sleep In Preparation: 04H^3FH]
Sleep Out Sequencing :
[Set Sleep Out Preparation: 04H^3EH]
[Set Analog Power Control: 20H^0BH]
Delay 500ms
[Set Sleep Out by Instruction: 94H]
[Set Sleep In by Instruction: 95H]
Delay 100ms
End of Sleep In
[Display On: AFH]
End of Sleep Out
Fig 8.5.7.1 Sleep In/Out Flow
Example：Sleep In Operation
void SleepIn( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0xae );
Write( COMMAND, 0x20);
Write( DATA, 0x03 );
Write( COMMAND, 0x04 );
Write( DATA, 0x3f );
Delay( 500ms);
Write( COMMAND, 0x95 );
}
// Ext = 0
// Display Off
// Power Control
// B/F/R = Off/On/On
// Sleep In Preparation
// Sleep In Sequencing
// Delay 500ms
// Sleep In
Example：Sleep Out Operation
void SleepOut( void )
{
Write( COMMAND, 0x30 );
Write( COMMAND, 0x04 );
Write( DATA, 0x3e );
Write( COMMAND, 0x20 );
Write( DATA, 0x0b );
Write( COMMAND, 0x94 );
Delay( 100ms );
Write( COMMAND, 0xaf );
}
Ver 1.5
// Ext = 0
// Sleep Out Preparation
// Sleep Out Sequencing
// Power Control
// B/F/R = On/On/On
// Sleep Out
// Delay 100ms
// Display On
75/94
2007/01/20
ST7626
9. LIMITING VALUES
In accordance with the Absolute Maximum Rating System of Bare Die; see notes 1 and 2.
Parameter
Symbol
Conditions
Unit
Power supply voltage
VDD, VDD1~VDD5
–0.5 ~ +4.0
V
Power supply voltage
VLCDIN
–0.5 ~ +20
V
Power supply voltage
V1, V2, V3, V4
0.3 to VLCDIN
V
Input voltage
VIN
–0.5 to VDD+0.5
V
Output voltage
VO
–0.5 to VDD+0.5
V
Operating temperature (die)
TOPR
–30 to +85
°C
Storage temperature (die)
TSTR
–40 to +125
°C
VLCD
V1 to V4
VDD
VDD
VSS
VSS
System (MPU) side
VSS
ST7626chip side
Notes
1. Stresses above those listed under Limiting Values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that
VLCDIN ≧ V0 ≧ V1 ≧ V2 ≧ V3 ≧ V4 ≧ VSS
Ver 1.5
76/94
2007/01/20
ST7626
10. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
11. DC CHARACTERISTICS
VDD = 1.8 V to 3.3V; VSS = 0 V; V0 = 3.76 to 18.0V; Tamb = -30℃ to +85℃; unless otherwise specified.
Item
Symbol
High-level Input Voltage
Rating
Condition
Units
Applicable
Pin
Min.
Typ.
Max.
VIHC
0.7 x VDD
—
VDD
V
*1
Low-level Input Voltage
VILC
VSS
—
0.3 x VDD
V
*1
High-level Output Voltage
VOHC
0.7 x VDD
—
VDD
V
*2
Low-level Output Voltage
VOLC
VSS
—
0.3 x VDD
V
*2
Input leakage current
ILI
VIN = VDD or VSS
-1.0
—
1.0
µA
*3
Output leakage current
ILO
VIN = VDD or VSS
-3.0
—
3.0
µA
*4
—
1
—
—
1.3
—
Ta = 25°C V0IN = 15.0
Liquid Crystal Driver ON
RON
Resistance
(Relative
V
To VSS)
V0IN = 8.0 V
KΩ
SEGn
COMn *5
Internal Oscillator
fOSC
—
5.39
12.02
kHz
*6
External Input
fCL
—
167.09
372.62
kHz
OSC
Oscillator
1/68 duty
Frequency
Ta = 25°C Internal OSC:
31 PWM
Frame frequency fFRAME
fFRAME = fOSC /(Duty+1)
Hz
External OSC:
fFRAME = fCL /[31*(Duty+1)]
Item
Operating Voltage (1)
Symbol
Rating
Condition
Units
Applicable Pin
3.4
V
VSS*7
—
3.4
V
VSS
—
—
20
V
VLCDOUT
—
—
20
V
VLCDIN
Min.
Typ.
Max.
(Relative to VSS)
1.7
—
(Relative to VSS)
2.4
VLCDOUT
(Relative To VSS)
VLCDIN
(Relative To VSS)
VDD
VDD1
Internal Power
VDD2
Operating Voltage (2)
VDD3
VDD4
VDD5
Supply Step-up output
voltage Circuit
Voltage regulator
Circuit Operating
Voltage
Ver 1.5
77/94
2007/01/20
ST7626
Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when
an external power supply is used .
Test pattern
Display Pattern
Normal(Bare die)
Power Down
(Bare die)
Symbol
ISS
Rating
Condition
Bare Die, VDD = 2.8 V, Booster x 5
@ 1/9 bias,1/68 duty,Vop=11V
ISS
Ta = 25°C
Units
Notes
—
µA
*8
10
µA
Min.
Typ.
Max.
—
350
—
—
Notes to the DC characteristics
1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load
Internal clock.
2. Power-down mode. During power down all static currents are switched off.
3. If external VLCD, the display load current is not transmitted to IDD.
4. VLCD external voltage applied to VLCDIN pin; VLCDIN disconnected from VLCDOUT
References for items market with *
*1 The A0, D0 to D5, D6, D7, SI, SCL, E_RD, RW_WR, /CS, RST terminals.
*2 The D0 to D7.
*3 The A0, E_RD, RW_WR, /CS, RST terminals.
*4 Applies when the D0 to D5, D6, D7, SI, SCL, terminals are in a high impedance state.
*5 These are the resistance values for when a 0.2 x V0 voltage is applied between the output terminal SEGn or COMn and
the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range.
RON = (0.2 V0 )/ ∆I (Where ∆I is the current that flows when 0.2 V0 is applied while the power supply is ON.)
*6 The relationship between the oscillator frequency and the frame rate frequency under CL dividing ratio setting = 00H.
*7 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
*8 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
Ver 1.5
78/94
2007/01/20
ST7626
12. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0
tAW8
tAH8
tAS8
/CS
tCYC8
tCCLR,tCCLW
/WR,/RD
tCCHR,tCCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Figure 12.1
(VDD=3.3V,Ta= –30 to 85°C)
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH8
10
—
tAS8
60
—
Address setup time
tAW8
0
—
System cycle time (WRITE)
tCYC8
180
—
tCCLW
60
—
/WR H pulse width (WRITE)
tCCHW
120
—
System cycle time (READ)
tCYC8
200
—
tCCLR
80
—
/RD H pulse width (READ)
tCCHR
120
—
WRITE data setup time
tDS8
60
—
tDH8
10
—
Address hold time
Address setup time
/WR L pulse width (WRITE)
/RD L pulse width (READ)
WRITE data hold time
READ access time
READ Output disable time
Ver 1.5
A0
WR
RD
D0 to D7
tACC8
CL = 100 pF
—
70
tOH8
CL = 100 pF
—
60
79/94
Units
ns
2007/01/20
ST7626
(VDD=2.8V,Ta= –30 to 85°C)
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH8
10
—
tAS8
80
—
Address setup time
tAW8
0
—
System cycle time (WRITE)
tCYC8
220
—
tCCLW
80
—
/WR H pulse width (WRITE)
tCCHW
140
—
System cycle time (READ)
tCYC8
280
—
tCCLR
100
—
/RD H pulse width (READ)
tCCHR
180
—
WRITE data setup time
tDS8
80
—
tDH8
10
—
Address hold time
Address setup time
/WR L pulse width (WRITE)
/RD L pulse width (READ)
WRITE data hold time
READ access time
A0
WR
RD
D0 to D7
READ Output disable time
tACC8
CL = 100 pF
—
75
tOH8
CL = 100 pF
—
65
Units
ns
(VDD=1.8V,Ta= –30 to 85°C )
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH8
10
—
tAS8
180
—
Address setup time
tAW8
30
—
System cycle time (WRITE)
tCYC8
430
—
tCCLW
150
—
/WR H pulse width (WRITE)
tCCHW
280
—
System cycle time (READ)
tCYC8
450
—
tCCLR
190
—
/RD H pulse width (READ)
tCCHR
230
—
WRITE data setup time
tDS8
150
—
tDH8
10
—
Address hold time
Address setup time
/WR L pulse width (WRITE)
/RD L pulse width (READ)
WRITE data hold time
READ access time
READ Output disable time
A0
WR
RD
D0 to D7
tACC8
CL = 100 pF
—
100
tOH8
CL = 100 pF
—
80
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between /CS being “L” and WR and RD being at the “L” level.
Ver 1.5
80/94
2007/01/20
ST7626
System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0
R/W
tAW6
tAH6
tAS6
/CS1
tCYC6
tCCLR,tCCLW
E
tCCHR,tCCHW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Figure 12.2
(VDD=3.3V,Ta= –30 to 85°C )
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH6
10
—
tAS6
60
—
Address setup time
tAW6
0
—
System cycle time (WRITE)
tCYC6
180
—
tCCLW
120
—
Enable H pulse width (WRITE)
tCCHW
60
—
System cycle time (READ)
tCYC6
200
—
tCCLR
120
—
Enable H pulse width (READ)
tCCHR
80
—
WRITE data setup time
tDS6
60
—
tDH6
10
—
Address hold time
Address setup time
Enable L pulse width (WRITE)
Enable L pulse width (READ)
WRITE data hold time
READ access time
READ Output disable time
Ver 1.5
A0
WR
RD
D0 to D7
tACC6
CL = 100 pF
—
70
tOH6
CL = 100 pF
—
60
81/94
Units
ns
2007/01/20
ST7626
(VDD=2.8V,Ta= –30 to 85°C )
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH6
10
—
tAS6
80
—
Address setup time
tAW6
0
—
System cycle time (WRITE)
tCYC6
220
—
tCCLW
140
—
Enable H pulse width (WRITE)
tCCHW
80
—
System cycle time (READ)
tCYC6
220
—
tCCLR
120
—
Enable H pulse width (READ)
tCCHR
100
—
WRITE data setup time
tDS6
80
—
tDH6
10
—
Address hold time
Address setup time
Enable L pulse width (WRITE)
Enable L pulse width (READ)
WRITE data hold time
READ access time
A0
WR
RD
D0 to D7
READ Output disable time
tACC6
CL = 100 pF
—
75
tOH6
CL = 100 pF
—
65
Units
ns
(VDD=1.8V,Ta= –30 to 85°C )
Item
Signal
Symbol
Condition
Rating
Min.
Max.
tAH6
10
—
tAS6
180
—
Address setup time
tAW6
30
—
System cycle time (WRITE)
tCYC6
430
—
tCCLW
280
—
Enable H pulse width (WRITE)
tCCHW
150
—
System cycle time (READ)
tCYC6
400
—
tCCLR
220
—
Enable H pulse width (READ)
tCCHR
180
—
WRITE data setup time
tDS6
150
—
tDH6
10
—
Address hold time
Address setup time
Enable L pulse width (WRITE)
Enable L pulse width (READ)
WRITE data hold time
READ access time
READ Output disable time
A0
WR
RD
D0 to D7
tACC6
CL = 100 pF
—
100
tOH6
CL = 100 pF
—
80
Units
ns
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tEWLW and tEWLR are specified as the overlap between /CS being “L” and E.
Ver 1.5
82/94
2007/01/20
ST7626
Serial Interface Characteristics (For 4-Line Interface)
tCSS
tCSH
/CS1
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
Fig 12.3
(VDD=3.3V,Ta= –30 to 85°C )
Item
Signal
Serial clock period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
A0
SI
Data hold time
CS-SCL setup time
CS-SCL hold time
/CS
Symbol
Condition
Rating
Min.
Max.
tSCYC
80
—
tSHW
40
—
tSLW
40
—
tSAS
10
—
tSAH
10
—
tSDS
10
—
tSDH
30
—
tCSS
20
—
tCSH
30
—
Units
ns
(VDD=2.8V,Ta= –30 to 85°C )
Item
Signal
Serial clock period
SCL “H” pulse width
SCL
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL setup time
CS-SCL hold time
Ver 1.5
A0
SI
/CS
Symbol
Condition
Rating
Min.
Max.
tSCYC
100
—
tSHW
50
—
tSLW
50
—
tSAS
10
—
tSAH
10
—
tSDS
10
—
tSDH
30
—
tCSS
20
—
tCSH
40
—
83/94
Units
ns
2007/01/20
ST7626
(VDD=1.8V,Ta= –30 to 85°C )
Item
Signal
Serial clock period
SCL
SCL “H” pulse width
SCL “L” pulse width
Address setup time
A0
Address hold time
Data setup time
SI
Data hold time
CS-SCL time
/CS
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
180
—
tSHW
90
—
tSLW
90
—
tSAS
10
—
tSAH
50
—
tSDS
10
—
tSDH
45
—
tCSS
10
—
tCSH
80
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Serial Interface Characteristics (For 3-Line Interface)
tCSS
tCSH
/CS1
tSCYC
tSLW
SCL
tSHW
tf
tSDS
tr
tSDH
SI
Fig 12.4
Ver 1.5
84/94
2007/01/20
ST7626
(VDD=3.3V,Ta= –30 to 85°C )
Item
Signal
Serial clock period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL setup time
CS-SCL hold time
/CS
Symbol
Condition
Rating
Min.
Max.
tSCYC
80
—
tSHW
40
—
tSLW
40
—
tSDS
10
—
tSDH
30
—
tCSS
20
—
tCSH
50
—
Units
ns
(VDD=2.8V,Ta= –30 to 85°C )
Item
Signal
Serial clock period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
SI
Data hold time
CS-SCL time
/CS
CS-SCL time
Symbol
Condition
Rating
Min.
Max.
tSCYC
100
—
tSHW
50
—
tSLW
50
—
tSDS
10
—
tSDH
30
—
tCSS
20
—
tCSH
50
—
Units
ns
(VDD=1.8V,Ta= –30 to 85°C )
Item
Signal
Serial clock period
SCL “H” pulse width
SCL
SCL “L” pulse width
Data setup time
Data hold time
CS-SCL time
CS-SCL time
SI
/CS
Symbol
Condition
Rating
Min.
Max.
tSCYC
180
—
tSHW
90
—
tSLW
90
—
tSDS
10
—
tSDH
45
—
tCSS
10
—
tCSH
80
—
Units
ns
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
Ver 1.5
85/94
2007/01/20
ST7626
13. RESET TIMING
tRW
/RES
tR
Internal
status
During reset
Reset complete
Fig 13.1
(VDD = 3.3V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
1
us
tRW
1.2
—
—
us
(VDD = 2.8V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
1.5
us
tRW
1.5
—
—
us
(VDD = 1.8V , Ta = –30 to 85°C )
Item
Signal
Reset time
Reset “L” pulse width
Ver 1.5
RESB
Symbol
Condition
Rating
Units
Min.
Typ.
Max.
tR
—
—
2
us
tRW
2
—
—
us
86/94
2007/01/20
ST7626
14. THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7626 Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial
interface it is possible to operate the ST7626 series chips with fewer signal lines.
The display area can be enlarged by using multiple ST7626 Series chips. When this is done, the chip select signal can be
used to select the individual Ics to access.
(1) 8080 Series MPUs
VDD
VCC
VDD
A0
A0
CS1
DO to D7
RD
WR
RES
GND
D0 to D7
/RD (E)
/WR (R/W)
/RES
VSS
RESET
ST7626
MPU
CS1
IF1
IF2
IF3
VSS
(2) 6800 Series MPUs
V DD
V DD
A0
A0
CS1
CS1
DO to D7
RD
WR
RES
GND
IF1
IF2
IF3
D0 to D7
E(/RD)
R/W (/W R)
/RES
V SS
RESET
ST7626
MPU
V CC
V SS
(3) Using the Serial Interface (4-line interface)
V DD
V CC
V DD
A0
CS1
CS1
IF1
IF2
IF3
Port 1
Port 2
RES
GND
ST7626
MPU
A0
SI
SCL
/RES
V SS
RESET
V SS
Ver 1.5
87/94
2007/01/20
ST7626
(4) Using the Serial Interface (3-line interface)
V DD or V SS
V CC
V DD
IF1
IF2
IF3
CS1
Port 1
Port 2
RES
GND
ST7626
MPU
CS1
SI
SCL
/RES
V SS
RESET
V SS
Ver 1.5
88/94
2007/01/20
ST7626
Application Circuits
( A ) 80 Series 16-bit Parallel Interface:
Interface : 8080series-16bits
VDD1(VDD,VDD1)=1.8~3.3V
VDD2(VDD2~VDD5)=2.4~3.3V
CSEL=H (Interlace Mode)
IF1=H;IF2=H;IF3=H
C0: 1.0~2.2uF/25V
Ver 1.5
89/94
2007/01/20
ST7626
( B ) 80 Series 8-bit Parallel Interface:
Interface : 8080series-8bits
VDD1(VDD,VDD1)=1.8~3.3V
VDD2(VDD2~VDD5)=2.4~3.3V
CSEL=H (Interlace Mode)
IF1=H;IF2=H;IF3=L
C0: 1.0~2.2uF/25V
Ver 1.5
90/94
2007/01/20
ST7626
( C ) 3 Line Serial Peripheral Interface:
Interface : 9-bit Serial(3-Line)
VDD1(VDD,VDD1)=1.8~3.3V
VDD2(VDD2~VDD5)=2.4~3.3V
CSEL=H (Interlace Mode)
IF1=L;IF2=L;IF3=H
C0: 1.0~2.2uF/25V
Ver 1.5
91/94
2007/01/20
ST7626
( D ) 4 Line Serial Peripheral Interface:
Interface : 8-bit Serial(4-Line)
VDD1(VDD,VDD1)=1.8~3.3V
VDD2(VDD2~VDD5)=2.4~3.3V
CSEL=H (Interlace Mode)
IF1=L;IF2=L;IF3=L
C0: 1.0~2.2uF/25V
Ver 1.5
92/94
2007/01/20
ST7626
16. Application Note of VLCD and Vop (V0) ITO Layout
When using internal voltage generator, VLCDIN、VLCDOUT must be connected together. V0IN
and V0OUT must be connected together too. In the following is the ITO layout for VLCDIN、
VLCDOUT、V0IN and V0OUT individually. Please follow the way as below for these two LCD
power voltages.
NOTE:
Microprocessor interfece pins should not be floating in any operation mode.
Ver 1.5
93/94
2007/01/20
ST7626
ST7626 Serial Specification Revision History
Version
Date
0.x
--
Preliminary version
1.0
2006/04/10 First issue.
1.1
2006/5/23
1.2
1.3
Ver 1.5
Description
Change the limitation voltage (P77):
VDD, VDD1=1.7V~3.4V
VDD2,VDD3, VDD4, VDD5=2.4V~3.4V
Change write EEPROM example program ( P.43)
Add microprossoer notice item (P.13,P93)
Add Vref Pin notice item (P.14,P11)
2006/09/25
Modifty Application circuit vref Pin section (P89, P90,P91,P92 )
2006/7/23
1.4
2006/10/31 Modifty page 67: ST7626 initial code example program
1.5
2007/01/20 Modifty page application circuit : page 89~page 93
94/94
2007/01/20