CYPRESS CY7C109BN

CY7C109BN
CY7C1009BN
128K x 8 Static RAM
Functional Description[1]
Features
• High speed
The CY7C109BN/CY7C1009BN is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable One (CE1) and
Write Enable (WE) inputs LOW and Chip Enable Two (CE2)
input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is
then written into the location specified on the address pins (A0
through A16).
— tAA = 12 ns
• Low active power
— 495 mW (max. 12 ns)
• Low CMOS standby power
— 55 mW (max.) 4 mW
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Reading from the device is accomplished by taking Chip
Enable One (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE2) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The CY7C109BN is available in standard 400-mil-wide SOJ
and 32-pin TSOP type I packages. The CY7C1009BN is
available in a 300-mil-wide SOJ package. The CY7C1009BN
and CY7C109BN are functionally equivalent in all other
respects.
Logic Block Diagram
Pin Configurations
SOJ
Top View
NC
A16
A14
A12
A7
A6
A5
A4
A3
I/O0
A2
A1
INPUT BUFFER
SENSE AMPS
512 x 256 x 8
ARRAY
I/O3
I/O4
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
OE
I/O0
I/O1
I/O2
GND
I/O2
I/O5
CE1
CE2
WE
A0
I/O1
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TSOP I
Top View
(not to scale)
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06430 Rev. **
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 1, 2006
CY7C109BN
CY7C1009BN
Selection Guide
7C109B-12
7C1009B-12
7C109B-15
7C1009B-15
7C109B-20
7C1009B-20
Unit
Maximum Access Time
12
15
20
ns
Maximum Operating Current
90
80
75
mA
Maximum CMOS Standby Current
10
10
10
mA
2
2
2
mA
L
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-Up Current ..................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[2] .... –0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State[2] ....................................–0.5V to VCC + 0.5V
Commercial
DC Input Voltage[2] .................................–0.5V to VCC + 0.5V
Industrial
Ambient
Temperature
VCC
0°C to +70°C
5V ± 10%
−40°C to +85°C
5V ± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
Voltage[2]
7C109BN-12
7C1009BN-12
7C109BN-15
7C1009BN-15
7C109BN-20
7C1009BN-20
Min.
Min.
Min.
Max.
2.4
Max.
2.4
Max.
2.4
0.4
0.4
Unit
V
0.4
V
2.2
VCC + 0.3
2.2
VCC + 0.3
2.2
VCC + 0.3
V
–0.3
0.8
–0.3
0.8
–0.3
0.8
V
VIL
Input LOW
IIX
Input Leakage
Current
GND < VI < VCC
–1
+1
–1
+1
–1
+1
µA
IOZ
Output Leakage
Current
GND < VI < VCC,
Output Disabled
–5
+5
–5
+5
–5
+5
µA
IOS
Output Short
Circuit Current[3]
VCC = Max., VOUT = GND
–300
–300
–300
mA
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
90
80
75
mA
ISB1
Max. VCC, CE1 > VIH
Automatic CE
Power-Down Current or CE2 < VIL, VIN > VIH or
—TTL Inputs
VIN < VIL, f = fMAX
45
40
30
mA
ISB2
Automatic CE
Max. VCC,
Power-Down Current CE1 > VCC – 0.3V,
or CE2 < 0.3V,
—CMOS Inputs
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
10
10
mA
2
2
2
mA
L
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
9
pF
8
pF
Notes:
2. Minimum voltage is –2.0V for pulse durations of less than 20 ns.
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06430 Rev. **
Page 2 of 9
CY7C109BN
CY7C1009BN
AC Test Loads and Waveforms
ALL INPUT PULSES
R1 480Ω
R1 480Ω
5V
3.0V
5V
OUTPUT
90%
OUTPUT
30 pF
R2
255Ω
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
5 pF
90%
10%
10%
GND
≤ 3 ns
INCLUDING
JIG AND
SCOPE
(b)
≤ 3 ns
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Equivalent to:
Switching Characteristics[5] Over the Operating Range
Parameter
Description
7C109BN-12
7C1009BN-12
7C109BN-15
7C1009BN-15
7C109BN-20
7C1009BN-20
Min.
Min.
Min.
Max.
Max.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
12
15
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
6
7
8
ns
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[6, 7]
8
ns
tLZCE
CE1 LOW to Low Z, CE2 HIGH to Low Z[7]
12
3
15
3
0
3
tHZCE
CE1 HIGH to High Z, CE2 LOW to High
tPU
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
tPD
CE1 HIGH to Power-Down, CE2 LOW to
Power-Down
0
12
ns
3
7
ns
8
ns
20
ns
0
15
ns
ns
0
3
0
20
7
6
ns
3
0
6
Z[6, 7]
20
ns
Write Cycle[8]
tWC
Write Cycle Time[9]
12
15
20
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
10
12
15
ns
tAW
Address Set-Up to Write End
10
12
15
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
10
12
12
ns
tSD
Data Set-Up to Write End
7
8
10
ns
tHD
Data Hold from Write End
0
0
0
ns
tLZWE
WE HIGH to Low Z[7]
3
3
3
ns
tHZWE
WE LOW to High Z[6, 7]
6
7
8
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a
write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the
signal that terminates the write.
9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06430 Rev. **
Page 3 of 9
CY7C109BN
CY7C1009BN
Data Retention Characteristics Over the Operating Range (Low Power version only)
Parameter
Description
Conditions
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data Retention Time
tR
Operation Recovery Time
Min.
No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Max
2.0
Unit
V
150
µA
0
ns
200
µs
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1[10, 11]
tRC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[11, 12]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
ICC
50%
ISB
Notes:
10. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 001-06430 Rev. **
Page 4 of 9
CY7C109BN
CY7C1009BN
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled)[13, 14]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tAW
tHA
tPWE
WE
tSD
DATA I/O
tHD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[13, 14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
DATAIN VALID
NOTE 15
tHZOE
Notes:
13. Data I/O is high impedance if OE = VIH.
14. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
15. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 001-06430 Rev. **
Page 5 of 9
CY7C109BN
CY7C1009BN
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[14]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
tSD
NOTE 15
DATA I/O
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE1
CE2
OE
WE
H
X
X
X
High Z
Power-Down
Standby (ISB)
X
L
X
X
High Z
Power-Down
Standby (ISB)
L
H
L
H
Data Out
Read
Active (ICC)
L
H
X
L
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Document #: 001-06430 Rev. **
I/O0–I/O7
Mode
Power
Page 6 of 9
CY7C109BN
CY7C1009BN
Ordering Information
Speed
(ns)
12
15
20
Package
Diagram
Ordering Code
CY7C109BN-12VC
51-85032
Operating
Range
Package Type
32-Lead (400-Mil) Molded SOJ
CY7C1009BN-12VC
51-85031
32-Lead (300-Mil) Molded SOJ
CY7C109BN-12ZC
51-85056
32-Lead TSOP Type I
CY7C109BN-12ZXC
51-85056
32-Lead TSOP Type I (Pb-free)
CY7C109BNL-15VC
51-85032
32-Lead (400-Mil) Molded SOJ
CY7C109BN-15VC
51-85032
32-Lead (400-Mil) Molded SOJ
CY7C1009BN-15VC
51-85031
32-Lead (300-Mil) Molded SOJ
CY7C109BN-15ZC
51-85056
32-Lead TSOP Type I
CY7C109BN-15ZXC
51-85056
32-Lead TSOP Type I (Pb-free)
CY7C109BN-15VI
51-85032
32-Lead (400-Mil) Molded SOJ
CY7C1009BN-15VI
51-85031
32-Lead (300-Mil) Molded SOJ
CY7C109BN-20VC
51-85032
32-Lead (400-Mil) Molded SOJ
CY7C1009BN-20VC
51-85031
32-Lead (300-Mil) Molded SOJ
Commercial
Commercial
Industrial
Commercial
CY7C109BN-20VI
51-85032
32-Lead (400-Mil) Molded SOJ
Industrial
CY7C109BN-20ZC
51-85056
32-Lead TSOP Type I
Commercial
CY7C109BN-20ZXC
51-85056
32-Lead TSOP Type I (Pb-free)
Please contact local sales representative regarding availability of these parts
Package Diagrams
28-Lead (400-Mil) Molded SOJ (51-85032)
PIN 1 I.D
14
1
.395
.405
15
DIMENSIONS IN INCHES
.435
.445
MIN.
MAX.
28
.720
.730
SEATING PLANE
.128
.148
.026
.032
.050
TYP.
.015
.020
Document #: 001-06430 Rev. **
.007
.013
0.004
.025 MIN.
.360
.380
51-85032-*B
Page 7 of 9
CY7C109BN
CY7C1009BN
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ (51-85031)
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
MAX.
3. DIMENSIONS IN INCHES
DETAIL
A
EXTERNAL LEAD DESIGN
PIN 1 ID
14
1
0.291
0.300
15
0.330
0.350
28
OPTION 1
0.697
0.713
0.014
0.020
OPTION 2
SEATING PLANE
0.120
0.140
0.050
TYP.
0.026
0.032
0.013
0.019
A
0.007
0.013
0.004
0.025 MIN.
0.262
0.272
51-85031-*C
32-Lead TSOP I (8x20 mm) (51-85056)
51-85056-*D
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 001-06430 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C109BN
CY7C1009BN
Document History Page
Document Title: CY7C109BN/CY7C1009BN 128K x 8 Static RAM
Document Number: 001-06430
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
423847
See ECN
NXR
Document #: 001-06430 Rev. **
Description of Change
New Data Sheet
Page 9 of 9