FDS3572
N-Channel PowerTrench® MOSFET
80V, 8.9A, 16mΩ
Features
Applications
• rDS(ON) = 14mΩ (Typ.), VGS = 10V, ID = 8.9A
• Primary switch for Isolated DC/DC converters
• Qg(tot) = 31nC (Typ.), VGS = 10V
• Distributed Power and Intermediate Bus Architectures
• Low Miller Charge
• High Voltage Synchronous Rectifier for DC Bus
Converters
• Low QRR Body Diode
• Optimized efficiency at high frequencies
• UIS Capability (Single Pulse and Repetitive Pulse)
Formerly developmental type 82663
Branding Dash
5
1
2
3
4
5
4
6
3
7
2
8
1
SO-8
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
80
Units
V
VGS
Gate to Source Voltage
±20
V
Drain Current
ID
Continuous (TA = 25oC, VGS = 10V, RθJA = 50oC/W)
8.9
A
Continuous (TA = 100oC, VGS = 10V, RθJA = 50oC/W)
5.6
A
Pulsed
EAS
PD
TJ, TSTG
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
515
mJ
Power dissipation
2.5
W
Derate above 25oC
20
mW/oC
Operating and Storage Temperature
o
-55 to 150
C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case (Note 2)
25
o
C/W
RθJA
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)
50
oC/W
RθJA
Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)
85
o
C/W
Package Marking and Ordering Information
Device Marking
FDS3572
©2003 Fairchild Semiconductor Corporation
Device
FDS3572
Package
SO-8
Reel Size
330mm
Tape Width
12mm
Quantity
2500 units
FDS3572 Rev. A
FDS3572
November 2003
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
80
-
-
-
V
-
1
-
-
250
VGS = ±20V
-
-
±100
nA
V
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 60V
VGS = 0V
TA = 150oC
µA
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
2
-
4
ID = 8.9A, VGS = 10V
-
0.014
0.016
ID = 5.6A, VGS = 6V
-
0.019
0.029
ID = 8.9A, VGS = 10V,
TA= 150oC
-
0.027
0.032
-
1990
-
pF
-
320
-
pF
-
85
-
pF
-
31
41
nC
-
4
5.2
nC
-
9
-
nC
-
5
-
nC
-
7.5
-
nC
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(tot)
Total Gate Charge at 10V
VGS = 0V to 10V
VGS = 0V to 2V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
Switching Characteristics
VDS = 25V, VGS = 0V,
f = 1MHz
VDD = 40V
ID = 8.9A
Ig = 1.0mA
(VGS = 10V)
tON
Turn-On Time
-
-
40
ns
td(ON)
Turn-On Delay Time
-
13
-
ns
tr
Rise Time
-
14
-
ns
td(OFF)
Turn-Off Delay Time
-
31
-
ns
tf
Fall Time
-
13
-
ns
tOFF
Turn-Off Time
-
-
67
ns
V
VDD = 40V, ID = 8.9A
VGS = 10V, RGS = 10Ω
Drain-Source Diode Characteristics
ISD = 8.9A
-
-
1.25
ISD = 4.3A
-
-
1.0
V
Reverse Recovery Time
ISD= 8.9A, dISD/dt= 100A/µs
-
-
50
ns
Reverse Recovered Charge
ISD= 8.9A, dISD/dt= 100A/µs
-
-
70
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: Starting TJ = 25°C, L = 21mH, IAS = 7A.
2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. RθJC is guaranteed by design while RθJA is determined by the user’s board design.
3: RθJA is measured with 1.0 in2 copper on FR-4 board
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
FDS3572
Electrical Characteristics TA = 25°C unless otherwise noted
10
VGS = 10V
1.0
8
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
6
4
2
0.2
RθJA=50oC/W
0
0
0
25
50
75
100
125
150
25
50
TA , AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
2
100
125
0.1
150
Figure 2. Maximum Continuous Drain Current vs
Ambient Temperature
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
1
ZθJA, NORMALIZED
THERMAL IMPEDANCE
75
TA , AMBIENT TEMPERATURE (oC)
RθJA=50oC/W
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.001
10-5
10-4
10-3
10-2
10-1
100
t, RECTANGULAR PULSE DURATION (s)
101
102
103
Figure 3. Normalized Maximum Transient Thermal Impedance
1000
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I = I25
VGS = 10V
150 - TA
125
100
10
5
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
102
103
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
FDS3572
Typical Characteristics TA = 25°C unless otherwise noted
FDS3572
Typical Characteristics TA = 25°C unless otherwise noted
20
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
ID , DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
50
10
STARTING TJ = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
15
TJ = 150oC
10
TJ = -55oC
TJ = 25oC
5
STARTING TJ = 150oC
0
1
1
0.1
10
3.0
100
3.5
tAV, TIME IN AVALANCHE (ms)
Figure 5. Unclamped Inductive Switching
Capability
5.0
5.5
20
VGS = 10V
DRAIN TO SOURCE ON RESISTANCE (m Ω)
20
VGS = 6V
VGS = 5V
ID, DRAIN CURRENT (A)
4.5
Figure 6. Transfer Characteristics
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
15
VGS = 4.5V
10
5
TA = 25oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
VGS = 6V
18
16
VGS = 10V
14
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
12
0
0.25
0.5
0.75
1.0
0
2
VDS , DRAIN TO SOURCE VOLTAGE (V)
4
6
8
10
ID, DRAIN CURRENT (A)
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Drain
Current
2.0
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = VDS, ID = 250µA
1.1
NORMALIZED GATE
THRESHOLD VOLTAGE
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
4.0
VGS , GATE TO SOURCE VOLTAGE (V)
1.5
1.0
1.0
0.9
0.8
0.7
VGS = 10V, ID = 8.9A
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
©2003 Fairchild Semiconductor Corporation
160
0.6
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
FDS3572 Rev. A
FDS3572
Typical Characteristics TA = 25°C unless otherwise noted
1.2
5000
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
1.1
1.0
1000
CISS = CGS + CGD
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
0.9
-80
-40
0
40
80
120
10
0.1
160
1
TJ , JUNCTION TEMPERATURE (oC)
10
80
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
VGS , GATE TO SOURCE VOLTAGE (V)
10
VDD = 40V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 8.9A
ID = 1A
2
0
0
10
20
30
40
Qg, GATE CHARGE (nC)
Figure 13. Gate Charge Waveforms for Constant Gate Currents
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
FDS3572
Test Circuits and Waveforms
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 14. Unclamped Energy Test Circuit
Figure 15. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS
VGS
VGS = 10V
+
Qgs2
VDD
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 16. Gate Charge Test Circuit
Figure 17. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 18. Switching Time Test Circuit
©2003 Fairchild Semiconductor Corporation
10%
Figure 19. Switching Time Waveforms
FDS3572 Rev. A
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
(T
–T )
JM
A
P
DM = -----------------------------R θJA
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
R
26
(EQ. 2)
θ JA = 64 + ------------------------------0.23 + Area
(EQ. 1)
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
4. The use of thermal vias.
200
5. Air flow and board orientation.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
RθJA = 64 + 26/(0.23+Area)
RθJA (oC/W)
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
150
100
50
0.001
0.01
0.1
1
AREA, TOP COPPER AREA (in2)
10
Figure 21. Thermal Resistance vs Mounting
Pad Area
ZθJA, THERMAL
IMPEDANCE (oC/W)
150
120
90
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
102
103
Figure 22. Thermal Impedance vs Mounting Pad Area
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
FDS3572
Thermal Resistance vs. Mounting Pad Area
FDS3572
PSPICE Electrical Model
.SUBCKT FDS3572 2 1 3 ;
Ca 12 8 7e-10
Cb 15 14 7e-10
Cin 6 8 1.9e-9
rev November 2003
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
Ebreak 11 7 17 18 86.6
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
5
51
EVTHRES
+ 19 8
+
LGATE
GATE
1
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
RSLC2
It 8 17 1
Lgate 1 9 1e-9
Ldrain 2 5 1e-9
Lsource 3 7 0.1e-9
RLDRAIN
RSLC1
51
EVTEMP
RGATE +
18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
RLgate 1 9 10
RLdrain 2 5 10
RLsource 3 7 1
LSOURCE
CIN
8
7
SOURCE
3
RSOURCE
RLSOURCE
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
14
13
13
8
S1B
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 5.5e-3
Rgate 9 20 1.3
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 5.5e-3
Rvthres 22 8 Rvthresmod 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
IT
14
+
+
-
+
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),2.5))}
.MODEL DbodyMOD D (IS=4.5E-12 RS=4.7e-3 TRS1=1.5e-3 TRS2=2e-5 XTI=3 CJO=1.4e-9 TT=3e-08 M=0.55)
.MODEL DbreakMOD D (RS=2.5 TRS1=1e-4 TRS2=1e-6)
.MODEL DplcapMOD D (CJO=4.6e-10 IS=1e-30 N=10 M=0.5)
.MODEL MmedMOD NMOS (VTO=3.35 KP=3 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.3 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=3.9 KP=60 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=2.88 kp=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=13 RS=0.1 T_ABS=25)
.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7.5e-7)
.MODEL RdrainMOD RES (TC1=4.8e-3 TC2=3e-5)
.MODEL RSLCMOD RES (TC1=2.4e-2 TC2=1e-7)
.MODEL RsourceMOD RES (TC1=1e-2 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.4e-3 TC2=-1.4e-5)
.MODEL RvtempMOD RES (TC1=-4e-3 TC2=2e-7)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-4.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0 VOFF=-0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
FDS3572
SABER Electrical Model
REV November 2003
template FDS3572 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=4.5e-12,rs=4.7e-3,trs1=1.5e-3,trs2=2e-5,xti=3,cjo=1.4e-9,tt=3e-08,m=0.55)
dp..model dbreakmod = (rs=2.5,trs1=1e-4,trs2=1e-6)
dp..model dplcapmod = (cjo=4.6e-10,isl=10e-30,nl=10,m=0.5)
m..model mmedmod = (type=_n,vto=3.35,kp=3,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.9,kp=60,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=2.88,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4.0,voff=-2.0)
DPLCAP 5
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-4.0)
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0,voff=-0.5)
RSLC1
51
c.ca n12 n8 = 7e-10
RSLC2
c.cb n15 n14 = 7e-10
ISCL
c.cin n6 n8 = 1.9e-9
spe.ebreak n11 n7 n17 n18 = 86.6
GATE
spe.eds n14 n8 n5 n8 = 1
1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
EVTEMP
RGATE + 18 22
9
20
21
RLDRAIN
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
DRAIN
2
DBREAK
50
-
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
LDRAIN
CIN
8
LSOURCE
SOURCE
3
7
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A
12
l.lgate n1 n9 = 1e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 0.1e-9
13
8
RBREAK
15
14
13
S1B
CA
res.rlgate n1 n9 = 10
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 1
S2A
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
VBAT
5
8
EDS
-
IT
14
+
+
-
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7.5e-7
res.rdrain n50 n16 = 5.5e-3, tc1=4.8e-3,tc2=3e-5
res.rgate n9 n20 = 1.3
res.rslc1 n5 n51 = 1e-6, tc1=2.4e-2,tc2=1e-7
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.5e-3, tc1=1e-2,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.4e-3,tc2=-1.4e-5
res.rvtemp n18 n19 = 1, tc1=-4e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/250))** 2.5))
}
}
©2003 Fairchild Semiconductor Corporation
FDS3572 Rev. A
JUNCTION
th
REV Nov 2003
FDS3572
Copper Area =1.0 in2
CTHERM1 TH 8 2.0e-3
CTHERM2 8 7 5.0e-3
CTHERM3 7 6 1.0e-2
CTHERM4 6 5 4.0e-2
CTHERM5 5 4 9.0e-2
CTHERM6 4 3 2e-1
CTHERM7 3 2 1
CTHERM8 2 TL 3
FDS3572
SPICE Thermal Model
RTHERM1
CTHERM1
8
RTHERM2
RTHERM1 TH 8 1e-1
RTHERM2 8 7 5e-1
RTHERM3 7 6 1
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 12
RTHERM7 3 2 18
RTHERM8 2 TL 25
RTHERM3
SABER Thermal Model
RTHERM4
CTHERM2
7
CTHERM3
6
CTHERM4
2
Copper Area = 1.0 in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 =2.0e-3
ctherm.ctherm2 8 7 =5.0e-3
ctherm.ctherm3 7 6 =1.0e-2
ctherm.ctherm4 6 5 =4.0e-2
ctherm.ctherm5 5 4 =9.0e-2
ctherm.ctherm6 4 3 =2e-1
ctherm.ctherm7 3 2 1
ctherm.ctherm8 2 tl 3
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
rtherm.rtherm1 th 8 =1e-1
rtherm.rtherm2 8 7 =5e-1
rtherm.rtherm3 7 6 =1
rtherm.rtherm4 6 5 =5
rtherm.rtherm5 5 4 =8
rtherm.rtherm6 4 3 =12
rtherm.rtherm7 3 2 =18
rtherm.rtherm8 2 tl =25
}
RTHERM7
CTHERM7
2
CTHERM8
RTHERM8
tl
CASE
TABLE 1. THERMAL MODELS
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
1.2e-1
1.5e-1
2.0e-1
2.0e-1
2.0e-1
CTHERM7
0.5
1.0
1.0
1.0
1.0
CTHERM8
1.3
2.8
3.0
3.0
3.0
RTHERM6
26
20
15
13
12
RTHERM7
39
24
21
19
18
RTHERM8
55
38.7
31.3
29.7
25
COMPONANT
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FDS3572 Rev. A
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Rev. I7