ADS-238Q 12-Bit, 20MHz, Low Power Sampling A/D Converters INNOVATION and EXCELLENCE FEATURES · · · · · · · 20MHz sampling rate Low Power, 100mW, max 100MHz full power input bandwidth Integral sample-and-hold Single +3V supply operation TTL compatible digital output Offset binary output coding INPUT/OUTPUT CONNECTIONS GENERAL DESCRIPTION The ADS-238Q is a monolithic, 12-bit, 20MHz, sampling analog-to-digital converter fabricated in a CMOS process. The converter is designed for applications where high speed, wide bandwidth and low power dissipation are essential. These characteristics are provided through the use of a fully differential pipeline A/D architecture with digital error correction logic for the eleven most significant bits. The ADS-238Q offers excellent dynamic performance while consuming only 79mW, typical. The power dissipation is approximately proportional to the sampling rate, thus the ADS-238Q is ideal for low power applications between 1 and 20 MHz. With low distortion and high dynamic range, this device provides the performance required for imaging, telecommunications, multimedia, and instrumentation applications. The ADS-238Q is available in a 44-pin (plastic) TQFP package and operates over the commercial 0°C to 70°C temperature range. PIN FUNCTION PIN FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND CLK N.C. VS VS VS VS VS VS VREF– VREF+ N.C. N.C. N.C. GND BIAS1 BIAS2 VCM GND VIN+ VIN– GND 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VS BIT 12 (LSB) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 GND GND GND GND GND GND GND GND GND Note: Recommend that N.C. (no connect) pins be connected to analog ground. 2-Bit Flash A/D BIAS1 16 BIAS2 17 Bias Current Adjust X2 Stage 10 å – + 2-Bit Flash A/D 2-Bit DAC X2 Digital Delay and Error Correction 32 Bit 1 (MSB) 33 Bit 2 34 Bit 3 35 Bit 4 36 Bit 5 37 Bit 6 38 Bit 7 39 Bit 8 40 Bit 9 41 Bit 10 42 Bit 11 43 Bit 12 (LSB) Stage 1 VREF+ 11 VREF– 10 Reference Input å – + VIN+ 20 VIN– 21 VCM 18 S/H 2-Bit Flash A/D 2-Bit DAC Common Mode Voltage Reference Clock 4 to 9, 44 +VS 2 CLK 1, 15, 19, 22 to 31 GND Figure 1. ADS-238Q Functional Block Diagram DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048 (U.S.A.) · Tel: (508)339-3000 Fax: (508)339-6356 · For immediate assistance: (800) 233-2765 ® ® ADS-238Q ABSOLUTE MAXIMUM RATINGS PARAMETERS Supply Voltage, VS (Pins 4-9,44) Input Voltages: Analog Input, VIN+, VIN– (Pin 20, 21) VREF–, VREF+, (Pin 10, 11) CLK, (Pin 2) Lead Temperature (10 seconds) LIMITS UNITS –0.5 to +6 Volts –0.5 to (+VS +0.5) –0.5 to (+VS +0.5) –0.5 to (+VS +0.5) +300 Volts Volts Volts °C DYNAMIC PERFORMANCE Differential Phase Differential Gain Aperature Uncertainty Aperture Delay Time, tAP Data Latency A/D Conversion Rate Logic "1" Logic "0" CLK to Output Delay Time, tD (TA = TMIN to TMAX, VS = 3.3V, VREF– = 1.15V, VREF+ = 2.15V, VCM = 1.65V, CLK Frequency = 20MHz, BIAS1 = 90µA, BIAS2 = 9.5µA, Duty Cycle = 50% and Differential Input, unless otherwise specified.) ANALOG INPUTS MIN. TYP. MAX. UNITS ±0.6 1.2 — — ±1.0 1.65 1.4 120 ±1.7 1.9 — — 80% VS — — — — — — — — 1.8 — 20% VS ±1 ±1 — Supply Voltages, VS Supply Current, IS Power Dissipation Power Supply Rejection Ratio Volts Volts pF MHz Operating Temp. Range, Case Storage Temperature Range Package Type Weight Volts Volts µA µA pF 95% VS 0.1 8 — 0.4 12 Volts Volts ns 2.8 — — — 3.3 24 79 63 3.6 30 100 — Volts mA mW dB 0 — +70 °C –65 — +125 °C 44-pin (leaded), plastic thin quad flat package 0.2 grams Differential Analog Input 0.6 1.0 1.7 Volts — 1.15 — Volts — 2.15 — Volts 1.3 1.65 1.8 Volts — — — — 12 — — 12 ±0.6 ±3.0 55 — ±1.0 0.3 — — — — — — — Bits LSB LSB dB Bits %FSR % The analog input is a fully differential input that can be configured in various ways depending on whether a singleended or differential, AC or DC coupled input is required. An AC coupled input is most readily implemented using a transformer (1:1 with a center tap on the secondary winding) as illustrated in Figures 2, Typical Connection Diagram, and 3.1, Transformer Coupled Input. To minimize distortion, the core of the transformer must not saturate at full scale input voltage levels. To minimize kickback noise from the internal sample-hold a small capacitor should be connected across the VIN pins (pins 20 and 21). Figure 3.2, DC Coupled Single Ended Input, illustrates a conversion circuit for a DC coupled single-ended input. Power supplies and by-pass capacitors are not shown. Reference Voltage Inputs The ADS-238Q is designed to accept two external reference voltages at the VREF input pins, see Figure 2, Typical Connection Diagram. These reference voltages, applied to VREF+ (pin 11) and VREF– (pin 10), determine the analog input voltage range, which is equal to ±(VREF+ VREF–). This voltage range will be symmetric about the common mode voltage, and for best performance should be symmetrical about the midpoint of the supply voltage. DYNAMIC PERFORMANCE Peak Harmonics FIN = 5MHz FIN = 10MHz Total Harmonics Distortion FIN = 5MHz FIN = 10MHz Signal-to-Noise Ratio (w/o distortion) FIN = 5MHz FIN = 10MHz Signal-to-Noise Ratio (and distortion) FIN = 5MHz FIN = 10MHz Effective Number of Bits FIN = 5MHz FIN = 10MHz 80% VS — 4 TECHNICAL NOTES STATIC PERFORMANCE Resolution Differential Nonlinearity Integral Nonlinearity Common Mode rejection ratio No Missing Codes Offset, Mid-Scale Gain Error Degrees % ps rms ns Cycles MHz PHYSICAL/ENVIRONMENTAL REFERENCE VOLTAGES Reference Input Voltage Range (VREF+ - VREF–) Negative Reference Voltage (VREF–) Positive Reference Voltage (VREF+) Common Mode Output Voltage (VCM) — — — — — — POWER REQUIREMENTS DIGITAL INPUTS Logic Levels Logic "1" Logic "0" Logic Loading "1" Logic Loading "0" Input Capacitance 0.2 0.5 10 5 7.5 — DIGITAL OUTPUTS FUNCTIONAL SPECIFICATIONS Differential Input Voltage Range Common Mode Input Voltage Input Capacitance Input Bandwidth, Large Signal — — — — — 20 62 — 70 61 — — dB dB — — –68 –60 –61 — dB dB 59 — 62 58 — — dB dB 57 — 61 56 — — dB dB 9.2 — 9.8 9.0 — — Bits Bits In order to minimize overall converter noise it is recommended that the VREF pins be adequately bypassed using a 4.7µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor. Locate the bypass capacitors as close to the unit as possible. 2 ® ® ADS-238Q 4.7µF Ref– In (+1.15V) CLK In (3V Logic) +3.3V 0.01µF 10µF + + +3.3V Ref+ In (+2.15V) 0.01µF 0.01µF 11 44 VS GND CLK NC VS VS VS VS VS NC Bit 12 (LSB) NC Bit 11 NC 90µA Bit 10 GND 9.5µA Bit 9 Bias1 Bias2 0.01µF Bit 8 ADS-238Q Bit 7 VCM (+1.65V) RF In Bit 5 VIN+ Bit 4 VIN– 51 GND Bit 3 Bit 2 Minicircuit T1-6T Bit 1 GND 22 Interfacing 3V Logic Bit 6 GND 68pF Decoupling Cap 1 VRef– 12 VS 4.7µF +3.3V Digital 0.1µF VRef+ + 23 34 Bit 2 33 Bit 1(MSB) Ferrite Bead EXC-ELSA35 AGND DGND Figure 2. ADS-238QTypical Connection Diagram R3 R3 – + VCM OP191GP (R3)/2 VCM R 0.01µF R RF In VIN+ 51 (+1.65V) 51W – + INPUT ( +– 0.5V) VIN+ OPA642 R2 R2 68pF 15pF VIN– Minicircuit T1-6T – + 51W OPA642 51W VIN– R R Figure 3-1. ADS-238Q Transformer Coupled Input R Figure 3-2. ADS-238Q DC Coupled Single Ended Input 3 ® ® ADS-238Q Common Mode Voltage Reference Bias Current Inputs The ADS-238Q has an internal common mode reference voltage, VCM (pin 18). This reference voltage is typically one half of the supply voltage and is capable of driving loads up to 20µA. This reference is used to drive the center tap in the transformer used in fully differential applications, or provide level shifting in single-ended to differential applications. The bias currents shown in Table I, Sample Rate Bias Current Settings, and Figure 4, Suggested Bias Currents vrs Sample Rate, are designed to optimize performance of the ADS-238Q for a given sample rate. Figure 5, Bias Current Determination and Adjustment, details the suggested circuits for measuring bias voltage drops to calculate the bias currents. Adjustments to the bias currents are made via the trim pots. The Bias1 voltage drop is measured across TP1A and TP1B. The Bias2 voltage drop is measured across TP2A and TP2B. Figures 6-1 and 6-2 show the relationship between the bias currents and voltages when measured in the indicated circuit. The Bias1 and Bias2 pins should be by-passed with 0.01µF capacitors. Table 1. Sample Rate Bias Current Settings SAMPLE RATE (MHz) BIAS1 (µA) BIAS2 (µA) 1 5 10 20 20 50 80 90 3.5 6.5 8.0 9.5 Bias1 30 60 90 120 150 Bias1 (µA) 90 3.4 80 3.2 VBias1 (V) Bias Current (µA) 70 60 50 40 30 VBias1 2.19 2.53 2.79 3 3.22 3.0 2.8 2.6 2.4 20 Bias2 (µA) 2.2 10 2.0 0 0 5 10 15 20 0 30 60 90 120 Figure 4. Suggested Bias Current vrs Sample Rate 0.90 100k 4.75k 0.85 Bias1 VBias2 (V) 0.01µF 4.7V + 4.7µF 0.01µF 500k 100k Bias2 0.80 0.75 0.70 0.01µF 100k 100k VBias2 0.6975 0.7535 0.796 0.8295 0.8595 IBias2 3 6 9 12 15 TP2A 500k 180 Figure 6-1. Bias1 Voltage vrs Bias1 Current TP1A 100k 150 IBias1 (µA) Sample Rate (MHz) 0.65 TP2B 0.60 0 TP1B 3 6 9 12 15 IBias2 (µA) Figure 5. Bias Current Determination and Adjustment Figure 6-2. Bias2 Voltage vrs Bias2 Current 4 18 ® ® ADS-238Q Clock The ADS-238Q accepts a low voltage CMOS logic level at the clock input (CLK, pin 2). The clock duty cycle must be held to within 50% +/-3% because consecutive stages of the A-to-D are clocked in opposite phase. A duty cycle other than this will reduce the settling time available for every other stage, there by degrading dynamic performance. 10.0 Clock to Output Delay (ns) 9.5 For optimum performance at high input frequencies the clock must have low jitter, and rise/fall times less than 2ns. Over/undershoot should be avoided. Clock jitter causes the noise floor to increase proportional to the input frequency. To reduce crosstalk, and hence jitter, clock traces on the PC board should be kept as short as possible with transmission line practices employed. 9.0 8.5 8.0 7.5 7.0 6.5 6.0 2.5 Digital Outputs 3.1 3.4 3.7 VS The digital output data is provided in offset binary format, at 3.3V CMOS logic levels, and is available 7.5 clock cycles after the data is sampled. The output data is invalid for the first 20 clock cycles when the ADS-238Q is first powered up. Figure 7. Clock to Output Delay vrs VS Power Supplies and Grounding The clock to output delay is typically 8ns, but will change as a function of the supply voltage, VS. Figure 7, Clock to Output Delay vrs VS, shows this relationship. The ADS-238Q is powered from a single 3.3V supply. The converters should be mounted on a board that provides separate low impedance paths for the analog and digital supplies and grounds. For best performance the 3.3V supply should be clean, and linearly regulated. The power supply should be bypassed to ground with a 10µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor. Locate the bypass capacitors as close to the converter as possible. Analog and digital grounds should be isolated with a ferrite bead. See the Typical Connection Diagram, Figure 2. A negative full scale input results in an all zeros output code (0000 0000 0000). A positive full scale input results in an all ones output code (1111 1111 1111). The input is sampled during the high-to-low transition of the input clock. Output data should be latched during the low-to-high clock transition as shown in Figure 8, Timing Diagram. N-1 N N+1 N+2 VIN 2.8 tAP N+6 N+7 N+8 CLK tD N-2 DOUT Figure 8. ADS-238Q Timing Diagram 5 N-1 N ® ® ADS-238Q TYPICAL PERFORMANCE CHARATERISTICS 80 THD, SNR, SINAD (dB) THD, SNR, SINAD (dB) 80 70 THD 60 SNR 50 SINAD 40 30 THD 70 SNR 60 SINAD 50 40 30 20 20 10 0 10 1 10 0 10 2 10 1 10 2 Sample Rate (MHz) Input frequency (MHz) Note: Bias1 and Bias2 currents optimized for each sample rate Figure 9-1. THD, SNR, SINAD vrs Input Frequency Figure 9-2. THD, SNR, SINAD vrs Sample Rate 70 THD, SNR, SINAD (dB) 68 THD 66 64 SNR 62 SINAD 60 58 56 68 THD 66 64 SNR 62 SINAD 60 58 56 0 25 70 0 25 Temperature (˚C) Temperature (˚C) Figure 9-3. THD, SNR, SINAD vrs Temperature Figure 9-4. THD, SNR, SINAD vrs Clock Duty Cycle 80 THD, SNR, SINAD (dB) THD, SNR, SINAD (dB) 70 70 THD 60 SNR SINAD 50 40 30 20 45 46 47 48 50 49 51 52 53 54 Clock Duty Cycle Figure 9-5. Power Dissipation vrs Sample Rate 6 55 70 ® ® ADS-238Q MECHANICAL DIMENSIONS INCHES (mm) A B C D PIN 44 INDEX PIN 1 E F G K H I J Inches Symbol A B C D E F G H I J K Min. 0.472 Typ. 0.394 Typ. 0.394 Typ. 0.472 Typ. 0.031 Typ. 0.012 0.053 0.002 0.018 0.039 Typ. 0-7º Millmeters Max. -----0.018 0.057 0.006 0.030 --- Min. 12.00 Typ. 10.00 Typ. 10.00 Typ. 12.00 Typ. 0.80 Typ. 0.300 1.35 0.05 0.450 1.00 Typ. 0-7º Max. -----0.45 1.45 0.15 0.750 --- ORDERING INFORMATION ® MODEL OPERATING TEMP. RANGE PACKAGE ADS-238Q 0 to +70 °C 44-PIN PLASTIC TQFP ® ISO 9001 R E G I S T E R E D DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 Tel: (508) 339-3000 (800) 233-2765 Fax: (508) 339-6356 Internet: www.datel.com E-mail:[email protected] Data Sheet Fax Back: (508) 261-2857 DS-0445 11/99 DATEL (UK) LTD. Tadley, England Tel: (01256)-880444 DATEL S.A.R.L. Montigny Le Bretonneux, France Tel: 1-34-60-01-01 DATEL GmbH München, Germany Tel: 89-544334-0 DATEL KK Tokyo, Japan Tel: 3-3779-1031, Osaka Tel: 6-354-2025 DATEL makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. The DATEL logo is a registered DATEL, Inc. trademark.