ONSEMI ADP4000

ADP4000
Product Preview
Programmable Multi- Phase
Synchronous Buck
Converter with PMBus
The ADP4000 is an integrated power control IC with a PMBus
interface. The ADP4000 can be programmed for 1-, 2-, 3-, 4-, 5- or 6phase operation, allowing for the construction of up to six
complementary buck switching stages. The ADP4000 supports PSI,
which is a power state indicator and can be used to reduce number of
operating phases at light loads. The ADP4000 includes a PMBus
interface, which can be used to program system set points such as
voltage offset, load line, phase balance and output voltage. Key system
performance data such as CPU current, CPU voltage, and power and
fault conditions can also be read back over the PMBus from the
ADP4000.
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ADP4000
JCPZ
#YYWW
XXXXX
CCCCC
Features
Typical Applications
PIN ASSIGNMENT
ALERT
FAULT
SDA
SCL
EN
GND
ADD / VSENSE2
VSENSE1
IMON
TTSENSE
VRHOT
IREF
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
PIN 1
INDICATOR
ADP4000
TOP VIEW
(Not to Scale)
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
SW1
SW2
SW3
SW4
SW5
SW6
RT 13
RAMPADJ 14
TRDET 15
FBRTN 16
COMP 17
FB 18
CSREF 19
CSSUM 20
CSCOMP 21
ILIMFS 22
ODN 23
OD1 24
• Servers
• Desktop PC’s
• POLs (Memory)
= Device Code
= Pb--Free Package
= Date Code
= Assembly Lot
= Country of Origin
VCC3
PWRGD
PSI
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VCC
PMBus Interface
Supports Both VR11 and VR11.1 Specifications
Digitally Programmable 0.375 V to 1.6 V Output
Additional 200 mV Offset Programmable (Max 1.8 V Output)
Selectable 1-, 2-, 3-, 4-, 5-, or 6-Phase Operation
Fast-Enhanced PWM FlexModet
TRDET to Improve Load Release
Active Current Balancing Between All Output Phases
Supports On--The--Fly (OTF) VID Code Changes
Supports PSI – Power Saving Mode
This is a Pb--Free Device
xx
#
YYWW
XXX
CCC
48
47
46
45
44
43
42
41
40
39
38
37
•
•
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAM
LFCSP40
CASE 932AD
ORDERING INFORMATION
Device*
Package
Shipping†
ADP4000JCPZ--REEL LFCSP48 2500/Tape & Reel
ADP4000JCPZ--RL7
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2008
June, 2008 -- Rev. P0
1
LFCSP48 750/Tape & Reel
*The “Z’ suffix indicates Pb--Free package.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
ADP4000/D
ADP4000
ADD SCL
7
LIMIT
REGISTERS
ALERT 1
COMPARATOR
SDA TRDET RT
4
3
RAMPADJ
VCC
VCC3
14
37
48
SHUNT
REGULATOR
3.3 V
REGULATOR
13
15
PMBUS
23
ODN
24
OD1
36
PWM1
RESET
35
PWM2
RESET
34
PWM3
33
PWM4
32
PWM5
31
PWM6
30
SW1
29
SW2
28
SW3
27
26
SW4
SW5
25
SW6
21
CSCOMP
19
CSREF
20
CSSUM
9
IMON
18
FB
FAULT 2
STATUS
REGISTERS
UVLO
SHUTDOWN
850 mV
GND 6
OSCILLATOR
DIGITAL CONFIG
& VALUE
CONTROL
REGISTERS
+
+
+
CMP
–
MUX
VSENSE1 8
ADC
CURRENT
BALANCING
CIRCUIT
VRHOT 11
+
CMP
–
2 / 3 / 4 /5 / 6
PHASE
DRIVER LOGIC
+
THERMAL
THROTTLING
CONTROL
TTSENSE 10
CMP
CONTROL
RESET
–
+
RESET
CMP
–
Over Voltage
Threshold
–
CSREF
+
CMP
+
Under Voltage
Threshold
PWRGD 47
EN
RESET
CMP
–
–
EN/VTT 5
SET
RESET
–
CURRENT
LIMIT
CROWBAR
+
–
DELAY
CONTROL
CURRENT
MEASUREMENT
AND LIMIT
+
–
ILIMFS 22
CONTROL
IREF 12
–
COMP 17
+
ADP4000
PSI 46
PRECISION
REFERENCE
16
FBRTN
CONTROL
44
43
42
41
40
VID0 VID1 VID2 VID3 VID4 VID5
39
38
VID6 VID7
Figure 1. Block Diagram
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2
+
–
BOOT VOLTAGE&
SOFT-- START CONTROL
VID DAC
45
+
–
100 k
NTC
3
CSSUM
RAMPADJ
RT
220 k
Figure 2. Application Schematic
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470 pF
X7R
CSCOMP
VID4
32.4 k
VID5
1.21 k
VID0
6.81 k, 1%
1000 pF
SW6
SW5
SW4
SW3
SW2
SW1
35.7 k
1500 pF
X7R
82.5 k
1k
1k
1k
1k
1k
1k
5%
100 k Thermistor
1500 pF
X7R
OD1
3.3 pF
ILIMFS
560 pF
ODN
VID6
4.99 k
VID7
69.8 k
ADP4000
IREF
VID1
121 k
VRHOT
TTSENSE
IMON
VSENSE1
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
1 uF
X7R
680
470 pF
X7R
0.1uF
PROCHOT
PWRGD
ADD/VSENSE2
GND
EN
SCL
PSI
20 k
4.54 k
1 nF
Interface
VID2
4.7 uF
VTT I/O
SDA
FAULT
VID3
1k
6.8 k
PMBus
VCC3
ALERT
VCC
FAULT
1200 uF
16 V
680
ALERT
POWER GOOD
PSI
1 uF
X7R
1k
Vin 12 V
CSREF
COMP
FB
FBRTN
TRDET
348 k
4.7 uF
4.7 uF
4.7 uF
4.7 uF
4.7 uF
4.7 uF
OD
VCC
2
3
4
OD
VCC
2
3
4
18 nF
OD
VCC
2
3
4
18 nF
OD
2
3
18 nF
DRVL 5
PGND 6
SW 7
DRVH 8
VCC
4
18 nF
DRVL 5
PGND 6
SW 7
DRVH 8
OD
2
3
VCC
BST
IN
1
DRVL 5
PGND 6
SW 7
DRVH 8
ADP3121 10 nF
2.2
OD
2
3
BST
IN
1
ADP3121 10 nF
2.2
VCC
BST
IN
1
10 nF
DRVL 5
PGND 6
SW 7
DRVH 8
ADP3121
2.2
BST
IN
1
10 nF
DRVL 5
PGND 6
SW 7
DRVH 8
ADP3121
2.2
BST
IN
1
4
18 nF
DRVL 5
PGND 6
SW 7
DRVH 8
ADP3121 10 nF
2.2
BST
IN
1
4
18 nF
ADP3121 10 nF
2.2
150 nH
4.7 uF
150 nH
4.7 uF
150 nH
4.7 uF
150 nH
4.7 uF
150 nH
4.7 uF
150 nH
4.7 uF
10
10
10
10
10
10
Vcc Core (RTN)
Vcc Core
Vcc Sense
Vss Sense
ADP4000
63.4 k
63.4 k
63.4 k
63.4 k
63.4 k
63.4 k
ADP4000
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VIN
--0.3 to 6
V
VFBRTN
--0.3 to + 0.3 V
V
--0.3 to VIN + 0.3
V
SW1 to SW6
--5 to +25 V
V
SW1 to SW6 (<200 ns|)
--10 to +25 V
V
--0.3 to VIN + 0.3
V
--65 to 150
°C
0 to 85
°C
Input Voltage Range (Note 1)
FBRTN
PWM2 to PWM6, Rampadj
All other Inputs and Outputs
Storage Temperature Range
TSTG
Operating Ambient Temperature Range
ESD Capability, Human Body Model (Note 2)
ESDHBM
2
kV
ESD Capability, Machine Model (Note 2)
ESDMM
100
V
Moisture Sensitivity Level
MSL
3
--
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb--Free Versions (Note 3)
TSLD
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Refer to Electrical Characteristics and Application Information for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC--Q100--002 (EIA/JESD22--A114)
ESD Machine Model tested per AEC--Q100--003 (EIA/JESD22--A115)
Latchup Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78
3. For additional information on our Pb--Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
THERMAL CHARACTERISTICS
Characteristic
Thermal Characteristics, LFCSP, 7 mm * 7 mm (Note 1)
Thermal Resistance, Junction--to--Air (Note 4)
Thermal Resistance, Junction--to--Lead 2 (Note 4)
Symbol
Value
RθJA
RΨJL
24
10
Unit
°C/W
4. Values based on copper area of 645 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.
OPERATING RANGES (Note 1)
Characteristic
Output Voltage (Adjustable Version Only) (Note 5)
Ambient Temperature
5. Maximum limit for VOUT = VOUT(NOM) -- 10%.
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4
Symbol
Min
Max
Unit
VOUT
0.375
1.8
V
TA
0
85
°C
ADP4000
PIN ASSIGNMENT
Pin No.
Pin Name
1
ALERT
ALERT Output. Open drain output that asserts low when the VR exceeds a programmable limit.
Description
2
FAULT
FAULT Output. Open drain output that asserts low when a fault has occurred. This fault can be due to VR or
current--limit, crowbar, or undervoltage. The trip points are loaded into registers.
3
SDA
Digital Input Output. PMBus serial data bi--directional pin. Requires PMBus pullup.
4
SCL
Digital Input. PMBus serial bus clock open drain input. Requires PMBus pullup.
5
EN
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
6
GND
7
ADD/
VSENSE2
PMBus Address Input. Connect a resistor to ground to select one of 8 addresses. This input is reconfigured
after startup as an analog voltage monitor, VSENSE2.
8
VSENSE1
Analog Input. Measures an input voltage between 0 and 2.0 V and reports this back over the PMBus interface.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
9
IMON
10
TTSENSE
VR Temperature Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the
temperature at the desired thermal monitoring point.
11
VRHOT
VR HOT Output. Open drain output that signals when the temperature at the monitoring point connected to
TTSENSE exceeds the VRHOT temperature threshold.
12
IREF
13
RT
14
RAMPADJ
15
TRDET
Transient Detect. This output is asserted low whenever a load release is detected
16
FBRTN
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
17
COMP
Error Amplifier Output and Compensation Point.
18
FB
19
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the Power--Good and crowbar functions. This pin should be connected to the common point of
the output inductors.
20
CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
21
CSCOMP
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of
the current sense amplifier and the positioning loop response time.
22
ILIMFS
Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the internal current
sensing signal for current--limit and IMON. This value can be over--written using PMBus interface.
23
ODN
Output Disable Logic Output for PSI operation. This pin is actively pulled low when PSI is low, otherwise it
functions in the same way as OD1.
24
OD1
Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its
UVLO threshold to signal to the Driver IC that the driver high--side and low--side outputs should go low.
25 to 30
SW6 to
SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
31 to 36
PWM6 to
PWM1
Logic--Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3121. Connecting PWM6 to VCC disables PWM6, connecting PWM5 to VCC disables PWM5 and PWM6,
etc. This means the ADP4000 can be setup to operate as a 1-- 2--, 3--, 4--, 5--, or 6--phase controller.
37
VCC
Supply Voltage for the Device. A 340 Ω resistor should be placed between the 12 V system supply and the
VCC pin. The internal shunt regulator maintains VCC = 5.0 V.
38 to 45
VID7 to
VID0
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open.
When in normal operation mode, the DAC output programs the FB regulation voltage from 0.375 V to 1.6 V.
46
PSI
47
PWRGD
48
VCC3
Total Current Output Pin.
Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB,
IILIMFS, and ITH(X).
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no load offset point.
Power State Indicator. Pulling this pin low places the controller in lower power state operation.
Power--Good Output. Open--drain output that signals when the output voltage is outside of the proper
operating range.
3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval 3.3 V LDO.
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5
ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 6 and 7)
Test Conditions
Parameter
Symbol
Min
Typ
Max
Unit
VIREF
1.75
1.8
1.85
V
Reference Current
Reference Bias Voltage
Reference Bias Current
IIREF
RIREF = 121 kΩ
15
mA
Error Amplifier
VCOMP
0
4.4
V
VFB
--7
+7
mV
VFB(BOOT)
1.093
1.1
1.107
V
Load Line Positioning Accuracy
--77
--80
--83
mV
Load Line Range
--350
0
mV
Output Voltage Range
Accuracy
Relative to nominal DAC output, referenced
to FBRTN (see Figure 2)
In startup
Load Line Attenuation
Differential Non--linearity
Input Bias Current
Offset Accuracy
IFB
0
100
%
--1.0
+1.0
LSB
14.2
VR Offset Register = 111111, VID = 1.0 V
VR Offset Register = 011111, VID = 1.0 V
FBRTN Current
Output Current
FB forced to VOUT --3%
Gain Bandwidth Product
COMP = FB
Slew Rate
COMP = FB
BOOT Voltage Hold Time
Internal Timer
16
17.7
--193.75
193.75
mA
mV
IFBRTN
100
200
ICOMP
500
mA
GBW(ERR)
20
MHz
25
V/ms
tBOOT
2.0
ms
mA
VID Inputs
Input Low Voltage
VID(X)
VIL(VID)
Input High Voltage
VID(X)
VIH(VID)
Input Current
0.3
0.8
IIN(VID)
V
V
--5.0
mA
VID Transition Delay Time
VID code change to FB change
200
ns
No CPU Detection Turn--Off Delay
Time
VID code change to PWM going low
5.0
ms
Oscillator
Frequency Range
Frequency Variation
TA = 25°C, RT = 270 kΩ, 6--phase
TA = 25°C, RT = 130 kΩ, 6--phase
TA = 25°C, RT = 68 kΩ, 6--phase
Output Voltage
RT = 500 kΩ to GND
RAMPADJ Output Voltage
RAMPADJ -- FB, VFB = 1.0 V,
IRAMPADJ = --150 mA
RAMPADJ Input Current Range
fOSC
0.25
9.0
MHz
fPHASE
225
245
500
850
265
kHz
VRT
1.93
2.03
2.13
V
VRAMPADJ
--50
+50
mV
IRAMPADJ
5.0
60
mA
VOS(CSA)
--1.0
+1.0
mV
Current Sense Amplifier
Offset Voltage
CSSUM -- CSREF (see Figure 4)
Input Bias Current, CSREF
CSREF = 1.0 V
IBIAS(CSREF)
--20
+20
mA
Input Bias Current, CSSUM
CSREF = 1.0 V
IBIAS(CSSUM)
--10
+10
nA
Gain Bandwidth Product
CSSUM = CSCOMP
GBW(CSA)
10
MHz
Current Sense Amplifier
Slew Rate
CCSCOMP = 10 pF
Input Common--Mode Range
CSSUM and CSREF
10
Output Voltage Range
Output Current
Current--Limit Latchoff Delay Time
ICSCOMP
Internal Timer
6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area.
7. Guaranteed by design, not production tested.
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6
V/ms
0
3.0
V
0.05
3.0
V
500
mA
8.0
ms
ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 6 and 7)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
0.3
V
PSI
Input Low Voltage
Input High Voltage
0.8
Input Current
V
--5
mA
Assertion Timing
Fsw = 300kHz
3.3
ms
Deassertion Timing
Fsw = 300kHz
825
ns
TRDET
Output Low Voltage
IOUT = --6 mA
VOL
150
300
mV
IMON
Clamp Voltage
Accuracy
10 x (CSREF -- CSCOMP)/RILIM
1.0
1.15
V
--3.0
3.0
%
Output Current
Offset
--5.5
800
mA
5.5
mV
Current--Limit Comparator
ILIM Bias Current
CSREF -- CSCOMP)/RILIM,
(CSREF -- CSCOMP) = 150 mV, RILIM = 7.5 kΩ
ILIM
22
mA
Current--Limit Threshold Current
4/3 x IIREF
ICL
22
mA
Current Balance Amplifier
VSW(X)CM
--600
+200
mV
Input Resistance
SW(X) = 0 V
RSW(X)
12
18
21
kΩ
Input Current
SW(X) = 0 V
ISW(X)
8.0
12
18
mA
Input Current Matching
SW(X) = 0 V
ΔISW(X)
--6.0
+6.0
%
Phase Balance Adjustment Range
Low
Phase Bal Registers = 00000
--25
%
Phase Balance Adjustment Range
High
Phase Bal Registers = 11111
+25
%
Internal Timer
Delay Time Register = 011
2.0
ms
Timer Range Low
Delay Time Register = 000
0.5
ms
Timer Range High
Delay Time Register = 111
4.0
ms
Common--Mode Range
Delay Timer
Soft--Start
Internal Timer
Soft--Start Slope Register = 010
0.5
V/ms
Timer Range Low
Soft--Start Slope Register = 000
0.1
V/ms
Timer Range High
Soft--Start Slope Register = 111
1.5
V/ms
Enable Input
Input Low Voltage
VIL(EN)
Input High Voltage
VIH(EN)
Input Current
0.3
0.8
V
V
IIN(EN)
--1.0
mA
EN > 0.8 V, Internal Delay
tDELAY(EN)
2.0
ms
Output Low Voltage
IOD(SINK) = --400 mA
VOL(ODN/1)
Output High Voltage
IOD(SOURCE) = 400 mA
VOL(ODN/1)
Delay Time
ODN and OD1 Outputs
ODN / OD1 Pulldown Resistor
6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area.
7. Guaranteed by design, not production tested.
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7
160
4.0
500
mV
5.0
V
60
kΩ
ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 6 and 7)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
VPWRGD(UV)
--600
--500
--400
mV
Power--Good Comparator
Undervoltage Threshold
Relative to Nominal DAC Output
Undervoltage Adjustment Range Low
PWRGD_LO Register = 000
--500
mV
Undervoltage Adjustment Range High
PWRGD_LO Register = 111
--150
mV
Overvoltage Threshold
Relative to DAC Output, PWRGD_Hi = 00
Overvoltage Adjustment Range Low
PWRGD_Hi Register = 11
Overvoltage Adjustment Range High
PWRGD_Hi Register = 00
Output Low Voltage
IPWRGD(SINK) = --4 mA
VPWRGD(OV)
200
300
400
150
mV
300
VOL(PWRGD)
150
mV
mV
300
mV
Power Good Delay Time
During Soft--Start
Internal Timer
VID Code Changing
100
VID Code Static
2.0
ms
250
ms
200
VCROWBAR
200
300
ns
Crowbar Trip Point
Relative to DAC Output, PWRGD_Hi = 00
400
mV
Crowbar Adjustment Range
PWRGD_Hi Register
150
Crowbar Reset Point
Relative to FBRTN
250
300
300
mV
350
Crowbar Delay Time
Overvoltage to PWM going low
mV
100
250
ms
400
ns
tCROWBAR
VID Code Changing
VID Code Static
PWM Outputs
Output Low Voltage
IPWM(SINK) = --400 mA
VOL(PWM)
160
Output High Voltage
IPWM(SOURCE) = 400 mA
VOH(PWM)
4.0
Logic High Input Voltage
VIH(SDA,SCL)
2.1
Logic Low Input Voltage
VIH(SDA,SCL)
500
5.0
mV
V
PMBus Interface
0.8
Hysteresis
SDA Output Low Voltage
V
500
ISDA = --6 mA
VOL
Input Current
VIH; IIL
Input Capacitance
CSCL, SDA
Clock Frequency
fSCL
--1
0.4
V
1.0
mA
400
kHz
1.0
ms
5.0
SCL Falling Edge to SDA Valid Time
V
mV
pF
ALERT, FAULT Outputs
Output Low Voltage
IOUT = --6 mA
VOL
0.4
V
Output High Leakage Current
VOH = 5.0 V
VOH
1.0
mA
3.0
V
TTSENSE Inputs
TTSENSE Voltage Range
Internally Limited
0
Source Current
RIREF = 121 kΩ
VRHOT Output Low Voltage
IVRHOT(SINK) = --4mA
ITH
Input Voltage Conversion Range
ADC Resolution
--110
--125
--140
mA
150
300
mV
0
LSB Weighting
2.0
2.0
V
mV
Analog / Digital Converter
0
ADC Input Voltage Range
ADC Resolution
Total Unadjusted Error (TUE)
Differential Non--linearity (DNL)
2.0
1.95
8 Bits
6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area.
7. Guaranteed by design, not production tested.
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8
V
mV
1.0
%
1.0
LSB
ADP4000
ELECTRICAL CHARACTERISTICS
VIN = (5.0 V) FBRTN -- GND, for typical values TA = 25°C, for min/max values TA = 0°C to 85°C; unless otherwise noted. (Notes 6 and 7)
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
Analog / Digital Converter cont.
Conversion Time, Voltage Channel
Averaging Enabled (32 averages)
Round Robin Cycle Time
80
ms
TBD
ms
ADD Input
IADD = 2/3*IIREF
ADD Output Current
IADD
10
Address 000 Threshold
mA
0.1
V
Address 001 Threshold
0.15
0.225
V
Address 010 Threshold
0.3
0.45
V
Address 011 Threshold
0.5
0.675
V
Address 100 Threshold
0.75
0.9
V
Address 101 Threshold
1.0
1.25
V
Address 110 Threshold
1.35
1.7
V
Address 111 Threshold
1.8
V
Supply
VCC
VCC
DC Supply Current (see Figure 2)
VSYSTEM = 13.2 V, RSHUNT = 340 Ω
4.7
IVCC
UVLO Turn--On Current
UVLO Threshold Voltage
VCC Rising
UVLO Turn--Off Voltage
VCC Falling
VCC3 Output Voltage
IVCC3 = 1 mA
VUVLO
9.5
VCC3
3.0
5.25
5.75
V
20
25
mA
6.5
11
mA
V
4.1
3.3
6. Refer to Absolute Maximum Ratings and Application Information for Safe Operating Area.
7. Guaranteed by design, not production tested.
TYPICAL CHARACTERISTICS
3000
2500
Frequency (Hz)
2000
PWM1
1500
1000
500
0
13
20
30
43
50
68
75
82
130 180 270 395 430 500 680 850
RT (kΩ)
Figure 3. ADP4000 RT vs Frequency
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9
V
3.6
V
ADP4000
TEST CIRCUITS
+12 V
+1.25 V
680 Ω
+1 m F
100 nF
PWM1
PWM2
NC
PWM3
NC
PWM4
EN
PWM5
ADP4000
GND
PSI_SET
PWM6
SW1
1 kΩ
20 k Ω
SW4
SW5
SW6
ODN
OD1
CSSUM
CSCOMP
ILIMITFS
RT
IREF
SW2
SW3
COMP
FB
CSREF
VRHOT
RAMPADJ
TRDET
FBRTN
LLSET
IMON
TTSENSE
121 kΩ
680 Ω
VID6
VID7
VCC
VID3
VID4
VID5
VID1
VID2
VCC3
NC
NC
PWRGD
PSI
VID0
8 BIT
VID CODE
10 kΩ
100 nF
Figure 4. Closed-Loop Output Voltage Accuracy
ADP4000
12 V
12 V
680 Ω
ADP4000
680 Ω
680 Ω
VCC
37
1 kΩ
VCC
37
COMP
17
10 k Ω
CSCOMP
21
39 k Ω
680 Ω
FB
18
100 nF
CSSUM
20
–
CSREF
19
CSREF
19
+
1V
GND
6
VOS =
1V
CSCOMP – 1 V
40
6
VID
DAC
GND
ΔVFB= FBΔV = 80mV – FBΔV = 0 mV
Figure 6. Positioning Voltage
Figure 5. Current Sense Amplifier VOS
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10
ADP4000
Description
current--limit latchoff as explained in the Current--Limit
section. The current--limit timer is set to 4 times the delay
timer.
The ADP4000 is a 6--Phase VR11.1 regulator with a
PMBus Interface Typical application circuits is shown in
Figure 2.
Table 1. Delay Codes
Startup Sequence
The ADP4000 follows the VR11 start-up sequence shown
in Figure 7. After both the EN and UVLO conditions are
met, a programmable internal timer goes through one delay
cycle TD1. This delay cycle is programmed using Delay
Command, default delay = 2 ms, see Table 1 for
programmable values). The first six clock cycles of TD2 are
blanked from the PWM outputs and used for phase detection
as explained in the following section. Then the
programmable internal soft--start ramp is enabled (TD2) and
the output comes up to the boot voltage of 1.1V. The boot
hold time is also set by Delay Command. This second delay
cycle is called TD3. During TD3 the processor VID pins
settle to the required VID code. When TD3 is over, the
ADP4000 reads the VID inputs and soft--starts either up or
down to the final VID voltage (TD4). After TD4 has been
completed and the PWRGD masking time (equal to VID on
the fly masking) is finished, a third cycle of the internal timer
sets the PWRGD blanking (TD5).
The internal delay and soft--start times are programmable
using the serial interface and the Delay Command and the
Soft--Start Commands.
5.0 V
SUPPLY
VTT I/O
(ADP4000 EN)
VCC_CORE
TD1
VVID
TD4
VR READY
(ADP4000 PWRGD)
CPU
VID INPUTS
VID INVALID
1
010
1.5
011
2 = default
100
2.5
101
3
110
3.5
111
4
The soft--start slope for the output voltage is set by an
internal timer. The default value is 0.5 V/msec, which can be
programmed through the PMBus interface. After TD1 and
the phase detection cycle have been completed, the SS time
(TD2 in Figure 7) starts. The SS circuit uses the internal VID
DAC to increase the output voltage in 6.25 mV steps up to
the 1.1 V boot voltage.
Once the SS circuit has reached the boot voltage, the boot
voltage delay time (TD3) is started. The end of the boot
voltage delay time signals the beginning of the second
soft--start time (TD4). The SS voltage changes from the boot
voltage to the programmed VID DAC voltage (either higher
or lower) using 6.25 mV steps.
The soft--start slew rate is programmed using Bits <2:0>
of the Ton_Rise (0xD5) command code. Table 2 provides
the soft--start values
TD2
50 ms
0.5
001
Soft--Start
TD3
VBOOT
(1.1 V)
Delay (msec)
000
The delay timer is programmed using Bits <2:0> of the
Ton Delay command (0xD4). The delay can be programmed
between 0.5 msec and 4 msec. Table 1 provides the
programmable delay times.
UVLO
THRESHOLD
0.85 V
Code
TD5
Table 2. Slew Rate Codes
VID VALID
Figure 7. System Startup Sequence for VR11
Internal Delay Timer
An internal timer sets the delay times for the startup
sequence, TD1, TD3 and TD5. The default time is 2msec,
which can be changed using the PMBus interface. This timer
is used for multiple delay timings (TD1, TD3 and TD5)
during the startup sequence. Also, it is used for timing the
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11
Code
Slew Rate (V/msec)
000
0.1
001
0.3
010
0.5 = default
011
0.7
100
0.9
101
1.1
110
1.3
111
1.5
ADP4000
Master Clock Frequency
The clock frequency of the ADP4000 is set with an
external resistor connected from the RT pin to ground. The
frequency follows the graph in Figure 3. To determine the
frequency per phase, the clock is divided by the number of
phases in use. If all phases are in use, divide by 6. If 4 phases
are in use then divide by 4.
RT =
1
− R TO
n × f SW × Cr
(eq. 1)
where CT = 2.2 pF and RTO = 21 k
Output Voltage Differential Sensing
The ADP4000 combines differential sensing with a high
accuracy VID DAC and reference, and a low offset error
amplifier. This maintains a worst-case specification of
±7 mV differential sensing error over its full operating
output voltage and temperature range. The output voltage is
sensed between the FB pin and FBRTN pin. FB is connected
through a resistor, RB, to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN is
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a minimal current of 100 mA to allow
accurate remote sensing. The internal error amplifier
compares the output of the DAC to the FB pin to regulate the
output voltage.
Figure 8. System Startup Sequence for VR11
Figure 8 shows typical startup waveforms for the
ADP4000.
Figure 8. Typical Start-up Waveforms
Channel 1: CSREF (yellow)
Channel 2: PWM1 (blue)
Channel 3 : Enable (pink)
Phase Detection
During startup, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP4000
operates as a 6--phase PWM controller.
Output Current Sensing
The ADP4000 provides a dedicated current--sense
amplifier (CSA) to monitor the total output current for
proper voltage positioning vs. load current, for the IMON
output and for current-limit detection. Sensing the load
current at the output gives the total real time current being
delivered to the load, which is an inherently more accurate
method than peak current detection or sampling the current
across a sense element such as the low-side MOSFET. This
amplifier can be configured several ways, depending on
the objectives of the system, as follows:
• Output inductor DCR sensing without a thermistor for
lowest cost.
• Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor
temperature.
• Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the
CSREF pin, which is connected to the average output
voltage. The inputs to the amplifier are summed together
through resistors from the sensing element, such as the
switch node side of the output inductors, to the inverting
input CSSUM. The feedback resistor between CSCOMP
and CSSUM sets the gain of the amplifier and a filter
capacitor is placed in parallel with this resistor. The gain of
the amplifier is programmable by adjusting the feedback
resistor. This difference signal is used internally to offset the
VID DAC for voltage positioning. This difference signal
can be adjusted between 50% and 150% of the external value
To operate as a 5--Phase Controller connect PWM6 to VCC.
To operate as a 4--Phase Controller connect PWM5 and
PWM6 to VCC.
To operate as a 3--Phase Controller connect PWM4, PWM5
and PWM6 to VCC.
To operate as a 2--Phase Controller connect PWM3, PWM4,
PWM5 and PWM6 to VCC.
To operate as a single--phase controller connect PMW2,
PWM3, PWM4, PWM5 and PWM6 to VCC.
Prior to soft--start, while EN is high the PWM6, PWM5,
PWM4 PWM3 and PWM2 pins sink approximately 100 mA
each. An internal comparator checks each pin’s voltage vs.
a threshold of 3.0 V. If the pin is tied to VCC, it is above the
threshold. Otherwise, an internal current sink pulls the pin
to GND, which is below the threshold. PWM1 is low during
the phase detection interval that occurs during the first six
clock cycles of TD2. After this time, if the remaining PWM
outputs are not pulled to VCC, the 100 mA current sink is
removed, and they function as normal PWM outputs. If they
are pulled to VCC, the 100 mA current source is removed,
and the outputs are put into a high impedance state.
The PWM outputs are logic-level devices intended for
driving fast response external gate drivers such as the
ADP3121. Because each phase is monitored independently,
operation approaching 100% duty cycle is possible. In
addition, more than one output can be on at the same time to
allow overlapping phases.
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12
ADP4000
Table 3. Current--Limit
using the PMBus Loadline Calibration (0xDE) and Loadline
Set (0xDF) commands.
The difference between CSREF and CSCOMP is used as
a differential input for the current-limit comparator.
To provide the best accuracy for sensing current, the CSA
is designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors to make it
extremely accurate.
The CPU current can also be monitored over the PMBus.
The current--limit and the load line can be adjusted from the
circuit component values over the PMBus.
Code
Where VILIMFS = VCSREF
V CSREF − V CSCOMP =
R CS
× R L × I LOAD
R PH
(eq. 2)
(eq. 3)
Where RL = DCR of the Inductor.
Assuming that
R CS
× R L = 1 mΩ
R PH
(eq. 4)
i.e. the external circuit is set up for a 1mΩ Loadline then
the RILIMFS is calculated as follows
I ILIMFS =
1 mΩ × I LOAD
R ILIMITFS
53.3%
1 0000
100% = default
1 0001
103.3%
1 1110
143.3%
1 1111
146.7%
If the current--limit is reached and TD5 has completed, an
internal latch-off delay time will start, and the controller will
shut down if the fault is not removed. This delay is four times
longer than the delay time during the startup sequence. The
current--limit delay time only starts after the TD5 has
completed. If there is a current--limit during start-up, the
ADP4000 will go through TD1 to TD5, and then start the
latchoff time. Because the controller continues to cycle the
phases during the latchoff delay time, if the short is removed
before the timer is complete, the controller can return to
normal operation.
The latchoff function can be reset by either removing and
reapplying the supply voltage to the ADP4000, or by
toggling the EN pin low for a short time.
During startup when the output voltage is below 200 mV,
a secondary current--limit is active. This is necessary
because the voltage swing of CSCOMP cannot go below
ground. This secondary current--limit limits the internal
COMP voltage to the PWM comparators to 1.5 V. This limits
the voltage drop across the low-side MOSFETs through the
current balance circuitry. Typical over-current latchoff
waveforms are shown in Figure 9.
The current--limit threshold on the ADP4000 is
programmed by a resistor between the ILIMFS pin and the
CSCOMP pin. The ILIMFS current, IILIMFS, is compared
with an internal current reference of 22 mA. If IILIMFS
exceeds 22 mA then the output current has exceeded the limit
and the current--limit protection is tripped.
V ILIMFS − V CSCOMP
R ILIMFS
50%
0 0001
Current--Limit, Short Circuit and latchoff protection
Current--Limit Setpoint
I ILIMFS =
Current--Limit (% of external limit)
0 0000
(eq. 5)
Assuming we want a current--limit of 150A that means
that ILIMFS must equal 22 mA at that load.
20 mA =
1 mΩ × 150 AD
= 6.8 kΩ
R ILIMITFS
(eq. 6)
Solving this equation for RLIMITFS we get 6.8 kΩ. The
closest 1% resistor value is 6.8 kΩ.
The current--limit threshold can be modified from the
resistor programmed value by using the PMBus interface
using Bits <4:0> of the Current--Limit Threshold command
(0xE2). The limit is programmable between 50% of the
external limit and 146.7% of the external limit. The
resolution is 3.3%. Table 3 gives some examples codes.
Figure 9. Overcurrent Latchoff Waveforms
Channel 1: CSREF, Channel 2: COMP,
Channel 3: PWM1
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13
ADP4000
Load Line Setting
An inherent per phase current--limit protects individual
phases if one or more phases stops functioning because of a
faulty component. This limit is based on the maximum
normal mode COMP voltage.
The Loadline is programmable over the PMBus on the
ADP4000. It is programmed using the Loadline Calibration
(0xDE) and Loadline Set (0xDF) commands. The loadline
can be adjusted between 0% and 100% of the external RCSA.
In this example RCSA = 1 mΩ. RO needs to 0.8 mΩ. Therefore
programming the Loadline Calibration + Loadline Set
Register to give a combined percentage of 80% will set the RO
to 0.8 mΩ.
Output Current Monitor
IMON is an analog output from the ADP4000
representing the total current being delivered to the load. It
outputs an accurate current that is directly proportional to
the current set by the ILIMFS resistor.
I IMON = 10 × I ILIMFS
Table 4. Loadline Commands
(eq. 7)
Code
The current is then run through a parallel RC connected
from the IMON pin to the FBRTN pin to generate an
accurately scaled and filtered voltage as per the VR11.1
specification. The size of the resistor is used to set the IMON
scaling.
The scaling is set such that IMON = 900mV at the TDC
current of the processor. This means that the RIMON resistor
should be chosen as follows.
From the Current--Limit Setpoint paragraph we know the
following:
I ILIMFS =
1 mΩ × I LOAD
R ILIMFS
I IMON = 10 ×
1 mΩ × ILOAD
R ILIMFS
V IMON = 900 mV = 198 mA × R MON
3.3%
1 0000
50% = default
1 0001
53.3%
1 1110
96.7%
1 1111
100%
The ADP4000 has individual inputs (SW1 to SW6) for
each phase that are used for monitoring the current of each
phase. This information is combined with an internal ramp
to create a current balancing feedback system that has been
optimized for initial current balance accuracy and dynamic
thermal balancing during operation. This current balance
information is independent of the average output current
information used for positioning as described in the section.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage
to the RAMPADJ pin determines the slope of the internal
PWM ramp.
The balance between the phases can be programmed using
the PMBus Phase Bal SW(x) commands (0xE3 to 0xE8).
This allows each phase to be adjusted if there is a difference
in temperature due to layout and airflow considerations. The
phase balance can be adjusted from a default gain of 5 (Bits
4:0 = 10000). The minimum gain programmable is 3.75 (Bits
4:0 = 00000) and the max gain is 6.25 (Bits 4:0 = 11111).
(eq. 8)
(eq. 9)
When ILOAD = 135A, IMON equals
1 mΩ × 135 A
= 198 mA
6.81 kΩ
0%
0 0001
Current Control Mode and Thermal Balance
For a 150 A current--limit RLIMFS = 7.5 kΩ. Assuming the
TDC = 135 A then VMON should equal 900 mV when
ILOAD = 135 A.
I IMON = 10 ×
Loadline (as a percentage of RCSA)
0 0000
(eq.
10)
(eq. 11)
This gives a value of 4.54 kΩ for RMON.
If the TDC and OCP limit for the processor have to be
changed then it may be necessary to change the ILIMITFS
resistor only. This is because the ILIMITFS resistor sets up
both the current--limit and also the current out of the IMON
pin, as explained earlier.
The IMON pin also includes an active clamp to limit the
IMON voltage to 1.15 V MAX while maintaining accuracy
at 900 mV full scale.
Voltage Control Mode
A high gain, high bandwidth, voltage mode error
amplifier is used for the voltage mode control loop. The
control input voltage to the positive input is set via the VID
logic according to the voltages listed in VID Code Table.
The VID code is set using the VID Input pins or it can be
programmed over the PMBus using the VOUT_Command.
By default, the ADP4000 outputs a voltage corresponding to
the VID Inputs. To output a voltage following the
VOUT_Command the user first needs to program the
required VID Code. Then the VID_EN Bits need to be
enabled. The following is the sequence:
Active Impedance Control Mode
For controlling the dynamic output voltage droop as a
function of output current, the CSA gain and load line
programming can be scaled to be equal to the droop
impedance of the regulator times the output current. This
droop voltage is then used to set the input control voltage to
the system. The droop voltage is subtracted from the DAC
reference input voltage directly to tell the error amplifier
where the output voltage should be. This allows enhanced
feed-forward response.
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14
ADP4000
1. Program the required VID Code to the
VOUT_Command code (0x21)
2. Set the VID_EN bit (Bit 3) in the VR Config 1 A
(0xD2) and on the VR Config 1B (0xD3).
This voltage is also offset by the droop voltage for active
positioning of the output voltage as a function of current,
commonly known as active voltage positioning. The output
of the amplifier is the COMP pin, which sets the termination
voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location
with Resistor RB and is used for sensing and controlling the
output voltage at this point. A current source (equal to IFB)
from the FB pin flowing through RB is used for setting the
no load offset voltage from the VID voltage. The no load
voltage is negative with respect to the VID DAC for Intel
CPU’s.
The value of RB can be found using the following
equation.
RB =
V VID − V ONL
I IFB
The size of the internal ramp can be made larger or
smaller. If it is made larger, stability and noise rejection
improves but the transient performance decreases. If the
ramp is made smaller then the transient response improves
however noise rejection and stability degrades.
COMP Pin Ramp
There is a ramp signal on the COMP signal, which is due
to the droop voltage and the output voltage ramps. This ramp
adds to the internal ramp to produce the following ramp
signal at the PWM input.
V RT =
1−
An offset voltage can be added to the control voltage over
the serial interface. This is done using Bits <5:0> of the
VOUT_TRIM (0xDB) and VOUT_CAL (0xDC) Commands.
The max offset that can be applied is ±193.75 mV (even if the
sum of the offsets > 193.75mV). The LSB size is 6.25 mV. A
positive offset is applied when Bit 5 = 0. A negative offset is
applied when Bit 5 = 1.
VOUT_
CAL
CODE
CAL
OFFSET
VOLTAGE
TOTAL
OFFSET
VOLTAGE
00 1000
50 mV
00
0010
12.5 mV
62.5 mV
10 0001
-6.25 mV
10 1110
-87.5 mV
-93.75 mV
00 1111
93.75 mV
10
0001
-6.25 mV
87.5 mV
The ADP4000 has the ability to respond to dynamically
changing VID inputs while the controller is running. This
allows the output voltage to change while the supply is
running and supplying current to the load. This is commonly
referred to as Dynamic VID (DVID). A DVID can occur
under either light or heavy load conditions. The processor
signals the controller by changing the VID inputs (or by
programming a new VOUT_Command) in a single or
multiple steps from the start code to the finish code. This
change can be positive or negative.
When a VID bit changes state, the ADP4000 detects the
change and ignores the DAC inputs for a minimum of
200 ns. This time prevents a false code due to logic skew
while the VID inputs are changing. Additionally, the first
VID change initiates the PWRGD and CROWBAR
blanking functions for a minimum of 100 ms to prevent a
false PWRGD or CROWBAR event. Each VID change
resets the internal timer.
If a VID off code is detected the ADP4000 will wait for
5 msec to ensure that the code is correct before initiating a
shutdown of the controller.
The ADP4000 also uses the TON_Transition command
code (0xD6) to limit the DVID slew rates. These can be
encountered when the system does a large single VID step
for power state changes, thus the DVID slew rate needs to
be limited to prevent large inrush currents.
RAMPADJ Input Current
The resistor connected to the Rampadj pin sets the internal
PWM ramp. The value for this resistor is chosen to provide
the combination of thermal balance, stability and transient
response.
RR =
AR × L
3 × A D × R DS × C R
(eq. 13)
Where
AR is the internal ramp amplifier gain (= 0.5)
AD is the current balancing amplifier gain (= 5)
RDS is the total low side MOSFET on resistance
CR is the internal ramp capacitor value (= 5pF).
The internal ramp voltage can be calculated as follows:
VR =
A R × (1 − D) × V VID
R R × C R × fSW
(eq. 15)
Dynamic VID
Table 5. Offset Codes
TRIM
OFFSET
VOLTAGE

2×(1−n×D)
n×f SW×C X×R O
Where Cx = bulk capacitance
RO = Droop
n = number of phases
fSW = switching frequency per phase
D = duty cycle
VR = Internal Ramp Voltage (calculated in
Rampadj section of this data sheet)
This ramp voltage should be set to at least 0.5 V for noise
immunity reasons. If it is less than 0.5 V then decrease the
ramp resistor.
(eq. 12)
VOUT_
TRIM
CODE

VR
(eq. 14)
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15
ADP4000
Power Good Monitoring
The transition slew rate is programmed using Bits <2:0>
of the Ton_Transition (0xD6) command code. Table 6
provides the soft--start values.
The power good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open-drain output
whose high level (when connected to a pull-up resistor)
indicates that the output voltage is within the nominal limits
specified in the specifications above based on the VID
voltage setting. PWRGD goes low if the output voltage is
outside of this specified range, if the VID DAC inputs are in
no CPU mode, or whenever the EN pin is pulled low.
PWRGD is blanked during a DVID event for a period of
100 ms to prevent false signals during the time the output is
changing.
The PWRGD circuitry also incorporates an initial turn-on
delay time (TD5). Prior to the SS voltage reaching the
programmed VID DAC voltage and the PWRGD masking
time finishing, the PWRGD pin is held low. Once the SS
circuit reaches the programmed DAC voltage, the internal
timer operates.
The default range for the PWRGD comparator is
+300 mV and --500 mV. However these values can be
adjusted over the PMBus. The high limit is programmed
using Bits <1:0> of Command Code 0xE0 and the low limit
is programmed using Bits <2:0> of Command code 0xE1.
The following is a table of the programmable values.
Table 6. Transition Rate Codes
Code
Transition Rate (V/msec)
000
1
001
3 = default
010
5
011
7
100
9
101
11
110
13
111
15
Enhanced Transients Mode
The ADP4000 incorporates enhanced transient response
for both load step up and load release. For load step up it
senses the output of the error amp to determine if a load step
up has occurred and then sequences on the appropriate
number of phases to ramp up the output current.
For load release, it also senses the output of the error amp
and uses the load release information to trigger the TRDET
pin, which is then used to adjust the error amp feedback for
optimal positioning. This is especially important during
high frequency load steps.
Additional information is used during load transients to
ensure proper sequencing and balancing of phases during
high frequency load steps as well as minimizing the stress on
components such as the input filter and MOSFET’s.
Table 7. PWRGD High Limits
Code
PWRGD High Limits
00
+300mV (default)
01
+250 mV
10
+200 mV
11
+150 mV
TRDET and Phase Shuffling
The ADP4000 senses the error amp output and triggers the
TRDET pin when a load release takes place. The TRDET
circuit, as shown in Figure 2, adjusts the feedback for
optimal positioning especially during high frequency load
steps. TRDET is also used to trigger phase shuffling. If
repeated transients take place at the switching frequency
then its possible for one phase to carry most of the currrent.
To prevent this from happening the ADP4000 will shuffle
the phases whenever a load release happens, i.e. it will
randomize the phase sequence.
Table 8. PWRGD Low Limits
Reference Current
The IREF pin is used to set an internal current reference.
This reference current sets IFB and ITTSENSE. A resistor to
ground programs the current based on the 1.8 V output.
I REF =
1.8 V
R IREF
PWRGD Low Limits
000
-500mV (default)
001
-450 mV
010
-400 mV
011
-350 mV
100
-300 mV
101
-250 mV
110
-200 mV
111
-150 mV
Power State Indicator
The PSI pin is an input used to determine the operating
state of the load. If this input is pulled low, the load is in a low
power state and the controller asserts the ODN pin low,
which can be used to disable phases and maintain better
efficiency at lighter loads.
The sequencing into and out of low power operation is
maintained to minimize output deviations as well as
providing full power load transients immediately after
exiting a low power state.
(eq. 16)
Typically, RIREF is set to 121 kΩ to program
IREF = 15 mA. The following currents are then equal to
I FB = 16 × I REF = 16 mA
15
Code
(eq. 17)
I TTSENSE = − 8 (IREF) = − 120 mA
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ADP4000
Output Enable and UVLO
The user can program how many phases are enabled when
PSI is asserted. By default only phase 1 is enabled. The
number of phases enabled can be changed over the PMBus.
However extreme care should be taken to ensure that OD1
is connected to all phases enabled during PSI. The number
of phases enabled during PSI is programmed using Bits 7
and 6 of the MFR Config Command (0xD1)
For the ADP4000 to begin switching, the input supply
current to the controller must be higher than the UVLO
threshold and the EN pin must be higher than its 0.8 V
threshold. This initiates a system startup sequence. If either
UVLO or EN is less than their respective thresholds, the
ADP4000 is disabled. This holds the PWM outputs at
ground and forces PWRGD, ODN and OD1 signals low.
In the application circuit (see Figure 2), the OD1 pin
should be connected to the OD inputs of the external drivers
for the phases that are always on. The ODN pin should be
connected to the OD inputs of the external drivers on the
phases that are shut down during low power operation.
Grounding the driver OD inputs disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important in preventing the discharge of the output
capacitors when the controller is shut off. If the driver
outputs are not disabled, a negative voltage can be generated
during output due to the high current discharge of the output
capacitors through the inductors.
Table 9. # Phases Enabled During PSI
# of Phases
Running
Normally
Code
# of Phases
Running
During PSI
6
00
1
1
01
2
1 and 4
10
3
1, 3 and 5
11
1
1
00
1
1
01
2
1 and 4
10
1
1
11
1
1
00
1
1
01
2
1 and 3
10
1
1
5
4
3
2
1
Phases
Running
11
1
1
00
1
1
01
1
1
10
1
1
11
1
1
00
1
1
01
1
1
10
1
1
11
1
1
00
1
1
01
1
1
10
1
1
11
1
1
Thermal Monitoring
The ADP4000 includes a thermal monitoring channel
using a thermistor. Temperature trip points can be set for
ALERT and FAULT levels through the PMBus interface.
Also, the temperature values can be read back over the
PMBus interface.
The VR thermal monitoring circuits require an NTC
thermistor to be placed from TTSENSE to GND. For best
accuracy, the thermistors can be linearized using resistors. A
fixed current of 8 times IREF (normally giving 120 mA) is
sourced out of the TTSENSE pin into the thermistor. When
the TTSENSE temperature exceeds the OT Fault Limit
(0x51), VRHOT is asserted.
The temperature value is reported back in the
Read_Temperature1 command. The AP4000 measures the
voltage on the TTSENSE pin and calculates the temperature
using the following formula:
Read_Temperature_1 = (TTSENSE Voltage)*TTSENSE
Gain + TTSENSE Offset.
The TTSENSE Gain and Offset factors depend upon the
combination of thermistor and linearizing register used in
the circuit and can be programmed by the user using
commands TTSENSE Gain (addr = 0xF7) and TTSENSE
Offset (addr = 0xF8). The default values in the ADP4000 are
for a 100 k Thermistor and a 20 k Linearizing resistor. If the
user would like to measure the voltage directly then the
TTSENSE Gain should be programmed to 1 and the Offset
should be programmed to 0.
The actual phases enabled depend upon how many phases
are enabled for normal operation. For example if 4 phases
are enabled normally and 2 during PSI, then Phase 1 and
Phase 3 will be enabled during PSI.
Output Crowbar
As part of the protection for the load and output
components of the supply, the PWM outputs are driven low
(turning on the low-side MOSFETs) when the output
voltage exceeds the upper crowbar threshold. This crowbar
action stops once the output voltage falls below the release
threshold of approximately 300 mV.
The value for the crowbar limit follows the programmable
PWRGD high limit.
Turning on the low-side MOSFETs pulls down the output
as the reverse current builds up in the inductors. If the output
overvoltage is due to a short in the high--side MOSFET, this
action current-limits the input supply or blows its fuse,
protecting the microprocessor from being destroyed.
Voltage Monitoring
The ADP4000 can monitor up to three voltages. It can
monitor the voltage on the EN pin and reports this back in
a register. It can also monitor the voltage on the VSENSE1
and the VSENSE2 pins and report these back in registers
over PMBus. The ADC range for the voltage measurements
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ADP4000
PMBus Interface
is 0 V to 2.0 V. Voltages greater than 2.0 V can monitored
using a resistor divider network. Voltage measurements are
10 bits wide.
Vsense1 is intended to measure the input voltage and
report this back in the READ_VIN command. However the
input voltage is typically 12 V and the ADC range is only 0 V
to 2.0 V. Therefore an external resistor divided is needed, the
ADP4000 assumes that an 8--1 resistor divider is used, the
ADP4000 measures the voltage on the pin and multiples by
8 and places the result in the Read Vin register. The circuit
in Figure 2 uses a 6.8 K and a 1.0 k resistor to divide the input
voltage by 8.
Control of the ADP4000 is carried out using the PMBus
Interface. The physical protocol for PMBus closely matches
that of SMBus.
The ADP4000 is connected to this bus as a slave device,
under the control of a master controller.
To setup the PMBus Address the ADP4000 sources a
10 mA current from the ADD pin through an external
resistor. The voltage is then measured by the ADC and user
to set the PMBus address. The table below gives the
thresholds for each possible PMBus address.
Table 10. Setting Up the PMBus Address
Shunt Resistor
The ADP4000 uses a shunt to generate 5.0 V from the
12 V supply range. A trade-off can be made between the
power dissipated in the shunt resistor and the UVLO
threshold. Figure 10 shows the typical resistor value needed
to realize certain UVLO voltages. It also gives the maximum
power dissipated in the shunt resistor for these UVLO
voltages.
High Threshold
Low Threshold
0xC0
0.1
--
0xC2
0.225
0.15
0xC4
0.45
0.3
0xC6
0.675
0.5
0xC8
0.9
0.75
0xCA
1.25
1.0
0xCC
1.7
1.35
0xCE
--
1.8
0.325
400
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, because a low--to--high
transition when the clock is high might be interpreted as a
stop signal. The number of data bytes that can be transmitted
over the serial bus in a single read or write operation is
limited only by what the master and slave devices can
handle.
1. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the tenth
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse;
this is known as No Acknowledge. The master
takes the data line low during the low period
before the tenth clock pulse, and then high during
the tenth clock pulse to assert a stop condition.
Any number of bytes of data can be transferred over
the serial bus in one operation, but it is not possible
to mix read and write in one operation because the
type of operation is determined at the beginning and
cannot subsequently be changed without starting a
new operation.
In the ADP4000, write operations contain one, two
or three bytes, and read operations contain one or
two bytes. The command code or register address
0.3
350
0.275
Rshunt
300
0.25
250
0.225
200
150
Address (8 Bits)
Pshunt
2--0603 Limit
2--0805 Limit
0.2
0.175
8
9
10
11
12
13
14
15
16
ICC (UVLO)
Figure 10. Typical Shunt Resistor Value and Power
Dissipation for Different UVLO Voltage
The maximum power dissipated is calculated using the
Equation 18.
P MAX =
VIN(MAX) − VCC(MIN)
R SHUNT
2
(eq. 18)
where:
VIN(MAX) is the maximum voltage from the 12 V input supply
(if the 12 V input supply is 12 V ±5%, VIN(MAX) = 12.6 V; if
the 12 V input supply is 12 V ±10%, VIN(MAX) = 13.2 V).
VCC(MIN) is the minimum VCC voltage of the ADP4000. This
is specified as 4.75 V.
RSHUNT is the shunt resistor value.
The CECC standard specification for power rating in
surface-mount resistors is: 0603 = 0.1 W, 0805 = 0.125 W,
1206 = 0.25 W.
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ADP4000
2. The read byte operation is shown in Figure 13.
First the command code needs to be written to the
ADP4000 so that the required data is sent back.
This is done by performing a write to the
ADP4000 as before, but only the data byte
containing the register address is sent, because no
data is written to the register. A repeated start is
then issued and a read operation is then performed
consisting of the serial bus address; R/W bit set to
1, followed by the data byte read from the data
register.
3. It is not possible to read or write a data byte from a
data register without first writing to the address
pointer register, even if the address pointer register
is already at the correct value.
4. In addition to supporting the send byte, the
ADP4000 also supports the read byte, write byte,
read word and write word protocols.
determines the number of bytes to be read or written,
See the register map for more information.
To write data to one of the device data registers or
read data from it, the address pointer register must be
set so that the correct data register is addressed (i.e.
command code), and then data can be written to that
register or read from it. The first byte of a read or
write operation always contains an address that is
stored in the address pointer register. If data is to be
written to the device, the write operation contains a
second data byte that is written to the register
selected by the address pointer register.
This write byte operation is shown in Figure 12. The
device address is sent over the bus, and then R/W is
set to 0. This is followed by two data bytes. The first
data byte is the address of the internal data register
to be written to, which is stored in the address pointer
register. The second data byte is the data to be written
to the internal data register.
9
1
9
1
SCL
1
SDA
10
0
START BY
MASTER
0
A1
A0
D6
D7
R/W
D4
D5
D2
D3
D1
D0
ACK. BY
ADP4000
FRAME 1
SERIAL BUS ADDRESS
BYTE
ACK. BY
ADP4000
STOP BY
MASTER
FRAME 2
COMMAND CODE
Figure 11. Send Byte
1
9
9
1
SCL
SDA
START BY
MASTER
1
1
0
0
0
A1
A0
D7
R/W
D6
D5
D4
D3
D2
D1
D0
ACK. BY
ADP4000
ACK. BY
ADP4000
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
COMMAND CODE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
FRAME 3
D ATA
BYTE
Figure 12. Write Byte
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19
D2
D1
D0
ACK. BY
ADP4000
STOP BY
MASTER
ADP4000
1
9
1
9
SCL
1
SDA
10
0
START BY
MASTER
0
A1
A0
D7
R/W
D6
D4
D5
D3
D2
D1
D0
ACK. BY
ADP4000
FRAME 1
SERIAL BUS ADDRESS
BYTE
ACK. BY
ADT4000
FRAME 2
COMMAND CODE
1
9
9
1
SCL
SDA
1
1
REPEATED START
BY MASTER
0
0
0
A1
A0
FRAME 1
SERIAL BUS ADDRESS
BYTE
R/W
D7
D6
D4
D5
D3
D2
D1
D0
STOP BY
MASTER
NO ACK. BY
MASTER
ACK. BY
ADP4000
FRAME 2
DATA BYTE
FROM ADP4000
Figure 13. Read Byte
Write Operations
out a single byte read without asserting an intermediate stop
condition.
The PMBus specification defines several protocols for
different types of read and write operations. The ones used
in the ADP4000 are discussed in this section. The following
abbreviations are used in the diagrams:
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA and
the transaction ends.
The byte write operation is shown in Figure 15.
S--START
P--STOP
R--READ
W--WRITE
A--ACKNOWLEDGE
A--NO ACKNOWLEDGE
The ADP4000 uses the following PMBus write protocols.
Send Byte
In this operation, the master device sends a single
command byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
For the ADP4000, the send byte protocol is used to clear
Faults. This operation is shown in Figure 14.
1
2
3
SLAVE
S
W A
ADDRESS
4
5 6
COMMAND
CODE
A P
1
2
3
SLAVE
S
W A
ADDRESS
4
COMMAND
CODE
5
6
7
8
A DATA A P
Figure 15. Single Byte Write to a Register
Write Word
In this operation, the master device sends a command byte
and two data bytes to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the first data byte.
7. The slave asserts ACK on SDA.
Figure 14. Send Byte Command
If the master is required to read data from the register
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
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ADP4000
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the Data Byte.
10. The master asserts NO ACK on SDA.
11. The master asserts a stop condition on SDA and
the transaction ends.
8. The master sends the second data byte.
9. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA and
the transaction ends.
The word write operation is shown in Figure 16.
1
2
3
SLAVE
S
W A
ADDRESS
4
5
COMMAND
CODE
6
7
8
9 10
DATA
DATA
A
A
A P
(LSB)
(MSB)
1
2
Figure 16. Single Word Write to a Register
Block Write
2
3
SLAVE
S
W A
ADDRESS
4
5
COMMAND
CODE
10
DATA
BYTE 2
11
A
A
...
...
6
7
BYTE COUNT
A
=N
12
DATA
BYTE N
13
A
8
4
5
COMMAND
CODE
6
7
8
9
10 11
SLAVE
A S
R A DATA A
ADDRESS
P
Figure 18. Single Read from a Register
In this operation, the master device sends a command byte
and a byte count followed by the stated number of data bytes
to the slave device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends the byte count N.
7. The slave asserts ACK on SDA.
8. The master sends the first data byte.
9. The slave asserts ACK on SDA.
10. The master sends the second data byte.
11. The slave asserts ACK on SDA.
12. The master sends the remainder of the data byes.
13. The slave asserts an ACK on SDA after each data
byte.
14. After the last data byte the master asserts a STOP
condition on SDA.
1
3
SLAVE
S
W A
ADDRESS
Read Word
In this operation, the master device receives two data
bytes from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA.
7. The master sends the 7 bit slave address followed
by the read bit (high).
8. The slave asserts ACK on SDA.
9. The slave sends the first Data Byte (low Data
Byte).
10. The master asserts ACK on SDA.
11. The slave sends the second Data Byte (high Data
Byte).
12. The masters asserts a No ACK on SDA.
13. The master asserts a stop condition on SDA and
the transaction ends.
9
DATA
A
BYTE 1
1
2
3
SLAVE
S
W A
ADDRESS
14
4
COMMAND
CODE
5
6
7
8
11
P
9
10
SLAVE
DATA
A S
R A
A
ADDRESS
(LSB)
12 13
DATA
A P
(MSB)
Figure 17. Block Write to a Register
Figure 19. Word Read from a Command Code
Read Operations
The ADP4000 uses the following PMBus read protocols.
Block Read
In this operation, the master device sends a command
byte, the slave sends a byte count followed by the stated
number of data bytes to the master device as follows:
1. The master device asserts a START condition on
SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a REPEATED START condition
on SDA.
Read Byte
In this operation, the master device receives a single byte
from a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserted ACK on SDA.
6. The master sends a repeated start condition on SDA.
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ADP4000
Operation Command
5. The master sends the 7-bit slave address followed
by the read bit (high).
6. The slave asserts ACK on SDA
7. The slave sends the byte count N.
8. The master asserts ACK on SDA.
9. The slave sends the first data byte
10. The master asserts ACK on SDA.
11. The slave sends the remainder of the data byes, the
master asserts an ACK on SDA after each data byte.
12. After the last data byte the master asserts a No
ACK on SDA.
13. The master asserts a STOP condition on SDA.
1
2
3
4
5
6
The operation command, when enabled in the
ON_OFF_Config command, can be used to start and stop
the ADP4000 switching. The options available described in
the Operation Command (0x01) in Table 11. There are two
options for turning off, soft off and immediate off. There are
three options for turning on. The first is ON, where the
output voltage is soft started towards the Boot Voltage and
then to the VID Voltage (same startup sequence as toggling
EN). The other two options are margin high and margin low.
When these options are selected the output voltage will settle
on the VOUT_MARGIN_HIGH VID Code (0x25) or the
VOUT_MARGIN_LOW VID Code (0x26).
7
Limits, ALERTs, and FAULTs
SLAVE
SLAVE
BYTE COUNT
S
W A S
R A
ADDRESS
ADDRESS
=N
8
9
10
A
DATA
BYTE 1
A
...
11
12 13
DATA
BYTE N
A P
The ADP4000 monitors a number of voltage rails,
temperatures, current etc. For each of the measured values
there are ALERT and FAULT limits. When an ALERT or
FAULT limit is exceeded then the ALERT or FAULT pin is
asserted low and will remain low until the PMBus master
does a Clear_Faults command and the measured value is
back within the programmed limits. Take for example the
temperature measurement Read_Temperature1 (0x8D).
This value is compared with the OT_WARN_LIMIT (0x51)
and the UT_WARN_LIMIT (0x52). If the measured
temperature goes above the OT_WARN_LIMIT or under
the UT_WARN_LIMIT then the corresponding Status bit is
set Status_Temperature Command (0x7D) and an ALERT
pin is pulled low. The ALERT pin will remain low until the
PMBus master does a Clear_Faults command (0x03) and the
measured temperature is back within the programmed
limits. If the measured temperature exceeds the
OT_FAULT_LIMIT (0x51) then Bit 7 of the
Status_Temperature command gets set and the FAULT pin
is asserted low. The intention is that a FAULT condition is
worse than an ALERT condition.
Each measured value is compared with appropriate high
and low limits and the results of these comparisons are
stored in Status Registers. See details of the various status
registers in Table 11, commands 0x78, STATUS BYTE to
0x80 STATUS ALERT.
The ADP4000 also allows the user to program which
measured values can generate an ALERT and a FAULT
using the Mask ALERT (0xF9) and Mask FAULT (0xFA)
Commands. If the Mask VOUT Bit (Bit 7 is set in the Mask
ALERT command) then the measured Vout going outside
the programmed limits will set the appropriate Status bit but
will not assert ALERT pin low. See command codes 0xF9
and 0xFA in Table 11 for more details.
Figure 20. Block Write to a Command Coder
PMBus Timeout
The ADP4000 includes an PMBus timeout feature. If
there is no PMBus activity for 35 ms, the ADP4000 assumes
that the bus is locked and releases the bus. This prevents the
device from locking or holding the PMBus expecting data.
Some PMBus controllers cannot handle the PMBus timeout
feature, so it can be disabled.
Configuration Register 1 (0xTBD)
Bit 3 SMB_TO_EN = 1; PMBus timeout enabled.
Bit 3 TODIS = 0; PMBus timeout disabled (default).
Virus Protection
To prevent rogue programs or viruses from accessing
critical ADP4000 register settings, the lock bit can be set.
Setting Bit 0 of the Lock/Reset sets the lock bit and locks
critical registers. In this mode, certain registers can no
longer be written to until the ADP4000 is powered down and
powered up again. For more information on which registers
are locked see the register map.
ON_OFF_Config Command
The PMBus specifies an ON_OFF_Config which allows
the user to configure when the ADP4000 should start and
stop switching. There two control inputs, the EN input
(specified as per VR11.1) and the Operation Command. The
user can program the ADP4000 to respond to or ignore each
of the control inputs. The default configuration is the EN pin
is acted on, and the Operation Command is ignored. The EN
pin is active high by default but can be programmed to be
active low over PMBus. The details of the individual bits can
be found in the description for Command Code 0x02
(ON_OFF_Config) in Table 11.
Linear Mode
PMBus specifies two data format used for reporting back
voltage, current and temperatures etc and for programming
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ADP4000
Limits. The ADP4000 uses Linear Mode. Linear Mode can
be decoded as follows:
X = Y*2^N
the PMBus spec says this register should read back Amps.
Therefore the IOUT_CAL_GAIN and IOUT_CAL_OFFSET
commands need to be programmed to convert the Imon
voltage into current in Amps. The following equation is used:
READ_IOUT = Imon Voltage × IOUT_CAL_GAIN
Where X = the value (for example if this is current then it
would be Amps, Temperature it would be °C etc). The
register readback is 16 Bits, the 5 MSB’s are the Exponent
(=N) and the 11 LSB’s are the mantissa (=Y). Both the
mantissa and exponent are 2’s compliment values, if the
MSB are 1 then they are negative values.
+ IOUT_CAL_OFFSET
(eq. 19)
The IOUT_CAL_GAIN defaults to 1 and
IOUT_CAL_OFFSET defaults to 0 which means the Imon
voltage is stored in the READ_IOUT Command.
IOUT_CAL_GAIN and IOUT_CAL_OFFSET
The ADP4000 measures the voltage on the Imon pin and
stores that in the READ_IOUT Command (0x8C). However
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ADP4000
VR11 VID CODES for the ADP4000
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
OFF
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
1.60000
0
0
0
0
0
0
1
0
1.59375
0
0
0
0
0
0
1
1
1.58750
0
0
0
0
0
1
0
0
1.58125
0
0
0
0
0
1
0
1
1.57500
0
0
0
0
0
1
1
0
1.56875
0
0
0
0
0
1
1
1
1.56250
0
0
0
0
1
0
0
0
1.55625
0
0
0
0
1
0
0
1
1.55000
0
0
0
0
1
0
1
0
1.54375
0
0
0
0
1
0
1
1
1.53750
0
0
0
0
1
1
0
0
1.53125
0
0
0
0
1
1
0
1
1.52500
0
0
0
0
1
1
1
0
1.51875
0
0
0
0
1
1
1
1
1.51250
0
0
0
1
0
0
0
0
1.50625
0
0
0
1
0
0
0
1
1.50000
0
0
0
1
0
0
1
0
1.49375
0
0
0
1
0
0
1
1
1.48750
0
0
0
1
0
1
0
0
1.48125
0
0
0
1
0
1
0
1
1.47500
0
0
0
1
0
1
1
0
1.46875
0
0
0
1
0
1
1
1
1.46250
0
0
0
1
1
0
0
0
1.45625
0
0
0
1
1
0
0
1
1.45000
0
0
0
1
1
0
1
0
1.44375
0
0
0
1
1
0
1
1
1.43750
0
0
0
1
1
1
0
0
1.43125
0
0
0
1
1
1
0
1
1.42500
0
0
0
1
1
1
1
0
1.41875
0
0
0
1
1
1
1
1
1.41250
0
0
1
0
0
0
0
0
1.40625
0
0
1
0
0
0
0
1
1.40000
0
0
1
0
0
0
1
0
1.39375
0
0
1
0
0
0
1
1
1.38750
0
0
1
0
0
1
0
0
1.38125
0
0
1
0
0
1
0
1
1.37500
0
0
1
0
0
1
1
0
1.36875
0
0
1
0
0
1
1
1
1.36250
0
0
1
0
1
0
0
0
1.35625
0
0
1
0
1
0
0
1
1.35000
0
0
1
0
1
0
1
0
1.34375
0
0
1
0
1
0
1
1
1.33750
0
0
1
0
1
1
0
0
1.33125
0
0
1
0
1
1
0
1
http://onsemi.com
24
ADP4000
VR11 VID CODES for the ADP4000
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1.32500
0
0
1
0
1
1
1
0
1.31875
0
0
1
0
1
1
1
1
1.31250
0
0
1
1
0
0
0
0
1.30625
0
0
1
1
0
0
0
1
1.30000
0
0
1
1
0
0
1
0
1.29375
0
0
1
1
0
0
1
1
1.28750
0
0
1
1
0
1
0
0
1.28125
0
0
1
1
0
1
0
1
1.27500
0
0
1
1
0
1
1
0
1.26875
0
0
1
1
0
1
1
1
1.26250
0
0
1
1
1
0
0
0
1.25625
0
0
1
1
1
0
0
1
1.25000
0
0
1
1
1
0
1
0
1.24375
0
0
1
1
1
0
1
1
1.23750
0
0
1
1
1
1
0
0
1.23125
0
0
1
1
1
1
0
1
1.22500
0
0
1
1
1
1
1
0
1.21875
0
0
1
1
1
1
1
1
1.21250
0
1
0
0
0
0
0
0
1.20625
0
1
0
0
0
0
0
1
1.20000
0
1
0
0
0
0
1
0
1.19375
0
1
0
0
0
0
1
1
1.18750
0
1
0
0
0
1
0
0
1.18125
0
1
0
0
0
1
0
1
1.17500
0
1
0
0
0
1
1
0
1.16875
0
1
0
0
0
1
1
1
1.16250
0
1
0
0
1
0
0
0
1.15625
0
1
0
0
1
0
0
1
1.15000
0
1
0
0
1
0
1
0
1.14375
0
1
0
0
1
0
1
1
1.13750
0
1
0
0
1
1
0
0
1.13125
0
1
0
0
1
1
0
1
1.12500
0
1
0
0
1
1
1
0
1.11875
0
1
0
0
1
1
1
1
1.11250
0
1
0
1
0
0
0
0
1.10625
0
1
0
1
0
0
0
1
1.10000
0
1
0
1
0
0
1
0
1.09375
0
1
0
1
0
0
1
1
1.08750
0
1
0
1
0
1
0
0
1.08125
0
1
0
1
0
1
0
1
1.07500
0
1
0
1
0
1
1
0
1.06875
0
1
0
1
0
1
1
1
1.06250
0
1
0
1
1
0
0
0
1.05625
0
1
0
1
1
0
0
1
1.05000
0
1
0
1
1
0
1
0
1.04375
0
1
0
1
1
0
1
1
http://onsemi.com
25
ADP4000
VR11 VID CODES for the ADP4000
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1.03750
0
1
0
1
1
1
0
0
1.03125
0
1
0
1
1
1
0
1
1.02500
0
1
0
1
1
1
1
0
1.01875
0
1
0
1
1
1
1
1
1.01250
0
1
1
0
0
0
0
0
1.00625
0
1
1
0
0
0
0
1
1.00000
0
1
1
0
0
0
1
0
0.99375
0
1
1
0
0
0
1
1
0.98750
0
1
1
0
0
1
0
0
0.98125
0
1
1
0
0
1
0
1
0.97500
0
1
1
0
0
1
1
0
0.96875
0
1
1
0
0
1
1
1
0.96250
0
1
1
0
1
0
0
0
0.95625
0
1
1
0
1
0
0
1
0.95000
0
1
1
0
1
0
1
0
0.94375
0
1
1
0
1
0
1
1
0.93750
0
1
1
0
1
1
0
0
0.93125
0
1
1
0
1
1
0
1
0.92500
0
1
1
0
1
1
1
0
0.91875
0
1
1
0
1
1
1
1
0.91250
0
1
1
1
0
0
0
0
0.90625
0
1
1
1
0
0
0
1
0.90000
0
1
1
1
0
0
1
0
0.89375
0
1
1
1
0
0
1
1
0.88750
0
1
1
1
0
1
0
0
0.88125
0
1
1
1
0
1
0
1
0.87500
0
1
1
1
0
1
1
0
0.86875
0
1
1
1
0
1
1
1
0.86250
0
1
1
1
1
0
0
0
0.85625
0
1
1
1
1
0
0
1
0.85000
0
1
1
1
1
0
1
0
0.84375
0
1
1
1
1
0
1
1
0.83750
0
1
1
1
1
1
0
0
0.83125
0
1
1
1
1
1
0
1
0.82500
0
1
1
1
1
1
1
0
0.81875
0
1
1
1
1
1
1
1
0.81250
1
0
0
0
0
0
0
0
0.80625
1
0
0
0
0
0
0
1
0.80000
1
0
0
0
0
0
1
0
0.79375
1
0
0
0
0
0
1
1
0.78750
1
0
0
0
0
1
0
0
0.78125
1
0
0
0
0
1
0
1
0.77500
1
0
0
0
0
1
1
0
0.76875
1
0
0
0
0
1
1
1
0.76250
1
0
0
0
1
0
0
0
0.75625
1
0
0
0
1
0
0
1
http://onsemi.com
26
ADP4000
VR11 VID CODES for the ADP4000
OUTPUT
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0.75000
1
0
0
0
1
0
1
0
0.74375
1
0
0
0
1
0
1
1
0.73750
1
0
0
0
1
1
0
0
0.73125
1
0
0
0
1
1
0
1
0.72500
1
0
0
0
1
1
1
0
0.71875
1
0
0
0
1
1
1
1
0.71250
1
0
0
1
0
0
0
0
0.70625
1
0
0
1
0
0
0
1
0.70000
1
0
0
1
0
0
1
0
0.69375
1
0
0
1
0
0
1
1
0.68750
1
0
0
1
0
1
0
0
0.68125
1
0
0
1
0
1
0
1
0.67500
1
0
0
1
0
1
1
0
0.66875
1
0
0
1
0
1
1
1
0.66250
1
0
0
1
1
0
0
0
0.65625
1
0
0
1
1
0
0
1
0.65000
1
0
0
1
1
0
1
0
0.64375
1
0
0
1
1
0
1
1
0.63750
1
0
0
1
1
1
0
0
0.63125
1
0
0
1
1
1
0
1
0.62500
1
0
0
1
1
1
1
0
0.61875
1
0
0
1
1
1
1
1
0.61250
1
0
1
0
0
0
0
0
0.60625
1
0
1
0
0
0
0
1
0.60000
1
0
1
0
0
0
1
0
0.59375
1
0
1
0
0
0
1
1
0.58750
1
0
1
0
0
1
0
0
0.58125
1
0
1
0
0
1
0
1
0.57500
1
0
1
0
0
1
1
0
0.56875
1
0
1
0
0
1
1
1
0.56250
1
0
1
0
1
0
0
0
0.55625
1
0
1
0
1
0
0
1
0.55000
1
0
1
0
1
0
1
0
0.54375
1
0
1
0
1
0
1
1
0.53750
1
0
1
0
1
1
0
0
0.53125
1
0
1
0
1
1
0
1
0.52500
1
0
1
0
1
1
1
0
0.51875
1
0
1
0
1
1
1
1
0.51250
1
0
1
1
0
0
0
0
0.50625
1
0
1
1
0
0
0
1
0.50000
1
0
1
1
0
0
1
0
OFF
1
1
1
1
1
1
1
0
OFF
1
1
1
1
1
1
1
1
http://onsemi.com
27
ADP4000
Table 11. PMBus Commands for the ADP4000
Cmd
Code
R/W
Default
Description
#
Byte
Comment
0x01
R/W
0x80
Operation
1
00xx xxxx – Immediate Off
01xx xxxx – Soft Off
1000 xxxx – On (slew rate set by soft--start) - Default
1001 10xx – Margin Low (Act on Fault)
1010 10xx – Margin High (Act on Fault)
0x02
R/W
0x17
ON_OFF_Config
1
Configures how the controller is turned on and off
Bit
Default
7:5
1
Reserved for Future Use
Comment
4
0
This bit is read only. Switching
starts when commanded by the
Control Pin and the Operation
Command, as set in Bits 3:0
3
1
0: Unit ignores OPERATION
commands over the PMBus
1: Unit responds to OPERATION
command, powerup may also
depend upon Control input, as
described in Bit 2
2
1
0: Unit ignores EN pin
1: Unit responds EN pin, powerup
may also depend upon the
Operation Register, as described
for Bit 3
1
1
Control Pin Polarity
0 = Active Low
1 = Active High
0
1
This bit is read only. 1 means that
when the controller is disabled it
will either immediately turn off or
soft off (as set in the Operation
Command)
0x03
W
NA
Clear_Faults
0
Writing any value to this command code will clear all Status Bits
immediately. The SMBus ALERT is deasserted on this command. If
the fault is still present the fault bit shall immediately be asserted
again.
0x10
R/W
0x00
Write Protect
1
The Write_Protect command is used to control writing to the PMBus
device. There is also a lock bit in the Manufacture Specific Registers
that once set will disable writes to all commands until the power to the
ADP4000 is cycled.
Data Byte
0x19
R
0xB0
Capability
1
Comment
1000 0000
Disables all writes except to the
Write_Protect Command
0100 0000
Disables all writes except to the
Write_Protect and Operation
Commands
0010 0000
Disables all writes except to the
Write_Protect, Operation,
ON_OFF_Config and
VOUT_COMMAND Commands
0000 0000
Enables writes to all commands
0001 0000
Disables all writes except to
WRITE_PROTECT, PAGE and all
MFR-SPECIFIC Commands
This command allows the host to get some information on the PMBus
device.
Bit
Default
7
1
PEC (Packet Error Checking is
supported).
6:5
01
Max supported bus speed is
400 kHz.
http://onsemi.com
28
Comment
ADP4000
Cmd
Code
R/W
Default
Description
#
Byte
Comment
4
1
3:0
000
ADP4000 has an SMBus ALERT
pin and ARA is supported.
Reserved
0x20
R
0x20
VOUT_MODE
1
The ADP4000 supports VID mode for programming the output voltage.
0x21
R/W
0x00
VOUT_COMMAND
2
Sets the output voltage using VID.
0x25
R/W
0x0020
VOUT_MARGIN_
HIGH
2
Sets the output voltage when operation command is set to Margin
High. Programmed in VID Mode.
0x26
R/W
0x00B2
VOUT_MARGIN_
LOW
2
Sets the output voltage when operation command is set to Margin
Low. Programmed in VID Mode.
0x38
R/W
0x0001
IOUT_CAL_GAIN
2
Sets the ratio of voltage sensed to current output. Scale is Linear and
is expressed in 1/Ω
0x39
R/W
0x0000
IOUT_CAL_OFFSET
2
This offset is used to null out any offsets in the output current sensing
circuitry. Programmed in Linear mode and units are Amps.
0x4A
R/W
0x0064
IOUT_OC_WARN_
LIMIT
2
This sets the high current--limit. Once this limit is exceeded
IOUT_OC_WARN_LIMIT bit is set in the Status_IOUT register and an
ALERT is generated. This limit is set in Amps and programmed in
Linear Mode.
0x4F
R/W
0x0055
OT_FAULT_LIMIT
2
This sets the temperature limit above which the Over Temp Fault Bit
gets set in the Status_TEMPERATURE Register and the FAULT
Output gets asserted. This limit is set using Linear Mode in °C.
0x51
R/W
0x0046
OT_WARN_LIMIT
2
This sets the temperature limit above which the Over Temp Warn Bit
gets set in the Status_TEMPERATURE Register and the ALERT Output
gets asserted. This limit is set using Linear Mode in °C.
0x52
R/W
0x0000
UT_WARN_LIMIT
2
This sets the temperature limit below which the Under Temp Warn Bit
gets set in the Status_TEMPERATURE Register and the ALERT Output
gets asserted. This limit is set using Linear Mode in °C.
0x55
R/W
0x0010
VIN_OV_FAULT LIMIT
2
This sets the input over voltage fault limit. Once exceeded the VIN
Overvoltage Fault Bit, Bit 7, gets set in the Status Input Register and
the FAULT output is asserted. This limit is set using Linear Mode, in V.
0x57
R/W
0x0010
VIN_OV_WARN LIMIT
2
This sets the input over voltage warn limit. Once exceeded the VIN
Overvoltage Warn Bit, Bit 6, gets set in the Status Input Register and
the ALERT output is asserted. This limit is set using Linear Mode, in V.
0x58
R/W
0x0000
VIN_UV_WARN LIMIT
2
This sets the input under voltage warn limit. Once exceeded the VIN
Undervoltage Warn Bit, Bit 5, gets set in the Status Input Register and
the ALERT output is asserted. This limit is set using Linear Mode, in V.
0x68
R/W
0x012C
POUT_OP_
FAULT LIMIT
2
This sets the output power over power fault limit. Once exceeded Bit 1
of the Status IOUT Command gets set and the FAULT output gets
asserted (if not masked). This limit is set using Linear Mode in W.
0x6A
R/W
0x012C
POUT_OP_
WARN LIMIT
2
This sets the output power over power warn limit. Once exceeded Bit 0
of the Status IOUT Command gets set and the ALERT output gets
asserted (if not masked). This limit is set using Linear Mode in W.
0x78
R
0x00
STATUS BYTE
1
Bit
Name
Comment
7
BUSY
A fault was declared because the
ADP4000 was busy and unable to
respond.
6
OFF
5
VOUT_OV
This bit gets set whenever the
ADP4000 goes into OVP mode.
4
IOUT_OC
This bit gets set whenever the
ADP4000 latches off due to an over
current event.
3
VIN_UV
This bit gets set when the input
voltage falls below its programmed
FAULT limit.
2
TEMP
This bit gets set when the
Temperature, as measured using
the THERMISTOR, exceeds its
THERM and/or high or low limits.
http://onsemi.com
29
This bit is set whenever the
ADP4000 is not switching.
ADP4000
Cmd
Code
0x79
0x7A
R/W
R
R
Default
0x0000
0x00
Description
STATUS WORD
STATUS VOUT
#
Byte
2
1
Comment
1
CML
A Communications, memory or
logic fault has occurred.
0
None of the Above
A fault has occurred which is not
one of the above.
Byte
Bit
Name
Low
7
Res
Reserved
Low
6
OFF
This bit is set whenever the
ADP4000 is not switching.
Low
5
VOUT
_OV
This bit gets set whenever the
ADP4000 goes into OVP mode.
Low
4
IOUT
_OC
This bit gets set whenever the
ADP4000 latches off due to an over
current event.
Low
3
Res
Low
2
TEMP
Low
1
CML
Low
6
None of
the Above
High
7
VOUT
This bit gets set whenever the
measured output voltage goes
outside its power good limits or an
OVP event has taken place, i.e.
any bit in Status VOUT is set.
High
6
Iout/Pout
This bit gets set whenever the
measured output current or power
exceeds its warning limit or goes
into OCP. i.e. any bit in Status IOUT
is set.
High
5
INPUT
This bit gets set if the input voltage,
as measured on VSENSE1 goes
outside its programmed limits. i.e.
any bit in Status VINPUT is set.
High
4
MFR
A manufacturer specific warning or
fault has occurred.
High
3
POWER
_GOOD
The Power--Good signal is
deasserted. Same as Power--Good
in General Status.
High
2
Res
High
1
OTHER
High
0
Res
Description
Reserved
This bit gets set when the
Temperature, as measured using
the THERMISTOR, exceeds its
THERM and/or high or low limits.
A Communications, memory or
logic fault has occurred.
A fault has occurred which is not
one of the above.
Reserved
A Status bit in Status Other is
asserted.
Reserved
Bit
Name
Description
7
VOUT_
OVERVOLTAGE
FAULT
This bit gets set whenever an OVP
Event takes place.
6
VOUT_
OVERVOLTAGE
WARNING
This bit gets set whenever the
measured output voltage goes
above its Power--Good limit.
5
VOUT_
UNDERVOLTAGE
WARNING
This bit gets set whenever the
measured output voltage goes
below its Power--Good limit.
4
VOUT_
UNDERVOLTAGE
FAULT
Not applicable.
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30
ADP4000
Cmd
Code
0x7B
0x7C
0x7D
R/W
R
R
R
Default
0x00
0x00
0x00
Description
STATUS IOUT
STATUS INPUT
STATUS_
TEMPERATURE
#
Byte
1
1
1
Comment
3
VOUT_MAX
Warning
Not supported, Can’t program an
output greater than max VID as
there are no bits to program it.
2
TON_MAX_FAULT
Not supported.
1
TOFF_MAX_
WARNING
Not supported.
0
VOUT_TRACKING_
ERROR
Not supported.
Bit
Name
7
IOUT Overcurrent
Fault
Description
This bit gets set if the ADP4000
latches off due to an OCP Event.
6
Reserved
5
IOUT Overcurrent
Warning
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
POUT Over--Power
Fault
This bit gets set if the measured
POUT exceeds the FAULT Limit.
0
POUT Over--Power
Warning
This bit gets set if the measured
POUT exceeds the Warn Limit.
Bit
Name
7
VIN Overvoltage
FAULT
This bit gets set when the input
voltage goes above its
programmed FAULT limit.
6
VIN Overvoltage
Warning
This bit gets set when the input
voltage goes above its
programmed high limit.
5
Undervoltage
Warning
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
Reserved
Reserved
0
Reserved
Reserved
Bit
Name
Description
7
Overtemperature
FAULT
This bit gets asserted when the
temperature measured by the
Thermistor connected to TTSENSE
exceeds its THERM/FAULT Limit.
6
Overtemperature
Warrning
This bit gets asserted when the
temperature measured by the
Thermistor connected to TTSENSE
exceeds its High Temperature
Limit.
5
Undertemperature
Warrning
This bit gets asserted when the
temperature measured by the
Thermistor connected to TTSENSE
exceeds its Low Temperature Limit.
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
Reserved
Reserved
0
Reserved
Reserved
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31
Reserved
This bit gets set if IOUT exceeds its
programmed high warning limit.
Description
This bit gets set when the input
voltage falls below its programmed
low limit.
ADP4000
Cmd
Code
R/W
Default
0x7E
R
0x00
0x80
R
0x00
Description
STATUS CML
STATUS_ALERT
#
Byte
1
1
Comment
Bit
Name
7
Invalid or
Unsupported
Command Received
Supported
Description
6
Invalid or
Unsupported Data
Received
Supported
5
PEC Failed
Supported
4
Memory Fault
Detected
Not Supported
3
Processor Fault
Detected
Not Supported
2
Reserved
Reserved
1
A communication
fault other than the
ones listed has
occurred.
Supported
0
Other memory or
Logic Fault has
occurred.
Not Supported
Bit
Name
7
Reserved
Reserved
6
Reserved
Reserved
5
VSENSE2 FAULT
4
VSENSE2 OV
WARN
Gets asserted when VSENSE2
exceeds it programmed OV WARN
limits.
3
VSENSE2 OV
WARN
Gets asserted when VSENSE2
exceeds it programmed UV WARN
limits.
2
VMON WARN
Gets asserted when VSENSE2
exceeds it programmed WARN
limits.
1
VMON FAULT
Gets asserted when VSENSE2
exceeds it programmed FAULT
limits.
0
Reserved
Description
Gets asserted when VSENSE2
exceeds it programmed FAULT
limits.
Reserved
0x88
R
0x00
READ_VIN
2
Readback input voltage (measured using VSENSE1).
Voltage is read back in Linear Mode
0x8B
R
0x00
READ_VOUT
2
Readback output voltage. Voltage is read back in VID Mode.
0x8C
R
0x00
READ_IOUT
2
Readback output current. Current is read back in Linear
Mode (Amps).
0x8D
R
0x00
READ_
TEMPERATURE1
2
Readback temperature 1. Thermistor, connected to
TTSENSE is the sense element. Temperature is read back
in Linear Mode °C.
0x96
R
0x00
READ_POUT
2
Readback Output Power, read back in Linear Mode in W’s.
0x99
R
0x41
MFR_ID
1
0x41
Readback using the Block command with the
Byte count equal to 1.
0x9A
R
0x4000
MFR_MODEL
2
0x4000
Readback using the Block command with the
Byte count equal to 2.
0x9B
R
0x01
MFR_REVISION
1
0
Readback using the Block command with the
Byte count equal to 1.
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32
ADP4000
Table 12. Manufacturer Specific Command Codes for the ADP4000
Cmd
Code
R/W
Default
0xD0
R/W
0x00
0xD1
0xD2
R/W
R/W
0x07
0x52
Description
Lock/Reset
Mfr Config
VR Config 1A
#
Byte
1
1
1
Comment
Bit
Name
Description
1
Reset
Resets all registers to their POR Value.
Has no effect if Lock bit is set.
0
Lock
Logic 1 locks all limit values to their
current settings. Once this bit is set, all
lockable registers become read-only
and cannot be modified until the
ADP4000 is powered down and
powered up again. This prevents rogue
programs such as viruses from
modifying critical system limit settings
(Lockable).
Bit
Name
7:6
PSI
Description
5
Reserved
Reserved
4
Reserved
Reserved
3
PMB_TO_EN
2
FAULT_EN
Enable the FAULT pin, Default = 1
1
ALERT_EN
Enable the ALERT pin
0
ENABLE_
MONITOR
When the ENABLE_MONITOR bit is set
to 1, the ADP4000 starts conversions
with the ADC and monitors the voltages
and temperatures.
These bits sets the number of phases
turned on during PSI.
00 = 1 Phase enabled during PSI
01 = 2 Phases enabled during PSI
10 = 3 Phases enabled during PSI
11 = 1 Phase enabled during PSI
PMBus Timeout Enable. When the
PMB_TO_EN bit is set to 1, the PMBus
Timeout feature is enabled. In this state
if, at any point during an PMBus
transaction involving the ADP4000,
activity ceases for more than 35 ms, the
ADP4000 assumes the bus is locked
and releases the bus. This allows the
ADP4000 to be used with SMBus
controllers that cannot handle SMBus
timeouts (Lockable).
Bit
Name
6:4
Phase Enable
Bits
3
VID_EN
When the VID_EN bit is set to 1, the VID
code in the VOUT_COMMAND register
sets the output voltage. When VID_EN is
set to 0, the output voltage follows the
VID input pins.
2
LOOP_EN
When the LOOP_EN bit is set to 1 in
both registers, the control loop test
function is enabled. This allows
measurement of the control loop AC
gain and phase response with
appropriate instrumentation. The control
loop signal insertion pin is IMON. The
control loop output pin is COMP.
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33
Description
000 = Phase 1
001 = Phase 2
010 = Phase 3
011 = Phase 4
100 = Phase 5
101 = Phase 6
All other codes = Phase 6
ADP4000
Cmd
Code
R/W
Default
Description
#
Byte
Comment
1
CLIM_EN
When CLIM_EN is set to 1, the
current--limit time out latchoff functions
normally. When this bit is set to 0 in
both registers, the current--limit latchoff
is disabled. In this state, the part can be
in current--limit indefinitely.
0
Reserved
Reserved
0xD3
R/W
0x52
VR Config 1B
1
This register is for security reasons. It has the same format as
register 0xD2. Bits need to be set in both registers for the function to
take effect.
0xD4
R/W
0x03
Ton Delay
1
This resister sets TD1, TD3 and TD5 delays for the soft--start
sequence. The current--limit latchoff timer is 4 times the programmed
delay time.
000 = 0.5 ms
001 = 1 ms
010 = 1.5 ms
011 = 2 ms = default
100 = 2.5 ms
101 = 3 ms
110 = 3.5 ms
111 = 4 ms
0xD5
R/W
0x02
Ton Rise
1
This register sets the soft--start voltage slew rate, and hence TD2
and TD4, of the soft--start sequence.
000 = 0.1 V/ms
001 = 0.3 V/ms
010 = 0.5 V/ms = default
011 = 0.7 V/ms
100 = 0.9 V/ms
101 = 1.1 V/ms
110 = 1.3 V/ms
111 = 1.5 V/ms
0xD6
R/W
0x01
Ton Transition
1
This register sets the slew rate during a dynamic VID.
000 = 1 V/ms
001 = 3 V/ms = default
010 = 5 V/ms
011 = 7 V/ms
100 = 9 V/ms
101 = 11 V/ms
110 = 13 V/ms
111 = 15 V/ms
0xD7
R
0x00
VSENSE2 Voltage
2
This is a 16 bit value that reports back the voltage on the VSENSE2
Pin. Can be configured to measure the input Voltage Current. 16 Bit
Value between 0 and 2.0 V. Voltage is reported using Linear Mode.
0xD8
R
0x00
EN/VTT Voltage
2
This is a 16 bit value that reports back the voltage on the VTT Pin.
Voltage is reported using Linear Mode.
0xDA
R
0x00
VMON Voltage
2
This is a 16 bit value that reports back the voltage measured
between FB and FBRTN. Voltage is reported using Linear Mode.
0xDB
R/W
0x00
VOUT_TRIM
1
Offset Command Code for VOUT, max ±200 mV.
0xDC
R/W
0x00
VOUT_CAL
1
Offset Command Code for VOUT, max ±200 mV.
0xDE
R/W
0x10
Load Line Calibration
1
This value sets the internal load line attenuation DAC calibration
value. The maximum load line is controlled externally by setting the
gain of the current sense amplifier as explained in the applications
section. This maximum load line can then be adjusted from 100% to
0% in 30 steps. Each LSB represents a 3.33% change in the load
line.
00000 = No Load Line
10000 = 50% of external load line
11111 = 100% of external Load Line
0xDF
R/W
0x00
Load Line Set
1
This value sets the internal load line attenuation DAC value. The
maximum load line is controlled externally by setting the gain of the
current sense amplifier as explained in the applications section. This
maximum load line can then be adjusted from 100% to 0% in 30
steps. Each LSB represents a 3.33% change in the load line.
00000 = No Load Line
10000 = 50% of external load line
11111 = 100% of external Load Line
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34
ADP4000
Cmd
Code
R/W
Default
Description
#
Byte
Comment
0xE0
R/W
0x00
PWRGD Hi Threshold
1
This value sets the PWRGD Hi Threshold and the CROWBAR
Threshold:
Code = 00, PWRGD HI = 300 mV (default)
Code = 01, PWRGD HI = 250 mV
Code = 10, PWRGD HI = 200 mV
Code = 11, PWRGD HI = 150 mV
0xE1
R/W
0x00
PWRGD Lo Threshold
1
This value sets the PWRGD Lo Threshold:
Code = 000, PWRGD Lo = -500 mV (default)
Code = 001, PWRGD Lo = -450 mV
Code = 010, PWRGD Lo = -400 mV
Code = 011, PWRGD Lo = -350 mV
Code = 100, PWRGD Lo = -300 mV
Code = 101, PWRGD Lo = -250 mV
Code = 110, PWRGD Lo = -200 mV
Code = 111, PWRGD Lo = -150 mV
0xE2
R/W
0x10
Current--Limit Threshold
1
This value sets the internal current--limit adjust value. The default
current--limit is programmed using a resistor to ground on the LIMIT
pin. The value of this register adjusts this value by a percentage
between 50% and 146.7%. Each LSB represents a 3.33% change in
the threshold.
11111 = 146.7% of external current--limit
10000 = 100% of external current--limit (default)
00000 = 50% of external current--limit
0xE3
R/W
0x10
Phase Bal SW1
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE4
R/W
0x10
Phase Bal SW2
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE5
R/W
0x10
Phase Bal SW3
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE6
R/W
0x10
Phase Bal SW4
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE7
R/W
0x10
Phase Bal SW5
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xE8
R/W
0x10
Phase Bal SW6
1
These values adjust the gain of the internal phase balance
amplifiers. The nominal gain is set to 5. These registers can adjust
the gain by ±25% from 3.75 to 6.25.
Code = 00000, Gain of 3.75
Code = 10000, Gain of 5 (default)
Code = 11111, Gain of 6.25
0xEE
R/W
0x0050
VRHOT RESET LIMIT
2
This is the temperature below which the VTHOT will de--assert.
0xEF
R/W
0x0002
VSENSE2 High Limit
2
VSENSE2 voltage high limit.
0xF0
R/W
0x0000
VSENSE2 Low Limit
2
VSENSE2 voltage low limit.
0xF1
R/W
0x0002
VSENSE2 FAULT Limit
2
VSENSE2 voltage FAULT limit.
0xF5
R/W
0x0002
VMON FAULT Limit
2
VMON FAULT Limit.
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35
ADP4000
Cmd
Code
R/W
Default
Description
0xF6
R/W
0x0002
VMON Warn Limit
2
VMON Warn Limit.
0xF7
R/W
0x07CE
TTSENSE Gain
2
Gain information used to convert TTSENSE Voltage to temperature.
0xF8
R/W
0x007B
TTSENSE Offset
2
Offset information used to convert TTSENSE Voltage to
temperature.
0xF9
R/W
0x00
Mask ALERT
1
Bit
Name
7
Mask VOUT
Masks any ALERT caused by bits in
Status VOUT Register.
6
Mask IOUT
Masks any ALERT caused by bits in
Status IOUT Register.
5
Mask Input
Masks any ALERT caused by bits in
Status Input Register.
4
Mask
Temperature
Masks any ALERT caused by bits in
Status Temperature Register.
3
Mask CML
Masks any ALERT caused by bits in
Status CML Register.
2
VMON
Masks any ALERT caused by VMON
exceeding its high or low limit.
1
VSENSE2
Masks any ALERT caused by VSENSE2
exceeding its high or low limit.
0
Mask POUT
Bit
Name
7
Mask VOUT
Masks any FAULT caused by bits in
Status VOUT Register.
6
Mask IOUT
Masks any FAULT caused by bits in
Status IOUT Register.
5
Mask Input
Masks any FAULT caused by bits in
Status Input Register.
4
Mask
Temperature
Masks any FAULT caused by bits in
Status Temperature Register.
3
Mask CML
Masks any FAULT caused by bits in
Status CML Register.
2
VMON
Masks any FAULT caused by VMON
exceeding its high or low limit.
1
VSENSE2
0
Mask POUT
0xFA
0xFB
0xFC
R/W
R/W
R
0x00
0x00
0x00
Mask FAULT
General Status
Phase Status
#
Byte
1
1
1
Comment
Bit
Name
7
FAULT
6
ALERT
5
POWER--GOOD
4
RDY
Description
Masks any ALERT caused by POUT
exceeding its programmed limit.
Description
Masks any FAULT caused by VSENSE2
exceeding its high or low limit.
Masks any FAULT caused by POUT
exceeding its programmed limit.
Description
Replaced by Bit 3 of the Status Word
Command.
Bit
Name
7
Phase 6
This bit is set to 1 when Phase 6 is
enabled.
6
Phase 5
This bit is set to 1 when Phase 5 is
enabled.
5
Phase 4
This bit is set to 1 when Phase 4 is
enabled.
4
Phase 3
This bit is set to 1 when Phase 3 is
enabled.
3
Phase 2
This bit is set to 1 when Phase 2 is
enabled.
http://onsemi.com
36
Description
ADP4000
PACKAGE DIMENSIONS
LFCSP48 7x7, 0.5P
CASE 932AD--01
ISSUE O
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
D1
PIN ONE
REFERENCE
E1
E
DIM
A
A1
A3
b
D
D1
D2
E
E1
E2
e
H
K
L
M
0.20 C
TOP VIEW
0.20 C
H
(A3)
0.10 C
A
NOTE 4
0.08 C
SIDE VIEW
A1
C
4X
M
D2
K
4X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
7.00 BSC
6.75 BSC
4.95
5.25
7.00 BSC
6.75 BSC
4.95
5.25
0.50 BSC
-----12 °
0.25
-----0.30
0.50
-----0.60
SEATING
PLANE
SOLDERING FOOTPRINT*
M
7.30
13
25
5.14
1
E2
PIN 1
INDICATOR
48X
L
5.14
1
48
e
37
48X
BOTTOM VIEW
48X
0.63
b
0.10 C A B
0.05 C
7.30
PACKAGE
OUTLINE
NOTE 3
48X
0.50
PITCH
0.28
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and solder
details, please download the ON Semiconductor Soldering a
Mounting Techniques Reference Manual, SOLDERRM/D.
FlexMode is a trademark of Analog Devices, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
ADP4000/D