TRIQUINT AGR09130EU

t Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
Introduction
Table 1. Thermal Characteristics
The AGR09130E is a high-voltage, laterally diffused
metal oxide semiconductor (LDMOS) RF power transistor suitable for cellular band, code division multiple
access (CDMA), global system for mobile communication (GSM), enhanced data for global evolution
(EDGE), and time division multiple access (TDMA)
single and multicarrier class AB wireless base station
amplifier applications. This device is manufactured
on an advanced LDMOS technology offering stateof-the-art performance, and reliability. Packaged in
an industry-standard package incorporating internal
matching and capable of delivering a minimum output power of 130 W, it is ideally suited for today's RF
power amplifier applications.
7
AGR09130EU
48
5
AGR09130EF
Figure 1. Available Packages
Features
Typical performance ratings are for the EDGE
format: 3GPP GSM 05.05:
— Output power (POUT): 50 W.
— Power gain: 17.8 dB.
— Modulation spectrum:
@ ±400 kHz = –60 dBc.
@ ±600 kHz = –72 dBc.
— Error vector magnitude (EVM) = 1.8%.
— Return loss: –10 dB.
High-reliability, gold-metalization process.
Internally matched.
High gain, efficiency, and linearity.
Integrated ESD protection.
Si LDMOS.
Industry-standard packages.
P1dB of 130 W minimum output power.
Parameter
Thermal Resistance,
Junction to Case:
AGR09130EU
AGR09130EF
Sym
R
JC
Value
Unit
0.5
0.5
°C/W
Table 2. Absolute Maximum Ratings*
Parameter
Drain-source Voltage
Gate-source Voltage
Drain Current—Continuous
Total Dissipation at TC = 25 °C:
AGR09130EU
AGR09130EF
Derate Above 25 C:
AGR09130EU
AGR09130EF
Operating Junction Temperature
Storage Temperature Range
Sym Value
VDSS
65
VGS –0.5, 15
ID
15
PD
TJ
Unit
Vdc
Vdc
Adc
350
350
W
2.0
2.0
200
W/°C
TSTG –65, 150
°C
°C
* Stresses in excess of the absolute maximum ratings can cause
permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at
these or any other conditions in excess of those given in the
operational sections of the data sheet. Exposure to absolute
maximum ratings for extended periods can adversely affect
device reliability.
Table 3. ESD Rating*
AGR09130E
Minimum (V)
Class
HBM
MM
CDM
500
50
1500
1B
A
4
* Although electrostatic discharge (ESD) protection circuitry has
been designed into this device, proper precautions must be
taken to avoid exposure to ESD and electrical overstress (EOS)
during all handling, assembly, and test operations. PEAK
Agere Devices
employs a human-body model (HBM), a machine model (MM),
and a charged-device model (CDM) qualification requirement in
order to determine ESD-susceptibility limits and protection
design evaluation. ESD voltage thresholds are dependent on the
circuit parameters used in each of the models, as defined by
JEDEC's JESD22-A114B (HBM), JESD22-A115A (MM), and
JESD22-C101A (CDM) standards.
Caution: MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and packaging MOS devices should be
observed.
Electrical Characteristics
Recommended operating conditions apply unless otherwise specified: TC = 30 °C.
Table 4. dc Characteristics
Parameter
Symbol
Min
Typ
Max
Off Characteristics
200 µA)
Drain-source Breakdown Voltage (VGS = 0, ID = 400
Unit
V(BR)DSS
65
—
—
Vdc
Gate-source Leakage Current (VGS = 5 V, VDS = 0 V)
IGSS
—
—
µAdc
Zero Gate Voltage Drain Leakage Current (VDS = 28 V, VGS = 0 V)
IDSS
—
—
4
200
12
Forward Transconductance (VDS = 10 V, ID = 1 A)
GFS
—
9
—
S
µAdc
On Characteristics
Gate Threshold Voltage (VDS = 10 V, ID = 400 µA)
VGS(TH)
—
—
4.8
Vdc
Gate Quiescent Voltage (VDS = 26 V, IDQ = 1000 mA)
VGS(Q)
—
3.8
—
Vdc
Drain-source On-voltage (VGS = 10 V, ID = 1 A)
VDS(ON)
—
0.08
—
Vdc
Symbol
Min
Typ
Max
Unit
Output Capacitance
(VDS = 28 Vdc, VGS = 0, f = 1 MHz)
COSS
—
72
—
pF
Transfer Capacitance
(VDS = 28 Vdc, VGS = 0, f = 1 MHz)
CRSS
—
3.0
—
pF
Table 5. RF Characteristics
Parameter
Dynamic Characteristics
Test Fixture)
Functional Tests (in Supplied
Agere Systems
Supplied Test Fixture)
(Test frequencies (f) = 920 MHz, 940 MHz, 960 MHz)
Linear Power Gain
(VDS = 26 V, POUT = 50 W, IDQ = 1000 mA)
Output Power
(VDS = 26 V, 1 dB compression, IDQ = 1000 mA)
GL
16
18
—
dB
P1dB
130
150
—
W
—
55
—
%
IM3
—
30
—
dBc
VSWRI
—
2:1
—
—
Drain Efficiency
(VDS = 26 V, POUT = P1dB, IDQ = 1000 mA)
Third-order Intermodulation Distortion
(100 kHz spacing, VDS = 26 V, POUT = 120 WPEP, IDQ = 1000 mA)
Input VSWR
Ruggedness
(VDS = 26 V, POUT = 130 W, IDQ = 1000 mA, f = 940 MHz,
VSWR = 5:1, all angles)
—
No degradation in output
power.
Draft Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
Draft Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
Test Circuit Illustrations for AGR09130E
VGG
R4
R3
R3
FB2
FB1
C23
C24
C25
VDD
C29 C12
R2
C11
C10
C9
C8
Z16
Z11
Z17
C13
R1
Z1
RF INPUT
C1 Z2
C2
Z3
Z4
C3
Z5
Z6
Z7
Z8
Z12
Z13
C15
C14
Z10
C17 C19 C26 C20 C28 C21 C22 C27
Z9
2
1
3
C4
C7
C5
DUT
Z14 C16 Z15
RF
OUTPUT
PINS:
1. DRAIN
2. GATE
3. SOURCE
C6
A. Schematic
2
3
1
MHz
Parts List:
Microstrip line:
Z1 0.834 in. x 0.066 in.; Z2 0.066 in. x 0.066 in.; Z3 0.290 in. x 0.066 in.; Z4 0.050 in. x 0.180 in.; Z5 0.650 in. x 0.180 in.;
Z6 0.050 in. x 0.800 in.; Z7 0.132 in. x 0.800 in.; Z8 0.105 in. x 0.800 in.; Z9 0.050 in. x 0.800 in.; Z10 0.423 in. x 0.700 in.;
Z11 0.227 in. x 0.700 in.; Z12 0.920 in. x 0.180 in.; Z13 0.040 in. x 0.180 in.; Z14 0.470 in. x 0.066 in.; Z15 0.495 in. x 0.066 in.;
Z16 1.340 in. x 0.050 in.: Z17 1.100 in. x 0.050 in.
AT C ® chip capacitor:
C1, C8, C16, C17: 47 pF 100B470JW; C3 1.5 pF 100B1R5BW; C4: 6.8 pF 100B6R8BW; C13, C14: 12 pF 100B120JW;
C5, C6, 10 pF 100B100JW; C7 5.6 pF 100B5R6BW; C9: 100 pF 100B101JW.
0603 chip capacitor: C10, C19: 220 pF.
K emet®: chip capacitor, C11, C26: 0.01 µF C1206C103KRAC7800; C12, C20, C23, C28, C29: 0.1 µF C1206C104KRAC7800.
J ohans on G iga-Trim® variable capacitor, 27291SL: C2, C15: 0.8 pF to 8 pF.
S prague ® tantalum chip capacitor (35 V): C21, C24, C25, C27 10 µF; C22 22 µF.
1206 size fixed film chip resistor (0.25 W): R1: 51 RM73B2B510J; R2 56 k RM73B2B563J; R3 12 RM73B2B120J;
R4 1.2 k RM73B2B122J; R5 RM73B2B4R3J 4.3 .
K reger ® ferrite bead: FB1 2743019447; FB2 2743021447.
Taconic ® ORCER RF-35: board material, 1 oz. copper, 30 mil thickness, r = 3.5.
B. Component Layout
Figure 2. AGR09130E Test Circuit
Typical Performance Characteristics
0.11
07
0.
0
45
1.0
0.9
0.8
55
0.4
EN
75
T
(+
j
X/
Z
5
0.4
0.2
PO
N
0.6
CE
CO
M
RE
AC
TA
N
0.8
0
1.
f1
0
1.
U CT
IVE
IN D
85
80
15
0
4
6
ZL
0.1
0.4
1.8
2.0
1.4
1.6
1.2
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.2
0.1
0.2
0.3
0.0
0.4
0.0 Ð > W A V EL E
N GTH
S TOW
A RD
0.0
0.49
GEN
ERA
0.48
± 180
TO
170
RÐ
0.4
>
7
1
60
90
70
0.6
0.2
A D <Ð
RESISTANCE COMPONENT (R/Zo), OR CONDUCTANCE COMPONENT (G/Yo)
0.2
f3
o)
jB/ Y
E (NC
ZS
0.6
f1
8
0.
0
0.2
TA
-85
0.48
0.4
1.
RD L O
TOW A
7
TH S
-170
EN G
V EL
A
W
-90
-160
0.49
40
8
920 (f1)
940
960 (f3)
Yo)
jB/
E (+
NC
f3
0.1
MHz (f)
R
TA
EP
SC
SU
0.15
0.35
80
0.3
Z0 = 5 Ω
,O
o)
T
CI
PA
CA
E
IV
90
0.
0.0
4
0.
5
14
0
70
0.
06
0.
44
13
5 65
0.
43
0.
110
0.14
0.36
1.4
0
12
0.6 60
2
0.4
0.37
0.7
1
0.4
8
0.13
0.38
50
0.4
9
0.0
0.0
0.39
100
0.12
1.2
0.1
ZL Ω
ZS Ω
(Complex Source Impedance) (Complex Optimum Load Impedance)
0.9 + j0.96
0.55 – j1.06
0.89 + j1.09
0.55 – j0.77
0.84 + j1.35
0.58 – j0.66
GATE (2)
ZS
DRAIN (1)
ZL
SOURCE (3)
INPUT MATCH
DUT
OUTPUT MATCH
Figure 3. Series Equivalent Input and Output Impedances
35
Draft Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
Draft Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
940 MHz
180
POWER OUT (POUT) (W)Z
200
160
960 MHz
140
180
POUT
160
140
920 MHz
120
100
80
PIN
120
100
960 MHz
80
60
60
40
920 MHz
20
0
0.00
0.50
1.00
1.50
2.00
2.50
40
940 MHz
3.00
DRAIN EFFICIENCY (Eff) (%)Z
200
20
0
4.00
3.50
INPUT POWER (PIN) (W)Z
VDD = 26 V, IDQ = 1.0 A, TF = 30 °C, FORMAT = CW.
Figure 4. POUT and Drain Efficiency vs. PIN
POWER GAIN (PG) (dB)Z
18.5
-2
PG @ POUT = 50 W
-4
18
PG @ POUT = 130 W
17.5
-6
-8
17
-10
16.5
RL
16
-12
15.5
-14
15
-16
14.5
-18
14
920
925
930
935
940
945
950
955
FREQUENCY (MHz)Z
VDD = 26 V, IDQ = 1.0 A, TF = 30 °C.
Figure 5. Power Gain and Return Loss vs. Frequency
-20
960
INPUT RETURN LOSS (RL) (dB)Z
0
19
Typical Performance Characteristics (continued)
100
19
PG
17
960 MHz
16
80
920 MHz
940 MHz
15
90
70
60
Eff
14
50
13
960 MHz
12
40
920 MHz
940 MHz
30
11
20
10
10
200
0
50
100
POWER OUT (POUT) (W)Z
150
DRAIN EFFICIENCY (Eff) (%)Z
POWER GAIN (PG) (dB)Z
18
VDD = 26 VDC, IDQ = 1.0 A, TF = 30 °C, FORMAT = CW.
Figure 6. Power Gain and Drain Efficiency vs. Power Out
MODULATION SPECTRUM
(dBc)Z
-10
Eff
35
-20
30
-30
25
PG
-40
20
15
-50
+/- 400 kHz
-60
+/- 600 kHz
-70
-80
920
10
925
930
935
940
945
950
5
955
POWER GAIN (dB) AND DRAIN
EFFICIENCY (%)Z
40
0
0
960
FREQUENCY (MHz)Z
VDD = 26 V, IDQ = 1.0 A, PO = 50 W, TF = 30 °C, EDGE FORMAT = 3GPP GSM 05.05.
Figure 7. ACP, Power Gain, and Efficiency vs. Frequency
Draft Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
Draft Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
Typical Performance Characteristics (continued)
MODULATION SPECTRUM (dBc)Z
0
-10
-20
-30
-40
-50
+/-400 kHz
-60
-70
-80
-90
+/-600 kHz
35
37
39
41
43
45
POWER OUT (POUT) (dBm)Z
47
49
FREQUENCY = 940 MHz, VDD = 26 VDC, IDQ = 1.0 A, TF = 30 °C, EDGE FORMAT = 3GPP GSM 05.05.
Figure 8. EDGE Modulation Spectrum vs. Power Out
6
960 MHz
5
EVM (%)Z
4
3
940 MHz
920 MHz
2
1
0
35.00
37.00
39.00
41.00
43.00
45.00
47.00
49.00
POWER OUT (POUT) (dBm)Z
VDD = 26 VDC, IDQ = 1.0 A, TF = 30 °C, EDGE FORMAT = 3GPP GSM 05.05
Figure 9. EVM vs. Power Out
Typical Performance Characteristics (continued)
0.00
-10.00
IMD dBcZ
-20.00
IM3+/-
-30.00
-40.00
-50.00
IM5+/IM7+/-
-60.00
-70.00
0.00
50.00
100.00
150.00
POWER OUT (POUT) WPEPZ
200.00
F1 = 940.0 MHz, F2 = 940.1 MHz, VDD = 26 V, IDQ = 1.0 A, TF = 30 °C.
Figure 10. 2-Tone IMD vs. Po
Draft Copy Only
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MOSFET
AGR09130E
130 W, 921 MHz—960 MHz, N-Chann el E-Mode, Latera l MOSFET
Package Di mensions
All dimensions are in inches. Tolerances are ±0.005 in. unless specified.
AGR09130EU
PINS:
1. DRAIN
2. GATE
3. SOURCE
1
AGERE
PEAK
DEVICES
M-AGR21125U
AGR09130EU
3
YYWWUR
XXXX
XXXXZZ
Z
2
AGR09130EF
PINS:
1. DRAIN
2. GATE
3. SOURCE
1
AGERE
PEAK DEVICES
M-AGR21125F
AGR09130EF
3
YYWWUR
XXXX
ZZZZZZZ
2
Marking Notes:
Line 1: Brand & Manufacturer
Line 2: Part Number
Line 3: 4 digit Trace Code first two digits are letters followed by two digit number
AGR09130E
130 W, 921 MHz—960 MHz, N-Channel E-Mode, Lateral MO SFET
Ordering Information
Devi ce Code
Package
Availability
AGR09130E
AGR09130EU (surface-mount)
Tray
AGR09130EF (flanged)
Tray
Johanson and Giga-Trim are registered trademarks of Johanson Manufacturing Corporation.
ATC is a registered trademark of American Technical Ceramics Corporation.
Kemet is a registered trademark of KRC Trade Corporation.
Sprague is a registered trademark of Sprague Electric Company Corporation.
Kreger is a registered trademark of Kreger Components, Inc.
Taconic is a registered trademark of Tonoga Limited DBA Taconic Plastics Ltd.
December 2005
Rev B