Full/Low Speed USB Digital Isolator ADuM4160 USB 2.0 compatible Low and full speed data rate: 1.5 Mbps and 12 Mbps Bidirectional communication Short-circuit protection for xD+ and xD− lines 3.3 V and 5 V (dual mode power configuration) operation 7 mA maximum upstream supply current @ 1.5 Mbps 8 mA maximum upstream supply current @ 12 Mbps 2.3mA maximum upstream idle current Class 3A contact ESD performance per ANSI/ESD STM5.1-2007 High temperature operation: 105°C High common-mode transient immunity: >25 kV/μs 16-lead SOIC wide-body package RoHS compliant Safety and regulatory approvals UL recognition: 5000 V rms for 1 minute per UL 1577 (pending) CSA Component Acceptance Notice #5A IEC 60601-1: 125 V rms (reinforced) IEC 60950-1: 380 V rms (reinforced) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 846 V peak APPLICATIONS USB peripheral isolation Isolated USB hub GENERAL DESCRIPTION The ADuM41601 is a USB port isolator, based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics and are easily integrated with low and full speed USB-compatible peripheral devices. 1 FUNCTIONAL BLOCK DIAGRAM VBUS1 1 16 VBUS2 GND1 2 15 GND2 VDD1 3 14 VDD2 PDEN 4 13 SPD SPU 5 12 PIN REG REG UD– 6 11 DD– UD+ 7 10 DD+ GND1 8 9 GND2 PU LOGIC PD LOGIC 08171-001 FEATURES Figure 1. Many microcontrollers implement USB so that it presents only the D+ and D− lines to external pins. This is desirable in many cases because it minimizes external components and simplifies the design; however, this presents particular challenges when isolation is required. USB lines must automatically switch between actively driving D+/D−, receiving data, and allowing external resistors to set the idle state of the bus. The ADuM4160 provides mechanisms for detecting the direction of data flow and control over the state of the output buffers. Data direction is determined on a packet-by-packet basis. The ADuM4160 uses the edge detection based iCoupler technology in conjunction with internal logic to implement a transparent, easily configured, upstream facing port isolator. Isolating an upstream facing port provides several advantages in simplicity, power management, and robust operation. The isolator has propagation delay comparable to that of a standard hub and cable. It operates with the supply voltage on either side ranging from 3.1 V to 5.5 V, allowing connection directly to VBUS by internally regulating the voltage to the signaling level. The ADuM4160 provides isolated control of the pull-up resistor to allow the peripheral to control connection timing. The device has a low idle current; a suspend mode is required. Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329. Other patents pending. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADuM4160 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................7 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................8 General Description ......................................................................... 1 Applications Information .............................................................. 10 Functional Block Diagram .............................................................. 1 Functional Description .............................................................. 10 Revision History ............................................................................... 2 Product Usage ............................................................................. 10 Specifications..................................................................................... 3 Compatibility of Upstream Applications .................................11 Electrical Characteristics ............................................................. 3 Power Supply Options ................................................................11 Package Characteristics ............................................................... 4 Printed Circuit Board Layout (PCB) ........................................11 Regulatory Information ............................................................... 4 DC Correctness and Magnetic Field Immunity ......................11 Insulation and Safety-Related Specifications ............................ 5 Insulation Lifetime ..................................................................... 12 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 5 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14 Recommended Operating Conditions ...................................... 6 Absolute Maximum Ratings............................................................ 7 REVISION HISTORY 9/09—Rev. 0 to Rev. A Added USB Logo, Reformatted Page 1 .......................................... 1 7/09—Revision 0: Initial Version Rev. A | Page 2 of 16 ADuM4160 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 4.5 V ≤ VBUS1 ≤ 5.5 V, 4.5 V ≤ VBUS2 ≤ 5.5 V; 3.1 V ≤ VDD1 ≤ 3.6 V, 3.1 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Each voltage is relative to its respective ground. Table 1. Parameter DC SPECIFICATIONS Total Supply Current 1 1.5 Mbps VDD1 or VBUS1 Supply Current VDD2 or VBUS2 Supply Current 12 Mbps VDD1 or VBUS1 Supply Current VDD2 or VBUS2 Supply Current Idle Current VDD1 or VBUS1 Idle Current Input Currents Single-Ended Logic High Input Threshold Single-Ended Logic Low Input Threshold Single-Ended Input Hysteresis Differential Input Sensitivity Logic High Output Voltages Logic Low Output Voltages VDD1 and VDD2 Supply Undervoltage Lockout VBUS1 Supply Undervoltage Lockout VBUS2 Supply Undervoltage Lockout Transceiver Capacitance Capacitance Matching Full Speed Driver Impedance Impedance Matching SWITCHING SPECIFICATIONS, I/O PINS LOW SPEED Low Speed Data Rate Propagation Delay 2 Side 1 Output Rise/Fall Time (10% to 90%) Low Speed Low Speed Differential Jitter, Next Transition Low Speed Differential Jitter, Paired Transition SWITCHING SPECIFICATIONS, I/O PINS FULL SPEED Full Speed Data Rate Propagation Delay2 Symbol Typ Max Unit Test Conditions IDD1 (L) IDD2 (L) 5 5 7 7 mA mA 750 kHz logic signal rate CL = 450 pF 750 kHz logic signal rate CL = 450 pF IDD1 (F) IDD2 (F) 6 6 8 8 mA mA 6 MHz logic signal rate CL = 50 pF 6 MHz logic signal rate CL = 50 pF 1.7 +0.1 2.3 +1 mA μA IDD1 (I) IDD−, IDD+, IUD+, IUD−, ISPD, IPIN, ISPU, IPDEN VIH VIL VHST VDI VOH VOL VUVLO VUVLOB1 VUVLOB2 CIN ZOUTH Min −1 2.0 0.8 0.4 0.2 2.8 0 2.4 3.5 3.5 3.6 0.3 3.1 4.35 4.4 10 10 4 20 10 1.5 tPHLL, tPLHL tRL/tFL 325 75 |tLJN| |tLJP| 300 45 15 tPHLF, tPLHF 20 Output Rise/Fall Time (10% to 90%) Full Speed tRF/tFF 4 Full Speed Differential Jitter, Next Transition Full Speed Differential Jitter, Paired Transition |tFJN| |tFJP| 12 60 70 20 3 1 Rev. A | Page 3 of 16 V V V V V V V V V pF % Ω % 0 V ≤ VDD-, VDD+, VUD+,VUD−, VSPD, VPIN, VSPU, VPDEN ≤ 3.0 |VXD+ − VXD−| RL = 15 kΩ, VL = 0 V RL = 1.5 kΩ, VL = 3.6 V UD+, UD−, DD+, DD− to ground Mbps CL = 50 pF ns CL = 50 pF, SPD = SPU = low VDD1, VDD2 = 3.3 V ns CL = 450 pF SPD = SPU = low VDD1, VDD2 = 3.3 V ns CL = 50 pF ns CL = 50 pF Mbps CL = 50 pF ns CL = 50 pF SPD = SPU = high, VDD1, VDD2 = 3.3 V ns CL = 50 pF SPD = SPU = high, VDD1, VDD2 = 3.3 V ns CL = 50 pF ns CL = 50 pF ADuM4160 Parameter For All Operating Modes Common-Mode Transient Immunity At Logic High Output 3 At Logic Low Output3 Symbol Min Typ |CMH| 25 35 |CML| 25 35 Max Unit Test Conditions kV/μs VUD+, VUD−, VDD+, VDD− = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V kV/μs VUD+, VUD−, VDD+, VDD− = 0 V, VCM = 1000 V, transient magnitude = 800 V 1 The supply current values for the device running at a fixed continuous data rate at 50% duty cycle alternating J and K states. Supply current values are specified with USB-compliant load present. 2 Propagation delay of the low speed DD+ to UD+ or DD− to UD− in either signal direction is measured from the 50% level of the rising or falling edge, to the 50% level of the rising or falling edge of the corresponding output signal. 3 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. PACKAGE CHARACTERISTICS Table 2. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction-to-Ambient Thermal Resistance Symbol RI-O CI-O CI θJA Min Typ 1012 2.2 4.0 45 Max Unit Ω pF pF °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside 1 Device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, and Pin 16 are shorted together. 2 Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM4160 is approved by the organizations listed in Table 3. Refer to Table 8 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 3. UL (Pending) Recognized under 1577 component recognition program 1 Single Protection 5000 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 380 V rms (537 V peak) maximum working voltage Reinforced insulation per IEC 60601-1 125 V rms (176 V peak) maximum working voltage File 205078 VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 846 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM4160 is proof tested by applying an insulation test voltage ≥6000 V rms for 1 sec (current leakage detection limit = 10 μA). In accordance with DIN V VDE V 0884-10, each ADuM4160 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. Rev. A | Page 4 of 16 ADuM4160 INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Value 5000 L(I01) 8.0 min Unit Conditions V rms 1 minute duration mm Measured from input terminals to output terminals, shortest distance through air 7.7 min mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Insulation distance through insulation >175 V DIN IEC 112/VDE 0303 Part 1 IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Minimum External Tracking (Creepage) L(I02) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 5. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 846 1590 V peak V peak 1375 1018 V peak V peak VTR 6000 V peak TS IS1 RS 150 550 >109 °C mA Ω VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure (see Figure 2) Case Temperature Side 1+ Side 2 Current Insulation Resistance at TS VIO = 500 V 500 400 300 200 100 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 08171-002 SAFE OPERATING VDD1 CURRENT (mA) 600 Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. A | Page 5 of 16 ADuM4160 RECOMMENDED OPERATING CONDITIONS Table 6. Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times 1 Symbol TA VBUS1, VBUS2 Min −40 3.1 Max +105 5.5 1.0 Unit °C V ms All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. Rev. A | Page 6 of 16 ADuM4160 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VBUS1, VBUS2, VDD1, VDD2) 1 Input Voltage (VUD+,VUD−, VSPU)1, 2 Output Voltage (VDD−, VDD+, VSPD, VPIN)1, 2 Average Output Current per Pin 3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients 4 Rating −65°C to +150°C −40°C to +105°C −0.5 V to +6.5 V −0.5 V to VDDI + 0.5 V Table 8. Maximum Continuous Working Voltage1 −0.5 V to VDDO + 0.5 V −10 mA to +10 mA −10 mA to +10 mA −100 kV/μs to +100 kV/μs Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Max 537 Unit V peak Constraint 50-year minimum lifetime 848 V peak 537 V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 848 V peak 537 V peak 1 All voltages are relative to their respective ground. VDDI, VBUS1, and VDD2, VBUS2 refer to the supply voltages on the upstream and downstream sides of the coupler, respectively. 3 See Figure 2 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latchup or permanent damage. Reinforced Insulation 2 DC Voltage Basic Insulation Reinforced Insulation 1 Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION Rev. A | Page 7 of 16 ADuM4160 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VBUS1 1 16 VBUS2 GND1* 2 VDD1 3 PDEN 4 15 GND2* ADuM4160 14 VDD2 SPU 5 13 SPD TOP VIEW (Not to Scale) 12 PIN UD– 6 11 DD– UD+ 7 10 DD+ GND1* 8 9 GND2* 08171-003 NC = NO CONNECT *PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. Figure 3. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic Direction Description VBUS1 Power Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, connect VBUS1 to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect VBUS1 to VDD1 and to the external 3.3 V power supply. Bypass to GND1 is required. GND1 Return Ground 1. Ground reference for Isolator Side 1. VDD1 Power Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the VDDI pin should be used for a bypass capacitor to GND1. Signal lines that may require pull up, such as PDEN and SPU, should be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS1 to VDD1 and to the external 3.3 V power supply. Bypass to GND1 is required. PDEN Input Pull-Down Enable. This pin is read when exiting reset. For standard operation, connect this pin to VDD1. When connected to GND1 while exiting from reset, the downstream pull-down resistors are disconnected, allowing buffer impedance measurements. SPU Input Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied low. This input must be set high via connection to VDD1 or set low via connection to GND1 and must match Pin 13. UD− I/O Upstream D−. UD+ I/O Upstream D+. GND1 Return Ground 1. Ground reference for Isolator Side 1. GND2 Return Ground 2. Ground reference for Isolator Side 2. DD+ I/O Downstream D+. DD− I/O Downstream D−. PIN Input Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can be tied to VDD2 for operation on power-up, or tied to an external control signal for applications requiring delayed enumeration. SPD Input Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied low. This input must be set high via connection to VDD2 or low via connection to GND2, and must match Pin 5. VDD2 Power Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, the VDD2 pin should be used for a bypass capacitor to GND2. Signal lines that may require pull-up, such as SPD, can be tied to this pin. Where the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2 and to the external 3.3 V power supply. Bypass to GND2 is required. GND2 Return Ground 2. Ground reference for Isolator Side 2. VBUS2 Power Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V, connect VBUS2 to the USB power bus. Where the isolator is powered from a 3.3 V power supply, connect VBUS2 to VDD2 and to the external 3.3 V power supply. Bypass to GND2 is required. Rev. A | Page 8 of 16 ADuM4160 Table 10. Truth Table, Control Signals, and Power (Positive Logic) 1 VSPU Input H VBUS1, VDD1 State Powered VUD+, VUD− State Active VSPD Input H VBUS2, VDD2 State Powered VDD+, VDD− State Active VPIN Input H L Powered Active L Powered Active H L Powered Active H Powered Active H H Powered Active L Powered Active H X Powered Z X Powered Z L X Unpowered X X Powered Z X X Powered Z X Unpowered X X 1 Notes Input and output logic set for full speed logic convention and timing. Input and output logic set for low speed logic convention and timing. Not allowed: VSPU and VSPD must be set to the same value. USB host detects communications error. Not allowed: VSPU and VSPD must be set to the same value. USB host detects communications error. Upstream Side 1 presents a disconnected state to the USB cable. When power is not present on VDD1, the downstream data output drivers revert to high-Z within 32 bit times. The downstream side initializes in high-Z state. When power is not present on the VDD2, the upstream side disconnects the pull-up and disables the upstream drivers within 32 bit times. H represents logic high input or output, L represents logic low input or output, X represents the don’t care logic input or output, and Z represents the high impedance output state. Rev. A | Page 9 of 16 ADuM4160 APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION PRODUCT USAGE USB isolation in the D+/D− lines is challenging for several reasons. First, access to the output enable signals is normally required to control a transceiver. Some level of intelligence must be built into the isolator to interpret the data stream and determine when to enable and disable its upstream and downstream output buffers. Second, the signal must be faithfully reconstructed on the output side of the coupler while retaining precise timing and not passing transient states such as invalid SE0 and SE1 states. In addition, the part must meet the low power requirements of the suspend mode. The ADuM4160 is designed to be integrated into a USB peripheral with an upstream facing USB port as shown in Figure 4. The key design points are: The iCoupler technology is based on edge detection, and, therefore, lends itself well to the USB application. The flow of data through the device is accomplished by monitoring the inputs for activity and setting the direction for data transfer based on a transition from the idle (J) state. When data direction is established, data is transferred until either an endof-packet (EOP) or a sufficiently long idle state is encountered. At this point, the coupler disables its output buffers and monitors its inputs for the next activity 4. The iCoupler does not have a special suspend mode, nor does it need one because its power supply current is below the suspend current limit of 2.5 mA when the USB bus is idle. 2. 3. 5. 6. The USB host provides power for the upstream side of the ADuM4160 through the cable. The peripheral supply provides power to the downstream side of the ADuM4160 The DD+/DD− lines of the isolator interface with the peripheral controller, and the UD+/UD− lines of the isolator connect to the cable or host. Peripheral devices have a fixed data rate that is set at design time. The ADuM4160 has configuration pins, SPU and SPD, that determine the buffer speed and logic convention for each side. These must be set identically and match the desired peripheral speed. USB enumeration begins when either the UD+ or UD− line is pulled high at the peripheral end of the USB cable, which is the upstream side of the ADuM4160. Control of the timing of this event is provided by the PIN input on the downstream side of the coupler. Pull-up and pull-down resistors are implemented inside the coupler. Only external series resistors and bypass capacitors are required for operation. PERIPHERAL VDD2 VBUS1 DD+ USB HOST DD– GND1 3.3V VBUS2 DD+ ADuM4160 DD– PIN MICROCONTROLLER POWER SUPPLY 08171-004 During the data transfers, the input side of the coupler holds its output buffers disabled. The output side enables its output buffers and disables edge detection from the input buffers. This allows the data to flow in one direction without wrapping back through the coupler making the iCoupler latch. Logic is included to eliminate any artifacts due to different input thresholds of the differential and single-ended buffers. The input state is transferred across the isolation barrier as one of three valid states, J, K, or SE0. The signal is reconstructed at the output side with a fixed time delay from the input side differential input. 1. Figure 4. Typical Application The ADuM4160 is designed to interface with an upstream facing low/full speed USB port by isolating the D+/D− lines. An upstream facing port supports only one speed of operation, thus, the speed related parameters, J/K logic levels, and D+/D− slew rate are set to match the speed of the upstream facing peripheral port (see Table 10). Other than the delayed application of pull-up resistors, the ADuM4160 is transparent to USB traffic, and no modifications to the peripheral design are required to provide isolation. The isolator adds propagation delay to the signals comparable to a hub and cable. Isolated peripherals must be treated as if there were a built-in hub when determining the maximum number of hubs in a data chain. A control line on the downstream side of the ADuM4160 activates a pull-up resistor integrated into the upstream side. This allows the downstream port to control when the upstream port attaches to the USB bus. The pin can be tied to the peripheral pull-up, a control line, or the VDD2 pin, depending on when the initial bus connect is to be performed. Hubs can be isolated like any other peripheral. Isolated hubs can be created by placing an ADuM4160 on the upstream port of a hub chip. This configuration can be made compliant if counted as two hub delays. The hub chip allows the ADuM4160 to operate at full speed yet maintains compatibility with low speed devices. Rev. A | Page 10 of 16 ADuM4160 COMPATIBILITY OF UPSTREAM APPLICATIONS PRINTED CIRCUIT BOARD LAYOUT (PCB) The ADuM4160 is designed specifically for isolating a USB peripheral. However, the chip does have two USB interfaces that meet the electrical requirements for driving USB cables. This opens the possibility of implementing isolation in downstream USB ports such as isolated cables, which have generic connections to both upstream and downstream devices, as well as isolating host ports. The ADuM4160 digital isolator requires no external interface circuitry for the logic interfaces. For full speed operation, the D+ and D− line on each side of the device requires a 24 Ω ± 1% series termination resistor. These resistors are not required for low speed applications. Power supply bypassing is required at the input and output supply pins (Figure 5). Install bypass capacitors between VBUSx and VDDx on each side of the chip. The capacitor value should have a value of 0.1 μF and be of a low ESR type. The total lead length between both ends of the capacitor and the power supply pin should not exceed 10 mm. Bypassing between Pin 2 and Pin 8 and between Pin 9 and Pin 15 should also be considered, unless the ground pair on each package side is connected close to the package. VBUS1 = 5.0V INPUT VDD1 = 3.3V OUTPUT The practical result of using the ADuM4160 in a host port is that the port works at a single speed. This behavior is acceptable in embedded host applications; however, this type of interface is not fully compliant as a general-purpose USB port. VBUS1 GND1 VDD1 PDEN SPU UD– UD+ GND1 Isolated cable applications have a similar issue. The cable operates at the preset speed only; therefore, treat cable assemblies as custom applications, not general-purpose isolated cables. POWER SUPPLY OPTIONS In most USB transceivers, 3.3 V is derived from the 5 V USB bus through an LDO regulator. The ADuM4160 includes internal LDO regulators on both the upstream and downstream sides. The output of the LDO is available on the VDD1 and VDD2 pins. In some cases, especially on the peripheral side of the isolation, there may not be a 5 V power supply available. The ADuM4160 has the ability to bypass the regulator and run on a 3.3 V supply directly. Two power pins are present on each side, VBUSx and VDDx. If 5 V is supplied to VBUSx, an internal regulator creates 3.3 V to power the xD+ and xD− drivers. VDDx provides external access to the 3.3 V supply to allow external bypass as well as bias for external pull-ups. If only 3.3 V is available, it can be supplied to both VBUSx and VDDx. This disables the regulator and powers the coupler directly from the 3.3 V supply. Figure 5 shows how to configure a typical application when the upstream side of the coupler receives power directly from the USB bus and the downstream side is receiving 3.3 V from the peripheral power supply. The downstream side can run from a 5V VBUS2 power supply as well. It can be connected in the same manner as VBUS1 as shown in Figure 5, if needed. VBUS2 = 3.3V INPUT VDD2 = 3.3V INPUT ADuM4160 VBUS2 GND2 VDD2 SPD PIN DD– DD+ GND2 08171-005 In a fully compliant application, a downstream facing port must be able to detect whether a peripheral is low speed or full speed based on the application of the upstream pull-up. The buffers and logic conventions must adjust to match the requested speed. Because the ADuM4160 sets its speed by hard wiring pins, the part cannot adjust to different peripherals on the fly. Figure 5. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than about 12 USB bit times, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 36 USB bit times, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 10) by the watchdog timer circuit. The limitation on the magnetic field immunity of the ADuM4160 is set by the condition in which induced voltage in the receiving Rev. A | Page 11 of 16 ADuM4160 V = (−dβ/dt)∑∏rn ; n = 1, 2, … , N 2 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 7. Maximum Allowable Current for Various Current-to-ADuM4160 Spacings Given the geometry of the receiving coil in the ADuM4160 and an imposed requirement that the induced voltage is, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 6. 100 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kguass) 10 0.01 where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). As shown, the ADuM4160 is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, a 0.5 kA current would need to be placed 5 mm away from the ADuM4160 to affect the operation of the component. Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Take care in the layout of such traces to avoid this possibility. 10 1 INSULATION LIFETIME 0.1 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 08171-006 0.01 0.001 1k DISTANCE = 1m 100 08171-007 The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages are tolerated. The voltage induced across the receiving coil is given by 1000 MAXIMUM ALLOWABLE CURRENT (kA) coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM4160 is examined because it represents the most susceptible mode of operation. Figure 6. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM4160 transformers. Figure 7 expresses these allowable current magnitudes as a function of frequency for selected distances. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM4160. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 8 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM4160 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler Rev. A | Page 12 of 16 ADuM4160 In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages and still achieves a 50-year service life. The working voltages listed in Table 8 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage cases. Treat any cross insulation voltage waveform that does not conform to Figure 9 or Figure 10 as a bipolar ac waveform and limit its peak voltage to the 50-year lifetime voltage value listed in Table 8. Note that the voltage presented in Figure 9 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. Rev. A | Page 13 of 16 08171-008 0V Figure 8. Bipolar AC Waveform RATED PEAK VOLTAGE 08171-009 Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. RATED PEAK VOLTAGE 0V Figure 9. Unipolar AC Waveform RATED PEAK VOLTAGE 08171-010 insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 8, Figure 9, and Figure 10 illustrate these different isolation voltage waveforms. 0V Figure 10. DC Waveform ADuM4160 OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) SEATING PLANE 0.51 (0.0201) 0.31 (0.0122) 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 032707-B 1 Figure 11. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimension shown in millimeters and (inches) ORDERING GUIDE Model ADuM4160BRWZ 1 , 2 ADuM4160BRWZ-RL1, 2 Number of Inputs, VDD1 Side Number of Inputs, VDD2 Side Maximum Data Rate (Mbps) Maximum Propagation Delay, 5 V (ns) Maximum Jitter (ns) Temperature Range Package Description Package Option 2 2 2 2 12 12 70 70 3 3 −40°C to +105°C −40°C to +105°C 16-Lead SOIC_W 16-Lead SOIC_W RW-16 RW-16 EVAL-ADUM4160EBZ1 1 2 Evaluation Board Z = RoHS Compliant Part. Specifications represent full speed buffer configuration. Rev. A | Page 14 of 16 ADuM4160 NOTES Rev. A | Page 15 of 16 ADuM4160 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08171-0-9/09(A) Rev. A | Page 16 of 16