Features • • • • • • • • • • • • • • Supply Voltage up to 40V RDSon Typically 0.5Ω at 25°C, Maximum 1.1Ω at 150°C Up to 1.5A Output Current Three High-side and Three Low-side Drivers Usable as Single Outputs or Half Bridges Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors and Inductors PWM Capability for Each Output Controlled by External PWM Signal No Shoot-through Current Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range Outputs Short-circuit Protected Selective Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency SO16 Power Package 1. Description Dual Triple DMOS Output Driver with Serial Input Control ATA6829 The ATA6829 is a fully protected driver interface designed in 0.8-µm BCDMOS technology. It is used to control up to six different loads by a microcontroller in automotive and industrial applications. Each of the three high-side and three low-side drivers is capable to drive currents up to 1.5A. Each driver is freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. The capability to control each output with an external PWM signal opens additional applications. Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in stand-by mode opens a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications. 4531G–BCD–07/09 Figure 1-1. Block Diagram OUT3H OUT2H 4 OUT1H 14 13 Charge pump Fault detect Fault detect Fault detect 12 6 DI 7 CLK O C S S I O L D P H 3 P L 3 P H 2 P L 2 Input register Output register 5 P H 1 H S 3 P L 1 L S 3 H S 2 H S 1 L S 2 S R R L S 1 Control logic Serial interface CS P S F I N H n. u. O V L n. u. n. n. u. u. n. n. u. u. H S 3 L S 3 H S 2 L S 2 H S 1 VS UV protection Power-on reset 11 VCC L T S P 1 10 DO 16 PWM 8 Fault detect Fault detect Thermal protection Fault detect 9 1 15 3 OUT3L 2 OUT2L GND GND GND 2 OUT1L ATA6829 4531G–BCD–07/09 ATA6829 2. Pin Configuration Figure 2-1. Pinning PSO16 GND OUT1L OUT3L OUT3H CS DI CLK PWM Table 2-1. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OUT2L OUT2H OUT1H VS VCC DO GND Pin Description Pin Symbol 1 GND Function 2 OUT1L Low-side driver output 1; power MOS open drain with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability 3 OUT3L Low-side driver output 3; see pin 2 4 OUT3H High-side driver output 3; power MOS open source with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability 5 CS Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled 6 DI Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first 7 CLK Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) 8 PWM PWM input; 5-V CMOS logic level input with internal pull down; receives PWM signal to control outputs which are selected for PWM mode by the serial data interface, high = outputs on, low = outputs off 9 GND Ground; see pin 1 10 DO 11 VCC Ground; reference potential; internal connection to pin 9 and pin 16; connection to heat slug Serial data output; 5-V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data-output line only. Logic supply voltage (5V) 12 VS 13 OUT1H Power supply for high-side output stages OUT1H, OUT2H, OUT3H, internal supply High-side driver output 1; see pin 4 14 OUT2H High-side driver output 2; see pin 4 15 OUT2L Low-side driver output 2; see pin 2 16 GND Ground; see pin 1 3 4531G–BCD–07/09 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. Data Transfer CS DI SRR LS1 HS1 LS2 HS2 LS3 HS3 PL1 PH1 PL2 0 1 2 3 4 5 6 7 8 9 10 11 S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. PH2 PL3 PH3 OLD OCS 12 13 14 n. u. OVL SI 15 CLK DO TP Table 3-1. Bit 4 INH PSF Input Data Protocol Input Register Function 0 SRR Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 PL1 Output LS1 additionally controlled by PWM Input 8 PH1 Output HS1 additionally controlled by PWM Input 9 PL2 See PL1 10 PH2 See PH1 11 PL3 See PL1 12 PH3 See PH1 13 OLD Open load detection (low = on) 14 OCS Overcurrent shutdown (high = overcurrent shutdown is active) 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) ATA6829 4531G–BCD–07/09 ATA6829 Table 3-2. Output Data Protocol Bit Output (Status) Register 0 TP Function Temperature prewarning: high = warning Status LS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR 2 Status HS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 n. u. Not used 8 n. u. Not used 9 n. u. Not used 10 n. u. Not used 11 n. u. Not used 12 n. u. Not used 13 OVL Over-load detected: set high, when at least one output is switched off by a short-circuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch. (open-load detection bit OLD = high) 14 INH Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation 15 PSF Power-supply fail: undervoltage at pin VS detected 1 After power-on reset, the input register has the following status: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SI OCS OLD PH3 PL3 PH2 PL2 PH1 PL1 HS3 LS3 HS2 LS2 HS1 LS1 SRR H H H L L L L L L L L L L L L L The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 (OCS) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR) H H H H H L L L L L L L L L L L H H H L L H H L L L L L L L L L H H H L L L L H H L L L L L L L 5 4531G–BCD–07/09 3.2 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IOUT1-3). If the current through the external load does not reach the open-load detection current, the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. 3.4 Overtemperature Protection If the junction temperature of one ore more output stages exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tj switch off, the affected output is disabled and the corresponding bit in the output register is set to low. Additional the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal prewarning and shutdown threshold avoids oscillations. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off after a delay time (tdSd). The over-load detection bit (OVL) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled. 3.6 Inhibit The SI bit in the input register has to be set to zero to inhibit the ATA6829. All output stages are then turned off but the serial interface stays active. The current consumption is reduced to less than 5 µA at pin VS and less than 100 µA at pin VCC. The output stages can be activated again by bit SI = 1. 6 ATA6829 4531G–BCD–07/09 ATA6829 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Pin Symbol Value Unit Supply voltage 12 VVS –0.3 to +40 V Supply voltage t < 0.5s; IS > –2A 12 VVS –1 V Logic supply voltage 11 VVCC –0.3 to +7 V 5 to 8 VCS, VDI, VCLK, VPWM –0.3 to VVCC + 0.3 V 10 VDO –0.3 to VVCC + 0.3 V 5 to 8 ICS, IDI, ICLK, IPWM –10 to +10 mA Output current 10 IDO –10 to +10 mA Output current 2 to 4 13 to 15 IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L Internally limited, see output specification Output voltage 2 to 4 13 to 15 IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L –0.3 to +40 V 2 to 4 13 to 15 towards pin 12 IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L 17 A Junction temperature range TJ –40 to +150 °C Storage temperature range TSTG –55 to +150 °C Logic input voltage Logic output voltage Input current Reverse conducting current (tpulse = 150 µs) 5. Thermal Resistance Parameters Test Conditions Junction pin Measured to heat slug GND pins 1, 9 and 16 Junction ambient Symbol Value Unit RthJP 5 K/W RthJA 30 K/W 6. Operating Range Parameters Supply voltage Logic supply voltage Symbol VVS Value VUV(1) to Unit 40 V VVCC 4.75 to 5.25 V VCS,VDI, VCLK, VPWM –0.3 to VVCC V Serial interface clock frequency fCLK 2 MHz PWM input frequency fPWM 1 kHz Tj –40 to +150 °C Logic input voltage Junction temperature range Note: 1. Threshold for undervoltage detection. 7 4531G–BCD–07/09 7. Noise and Surge Immunity Parameters Test Conditions Conducted interferences ISO 7637-1 Interference suppression VDE 0879 Part 2 ESD (Human Body Model) ESD S 5.1 ESD (Machine Model) JEDEC A115A Note: Value Level 4(1) Level 5 2 kV 200 V 1. Test pulse 5: Vsmax = 40V. 8. Electrical Characteristics 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. 1 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Current Consumption 1.1 Quiescent current VS VVS < 20V, SI = low 12 IVS 1 5 µA A 1.2 Quiescent current VCC 4.75V < VVCC < 5.25V, SI = low 11 IVCC 60 100 µA A 1.3 Supply current VS VVS < 20V normal operating, all outputs off, input register bit 13 (OLD) = high 12 IVS 4 6 mA A 1.4 Supply current VCC 4.75V < VVCC < 5.25V, normal operating 11 IVCC 350 650 µA A 1.5 Discharge current VS VVS = 32.5V, INH = low 12 IVS 0.5 5.5 mA A 1.6 Discharge current VS VVS = 40V, INH = low 12 IVS 2.5 10 mA A 11 VVCC 3.2 3.9 4.4 V A tdPor 30 95 190 µs A 5.6 7.0 V A V A 40 µs A 2 Undervoltage Detection, Power-on Reset 2.1 Power-on reset threshold 2.2 Power-on reset delay time 2.3 Undervoltage-detection VCC = 5V threshold 12 VUv 2.4 Undervoltage-detection VCC = 5V hysteresis 12 ΔVUv 2.5 Undervoltage-detection delay time 3 After switching on VCC 0.6 tdUV 10 TjPW set 120 145 170 °C B 105 130 155 °C B K B °C B Thermal Prewarning and Shutdown 3.1 Thermal prewarning set 3.2 Thermal prewarning reset TjPW reset 3.3 Thermal prewarning hysteresis ΔTjPW 3.4 Thermal shutdown off Tj switch off 15 150 175 200 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 8 ATA6829 4531G–BCD–07/09 ATA6829 8. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. Parameters 3.5 Thermal shutdown on 3.6 Thermal shutdown hysteresis ΔTj switch off 3.7 Ratio thermal shutdown off/thermal prewarning set Tj switch off/ TjPW set 1.05 1.2 B 3.8 Ratio thermal shutdown on/thermal prewarning reset Tj switch on/ TjPW reset 1.05 1.2 B 4 4.1 Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Tj switch on 135 160 185 °C B K B 15 Output Specification (OUT1-OUT3) On resistance 4.2 IOut 1-3 H = –1.3A IOut 1-3 L = 1.3A 4, 13, 14 RDSOn1-3H 1.1 Ω A 2, 3, 15 RDSOn1-3L 1.1 Ω A µA A 4.3 High-side output leakage current VOut 1-3 H = 0V, output stages off 4, 13, 14 IOut1-3H 4.4 Low-side output leakage current VOut 1-3 L = VVS, output stages off 2, 3, 15 IOut1-3L 5 µA A 4.5 High-side switch reverse diode forward voltage IOut = 1.5A 4, 13, 14 VOut1-3 – VVS 1.5 V A 4.6 Low-side switch reverse IOut 1-3 L = –1.5A diode forward voltage 2, 3, 15 VOut1-3L –1.5 V A 4.7 High-side overcurrent limitation and shutdown threshold 4, 13, 14 IOut1-3H –2.5 –2 –1.5 A A 4.8 Low-side overcurrent limitation and shutdown threshold 2, 3, 15 IOut1-3L 1.5 2 2.5 A A 4.9 Overcurrent shutdown delay time tdSd 10 40 µs A 4.10 High-side open load detection current Input register bit 13 (OLD) = low, output off 4, 13, 14 IOut1-3H –2.5 –0.2 mA A 4.11 Low-side open load detection current Input register bit 13 (OLD) = low, output off 2, 3, 15 IOut1-3L 0.2 2.5 mA A 4.12 High-side output switch VVS = 13V on delay(1),(2) RLoad = 30Ω tdon 20 µs A 4.13 Low-side output switch VVS = 13V on delay(1),(2) RLoad = 30Ω tdon 20 µs A 4.14 High-side output switch VVS =13V off delay(1),(2) RLoad = 30Ω tdoff 20 µs A –5 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 9 4531G–BCD–07/09 8. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. Parameters 4.15 Low-side output switch VVS =13V off delay(1),(2) RLoad = 30Ω 4.16 Dead time between corresponding highand low-side switches VVS =13V RLoad = 30Ω tdon – tdoff 4.17 ΔtdPWM low-side switch(3) VVS = 13V RLoad = 30Ω ΔtdPWM = tdon – tdoff 4.18 ΔtdPWM high-side switch(3) VVS = 13V RLoad = 30Ω ΔtdPWM = tdon – tdoff 3 0.3 × VVCC 5 Test Conditions Pin Symbol Min. tdoff Typ. Max. Unit Type* 3 µs A µs A 20 µs A 7 µs A V A 0.7 × VVCC V A 1 Logic Inputs DI, CLK, CS, PWM 5.1 Input voltage low-level threshold 5-8 VIL 5.2 Input voltage high-level threshold 5-8 VIH 5.3 Hysteresis of input voltage 5-8 ΔVI 50 700 mV A 5.4 Pull-down current Pins DI, CLK, PWM VDI, VCLK, VPWM = VCC 6, 7, 8 IPD 10 65 µA A 5.5 Pull-up current Pin CS VCS = 0V 5 IPU –65 –10 µA A 0.4 V A V A 10 µA A 100 µs A 6 Serial Interface – Logic Output DO 6.1 Output-voltage low level IDOL = 2 mA 10 VDOL 6.2 Output-voltage high level IDOL = –2 mA 10 VDOH VVCC – 0.7 V 6.3 Leakage current (tri-state) VCS = VCC 0V < VDO < VVCC 10 IDO –10 7 7.1 Inhibit Input – Timing Delay time from standby to normal operation tdINH *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 10 ATA6829 4531G–BCD–07/09 ATA6829 9. Serial Interface – Timing Pin Timing Chart No.(1) Symbol DO enable after CS CDO = 100 pF falling edge 10 1 8.2 DO disable after CS CDO = 100 pF rising edge 10 8.3 DO fall time CDO = 100 pF 10 8.4 DO rise time CDO = 100 pF 10 8.5 DO valid time CDO = 100 pF 10 8.6 CS setup time 5 4 tCSSethl 8.7 CS setup time 5 8 8.8 CS high time 5 8.9 CLK high time 7 8.10 CLK low time No. Parameters 8.1 Test Conditions Min. Typ. Max. Unit Type* tENDO 200 ns D 2 tDISDO 200 ns D - tDOf 100 ns D - tDOr 100 ns D 10 tDOVal 200 ns D 225 ns D tCSSetlh 225 ns D 9 tCSh 500 ns D 5 tCLKh 225 ns D 7 6 tCLKl 225 ns D 8.11 CLK period time 7 - tCLKp 500 ns D 8.12 CLK setup time 7 7 tCLKSethl 225 ns D 8.13 CLK setup time 7 3 tCLKSetlh 225 ns D 8.14 DI setup time 6 11 tDIset 40 ns D 8.15 DI hold time 6 12 tDIHold 40 ns D *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. See Figure 9-1 on page 12 11 4531G–BCD–07/09 Figure 9-1. Serial Interface Timing with Chart Number 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 x VCC, low level = 0.3 x VCC Output DO: High level = 0.8 x VCC, low level = 0.2 x VCC 12 ATA6829 4531G–BCD–07/09 ATA6829 10. Application Circuit VCC U5021M M M OUT3H Trigger Reset Watchdog OUT2H 4 OUT1H 14 13 Charge VS pump Fault detect Fault detect Fault detect 12 6 DI VBatt VS 0 to 40 V + Microcontroller 7 CLK S I O C S O L D P H 3 P L 3 P H 2 P L 2 P H 1 H S 3 P L 1 L S 3 H S 2 L S 2 H S 1 L S 1 S R R Control Input register Serial interface Output register 5 logic Power-on reset CS I N H n. u. O V L n. u. n. n. u. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 VCC 11 VCC 5V L T S P 1 + P S F UV protection 10 DO 16 PWM 8 Fault detect Fault detect Thermal protection Fault detect 9 1 15 3 OUT3L OUT2L GND GND GND 2 OUT1L VCC 10.1 Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOut1,2,3 (see “Absolute Maximum Ratings” on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to the GND pins. Negative spikes at the output pins (e.g. negative spikes caused by an inductive load switched off with a high side driver) may activate the overtemperature protection function of the ATA6829. In this condition, the affected output will be switched off. If this behavior is not acceptable or compatible with the specific application functionally, it is necessary, that for switching on required outputs again, the SRR bit (Status Register Reset) is set, to ensure a reset of the overtemperature function. 13 4531G–BCD–07/09 11. Ordering Information Extended Type Number Package ATA6829-T3QY PSO16 Remarks Power package with heat slug, taped and reeled, lead-free 12. Package Information 1 heat slug exposed 8 ∅ 0.4 A B 9 16 2.54-0.5 Package: PSO16 with heat slug Dimensions in mm 6.86 technical drawings according to DIN specifications A 0.41 1.27 nom. 1.52 max. 0.1 max. 0.23 1.62 max. 9.9±0.1 3.99 max. B 4.27±0.4 6±0.2 7 x 1.27 = 8.89 nom. Drawing-No.: 6.541-5050.01-4 Issue: 2; 18.08.05 14 ATA6829 4531G–BCD–07/09 ATA6829 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 4531G-BCD-07/09 • Complete datasheet: T6819 deleted 4531F-BCD-09/05 • Complete datasheet: T6829 changed in ATA6829 • Ordering Information on page 14 changed • Package drawing on page 15 changed 15 4531G–BCD–07/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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