19-5920; Rev 6/11 DS1323 3.3V Flexible Nonvolatile Controller with Lithium Battery Monitor FEATURES PIN ASSIGNMENT Converts CMOS SRAM into nonvolatile memory Unconditionally write-protects SRAM when VCC is out of tolerance Automatically switches to battery backup when VCC power failure occurs Flexible memory organization - Mode 0: 4 banks with 1 SRAM each - Mode 1: 2 banks with 2 SRAMs each - Mode 2: 1 bank with 4 SRAMs each Monitors voltage of a lithium cell and provides advanced warning of impending battery failure Signals low-battery condition on active low battery warning output signal Resets processor when power failure occurs and holds processor in reset during system power-up 10% power-fail detection Industrial temperature range of -40°C to +85°C VCCO 1 20 VCCI VBAT 2 19 RST NC 3 4 18 17 BW CEI1 CEI2 5 16 CEO2 NC 6 NC A/CEI3 7 15 14 B/CEI4 8 13 CEO4 NC 9 12 NC 10 11 MODE GND CEO1 CEO3 DS1323E 20-Pin TSSOP (173 mils) PIN DESCRIPTION VCCI VCCO VBAT A, B - +3.3V Power Supply Input - SRAM Power Supply Output - Backup Battery Input - Address Inputs CEI1 - CEI4 - Chip Enable Inputs CEO1 - CEO4 - Chip Enable Outputs - Battery Warning Output (Open BW Drain) - Reset Output (Open Drain) RST MODE - Mode Input GND - Ground NC - No Connection 1 of 14 DS1323 DESCRIPTION The DS1323 Flexible Nonvolatile Controller with Lithium Battery Monitor is a CMOS circuit that solves the application problem of converting CMOS SRAMs into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip-enable outputs are inhibited to accomplish write protection and the battery is switched on to supply the SRAMs with uninterrupted power. Special circuitry uses a low-leakage CMOS process which affords precise voltage detection at extremely low battery consumption. One DS1323 can support as many as four SRAMs arranged in any of three memory configurations. In addition to battery-backup support, the DS1323 performs the important function of monitoring the remaining capacity of the lithium battery and providing a warning before the battery reaches end-of-life. Because the open-circuit voltage of a lithium backup battery remains relatively constant over the majority of its life, accurate battery monitoring requires loaded-battery voltage measurement. The DS1323 performs such measurement by periodically comparing the voltage of the battery as it supports an internal resistive load with a carefully selected reference voltage. If the battery voltage falls below the reference voltage under such conditions, the battery will soon reach end-of-life. As a result, the battery warning pin is activated to signal the need for battery replacement. MEMORY BACKUP The DS1323 performs all the circuit functions required to provide battery-backup for as many as four SRAMs. First, the device provides a switch to direct power from the battery or the system power supply (VCCI). Whenever VCCI is less than the VCCTP trip point and VCCI is less than the battery voltage VBAT, the battery is switched on to provide backup power to the SRAM. This switch has voltage drop of less than 0.2 volts. Second, the DS1323 handles power failure detection and SRAM write-protection. VCCI is constantly monitored, and when the supply goes out of tolerance, a precision comparator detects power failure and inhibits the four chip enable outputs in order to write-protect the SRAMs. This is accomplished by holding CEO1 through CEO4 to within 0.2 volts of VCCO when VCCI is out of tolerance. If any CEI is active (low) at the time that power failure is detected, the corresponding CEO signal is kept low until the CEI signal is brought high again. Once the CEI signal is brought high, the CEO signal is taken high and held high until after VCCI has returned to its nominal voltage level. If the CEI signal is not brought high by 1.5µs after power failure is detected, the corresponding CEO is forced high at that time. This specific scheme for delaying write protection for up to 1.5µs guarantees that any memory access in progress when power failure occurs will complete properly. Power failure detection occurs in the range of 2.8 to 3.0 volts. 2 of 14 DS1323 MEMORY CONFIGURATIONS The DS1323 can be configured via the MODE pin for three different arrangements of the four attached SRAMs. The state of the MODE pin is latched at VCCI = VCCTP on power-up. See Figure 1 for details. MEMORY CONFIGURATIONS Figure 1 MODE = GND (4 BANKS WITH 1 SRAM EACH): DS1323 MODE = VCCO (2 BANKS WITH 2 SRAM EACH): DS1323 MODE = Not Connected (1 BANK WITH 4 SRAMs): DS1323 3 of 14 DS1323 BATTERY VOLTAGE MONITORING The DS1323 automatically performs periodic battery voltage monitoring at a factory-programmed time interval of 24 hours. Such monitoring begins within tREC after VCCI rises above VCCTP and is suspended when power failure occurs. After each 24-hour period (tBTCN) has elapsed, the DS1323 connects VBAT to an internal 1MΩ test resistor (RINT) for one second (tBTPW). During this one second, if VBAT falls below the factory-programmed battery voltage trip point (VBTP), the battery warning output BW is asserted. While BW is active, battery testing will be performed with period tBTCW to detect battery removal and replacement. Once asserted, BW remains active until the battery is physically removed and replaced by a fresh cell. The battery is still retested after each VCC power-up, however, even if BW was active on power-down. If the battery is found to be higher than VBTP during such testing, BW is deasserted and regular 24-hour testing resumes. BW has an open-drain output driver. Battery replacement following BW activation is normally done with VCCI nominal so that SRAM data is not lost. During battery replacement, the minimum time duration between old battery detachment and new battery attachment (tBDBA) must be met or BW will not deactivate following attachment of the new battery. Should BW not deactivate for this reason, the new battery can be detached for tBDBA and then re-attached to clear BW . NOTE: The DS1323 cannot constantly monitor an attached battery because such monitoring would drastically reduce the life of the battery. As a result, the DS1323 only tests the battery for one second out of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that has not been previously flagged with BW ) is removed between battery tests, the DS1323 may not immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery is then reattached to the DS1323, the battery may not be tested until the next scheduled test. NOTE: Battery monitoring is only a useful technique when testing can be done regularly over the entire life of a lithium battery. Because the DS1323 only performs battery monitoring when VCC is nominal, systems which are powered down for excessively long periods can completely drain their lithium cells without receiving any advanced warning. To prevent such an occurrence, systems using the DS1323 battery monitoring feature should be powered up periodically (at least once every few months) in order to perform battery testing. Furthermore, anytime BW is activated on the first battery test after a power-up, data integrity should be checked via checksum or other technique. POWER MONITORING The DS1323 automatically detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When VCCI falls below the trip point level in the range of 3.0 to 2.8 volts (10% tolerance) (VCCTP), the VCCI comparator activates the reset signal RST . RST also serves as a power-on reset during power-up. After VCCI exceeds VCCTP, RST will be held active for 200ms nominal (tRPU). This reset period is sufficiently long to prevent system operation during power-on transients and to allow tREC to expire. RST has an open-drain output driver. FRESHNESS SEAL MODE When the battery is first attached to the DS1323 without VCC power applied, the device does not immediately provide battery-backup power on VCCO. Only after VCCI exceeds VCCTP will the DS1323 leave Freshness Seal Mode. This mode allows a battery to be attached during manufacturing but not used until 4 of 14 DS1323 after the system has been activated for the first time. As a result, no battery energy is drained during storage and shipping. FUNCTIONAL BLOCK DIAGRAM Figure 2 5 of 14 DS1323 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Storage Temperature Lead Temperature (soldering, 10s) Soldering Temperature (reflow) -0.3V to +7.0V -40°C to +85°C -55°C to +125°C +260°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C) PARAMETER Supply Voltage Battery Supply Voltage SYMBOL VCCI VBAT VIH VIL Logic 1 Input Logic 0 Input MIN 3.0 2.0 2.0 -0.3 TYP 3.3 MAX 3.6 6.0 VCCI+0.3 0.6 UNITS V V V V NOTES 1 MAX UNITS 200 µA 100 µA V 80 mA NOTES 3 3, 4 2 2 DC ELECTRICAL CHARACTERISTICS (VCCI ≥ VCCTP, TA = -40°C to +85°C.) PARAMETER Supply Current Supply Current RAM Supply Voltage RAM Supply Current SYMBOL ICC1 ICC2 VCCO ICCO1 RAM Supply Current ICCO2 VCC Trip Point VBAT Trip Point Output Current Output Current Input Leakage Output Leakage Battery Monitoring Test Load VCCTP VBTP IOH IOL IIL ILO RINT CONDITION TTL inputs CMOS inputs MIN TYP 50 30 VCCI -0.2 VCCO ≥ VCCI 0.2V VCCO ≥ VCCI 0.3V 2.8 2.5 -1 2.2V 0.4V -1.0 -1.0 0.8 2.9 2.6 1.2 140 mA 3.0 2.7 V V mA mA µA µA MΩ 4 +1.0 +1.0 1.5 5, 6 5, 6 DC ELECTRICAL CHARACTERISTICS (VCCI < VBAT; VCCI < VCCTP, TA = -40°C to +85°C. PARAMETER SYMBOL CONDITION Battery Current IBAT Battery Backup Current ICCO3 VCCO ≥ VBAT -0.2V Supply Voltage VCCO CEO Output VOHL 6 of 14 MIN TYP VBAT -0.2 VBAT -0.2 MAX 100 500 UNITS nA µA V NOTES 3 V 7 DS1323 CAPACITANCE (TA = +25°C) PARAMETER Input Capacitance ( CEI , MODE) Output Capacitance ( CEO , BW , RST ) SYMBOL CIN MIN TYP COUT MAX 7 UNITS pF NOTES 7 pF MAX 25 1.5 125 UNITS ns µs ms ms ms s UNITS µs µs µs NOTES UNITS s hr s s s s NOTES 6 AC ELECTRICAL CHARACTERISTICS (VCCI ≥ VCCTP, TA = -40°C to +85°C.) PARAMETER CEI to CEO Propagation Delay CE Pulse Width VCC Valid to End of Write Protection VCC Valid to CEI Inactive VCC Valid to RST Inactive VCC Valid to BW Valid SYMBOL tPD tCE tREC MIN tPU tRPU tBPU TYP 15 150 200 2 350 1 MIN 150 TYP MAX NOTES 8 9 6 6 AC ELECTRICAL CHARACTERISTICS (VCCI < VCCTP, TA = -40°C to +85°C.) PARAMETER VCC Slew Rate VCC Fail Detect to RST Active VCC Slew Rate SYMBOL tF tRPD tR 15 15 6 AC ELECTRICAL CHARACTERISTICS (VCCI ≥ VCCTP, TA = -40°C to +85°C.) PARAMETER Battery Test to BW Active Battery Test Cycle-Normal Battery Test Cycle-Warning Battery Test Pulse Width Battery Detach to Battery Attach Battery Attach to BW Inactive SYMBOL tBW tBTCN tBTCW tBTPW tBDBA tBABW MIN TYP MAX 1 24 5 1 7 1 7 of 14 6 DS1323 TIMING DIAGRAM: POWER-UP NOTE: If VBAT > VCCTP, VCCO will begin to slew with VCCI when VCCI = VCCTP. 8 of 14 DS1323 TIMING DIAGRAM: POWER-DOWN NOTES: If VBAT > VCCTP, VCCO will slew down with VCCI until VCCI = VCCTP. 9 of 14 DS1323 TIMING DIAGRAM: BATTERY WARNING DETECTION NOTE: tBW is measured from the expiration of the internal timer to the activation of the battery warning output BW . TIMING DIAGRAM: BATTERY REPLACEMENT 10 of 14 DS1323 NOTES: 1. 2. 3. 4. 5. 6. All voltages referenced to ground. In battery backup mode, inputs must never be below ground or above VCCO. Measured with outputs open. All inputs within 0.3V of ground or VCCI. Measured with a load as shown in Figure 3. BW and RST are open drain outputs and, as such, cannot source current. External pull-up resistors should be connected to these pins for proper operation. Both BW and RST can sink 10mA. 7. Chip Enable Outputs CEO1 – CEO4 can only sustain leakage current in the battery backup mode. 8. tCE maximum must be met to ensure data integrity on power down. 9. CEO1 through CEO4 will be held high for a time equal to tREC after VCCI crosses VCCTP on power-up. 10. The DS1323 is recognized by Underwriters Laboratories (UL) under file E99151. DC TEST CONDITIONS AC TEST CONDITIONS Outputs Open All voltages are referenced to ground Output Load: See below Input Pulse Levels: 0 – 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns OUTPUT LOAD Figure 3 *INCLUDING SCOPE AND JIG CAPACITANCE 11 of 14 DS1323 TYPICAL OPERATING CHARACTERISTICS (VCC = +3.3V, TA = +25°C, unless otherwise specified.) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (µA) 55 50 45 40 35 30 -40 -20 0 20 40 60 80 TEMPERATURE (C) VCC TRIP vs. TEMPERATURE 3 2.95 2.9 VCC TRIP(V) 2.85 2.8 2.75 2.7 2.65 2.6 2.55 2.5 -40 -20 0 20 40 TEMPERATURE (C) 12 of 14 60 80 DS1323 TYPICAL OPERATING CHARACTERISTICS (continued) (VCC = +3.3V, TA = +25°C, unless otherwise specified.) /CE PROPAGATION DELAY vs. TEMPERATURE 17 16 DELAY TIME (nS) 15 14 13 12 11 10 /CEO Propagation Delay, Rising Edge /CEO Propagation Delay, Falling Edge 9 8 -40 -20 0 20 40 60 80 TEMPERATURE (C) ORDERING INFORMATION PART DS1323+ DS1323+T&R OPERATING VOLTAGE (V) 3.3 3.3 TEMP RANGE -40ºC to +85ºC -40ºC to +85ºC PACKAGE TYPE 20 TSSOP 20 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-“ in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 20 TSSOP U20+1 21-0066 90-0116 13 of 14 DS1323 REVISION HISTORY REVISION DATE 6/11 DESCRIPTION Deleted references to 16-pin DIP and 16-pin SO packages; updated the Absolute Maximum Ratings section; updated the Recommended Operating Conditions, DC Electrical Characteristics, Capacitance, AC Electrical Characteristics tables; updated Notes; updated the Ordering Information table; added the Package Information table PAGES CHANGED 1, 3, 6, 7, 13 14 of 14 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.