BF1210 Dual N-channel dual gate MOSFET Rev. 01 — 25 October 2006 Product data sheet 1. Product profile 1.1 General description The BF1210 is a combination of two dual gate MOSFET amplifiers with shared source and gate2 leads. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package. CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling. 1.2 Features n Two low noise gain controlled amplifiers in a single package; both with a partly integrated bias n Superior cross modulation performance during AGC n High forward transfer admittance n High forward transfer admittance to input capacitance ratio 1.3 Applications n Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply voltage u digital and analog television tuners u professional communication equipment BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 1.4 Quick reference data Table 1. Quick reference data Per MOSFET unless otherwise specified. Symbol Parameter Conditions VDS drain-source voltage ID drain current DC Ptot total power dissipation Tsp ≤ 107 °C |yfs| forward transfer admittance amplifier A; ID = 19 mA [1] amplifier B; ID = 13 mA Ciss(G1) input capacitance at gate1 amplifier A amplifier B reverse transfer capacitance f = 100 MHz NF noise figure Xmod cross modulation [2] Max Unit - - 6 V - - 30 mA - - 180 mW 26 31 41 mS 28 33 43 mS - 2.2 2.7 pF - 1.9 2.4 pF - 20 - fF amplifier A; f = 400 MHz - 0.9 1.5 dB amplifier B; f = 800 MHz - 1.2 1.9 dB amplifier A 100 105 - dBµV amplifier B 100 103 - dBµV - - 150 °C input level for k = 1 % at 40 dB AGC junction temperature Tj Typ [2] f = 100 MHz Crss Min [1] Tsp is the temperature at the soldering point of the source lead. [2] Calculated from S-parameters. 2. Pinning information Table 2. Discrete pinning Pin Description 1 gate1 (AMP A) 2 gate2 Simplified outline 6 3 gate1 (AMP B) 4 drain (AMP B) 5 source 6 drain (AMP A) 5 Symbol 4 AMP A DA G1A S G2 1 2 3 DB G1B AMP B sym119 3. Ordering information Table 3. Ordering information Type number BF1210 Package Name Description Version - plastic surface-mounted package; 6 leads SOT363 BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 2 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 4. Marking Table 4. Marking Type number Marking Description BF1210 *AB * = p : made in Hong Kong * = t : made in Malaysia * = w : made in China 5. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit - 6 V DC - 30 mA - ±10 mA - ±10 mA Per MOSFET VDS drain-source voltage ID drain current IG1 gate1 current IG2 gate2 current Tsp ≤ 107 °C [1] Ptot total power dissipation - 180 mW Tstg storage temperature −65 +150 °C Tj junction temperature - 150 °C [1] Tsp is the temperature at the soldering point of the source lead. 001aac193 250 Ptot (mW) 200 150 100 50 0 0 50 100 150 200 Tsp (˚C) Fig 1. Power derating curve BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 3 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 6. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Typ Unit 240 K/W 7. Static characteristics Table 7. Static characteristics Tj = 25 °C. Symbol Parameter Conditions Min Typ Max Unit amplifier A 6 - - V amplifier B 6 - - V Per MOSFET; unless otherwise specified drain-source breakdown voltage V(BR)DSS VG1-S = VG2-S = 0 V; ID = 10 µA V(BR)G1-SS gate1-source breakdown voltage VG2-S = VDS = 0 V; IG1-S = 10 mA 6 - 10 V V(BR)G2-SS gate2-source breakdown voltage VG1-S = VDS = 0 V; IG2-S = 10 mA 6 - 10 V VF(S-G1) forward source-gate1 voltage VG2-S = VDS = 0 V; IS-G1 = 10 mA 0.5 - 1.5 V VF(S-G2) forward source-gate2 voltage VG1-S = VDS = 0 V; IS-G2 = 10 mA 0.5 - 1.5 V VG1-S(th) gate1-source threshold voltage VDS = 5 V; VG2-S = 4 V; ID = 100 µA 0.3 - 1.0 V VG2-S(th) gate2-source threshold voltage VDS = 5 V; VG1-S = 5 V; ID = 100 µA 0.4 - 1.0 V amplifier A; VDS(A) = 5 V; RG1(A) = 59 kΩ 14 - 24 mA amplifier B; VDS(B) = 5 V; RG1(B) = 150 kΩ 9 - 17 mA amplifier A; VG1-S(A) = 5 V - - 50 nA amplifier B; VG1-S(B) = 5 V - - 50 nA - - 20 nA Min Typ Max Unit drain-source current IDS IG1-S IG2-S [1] [1] VG2-S = 4 V gate1 cut-off current VG2-S = 0 V; VDS(A) = VDS(B) = 0 V gate2 cut-off current VG2-S = 4 V; VDS(A) = VDS(B) = 0 V; VG1-S(A) = VG1-S(B) = 0 V RG1 connects gate1 to VGG = 5 V. See Figure 32. 8. Dynamic characteristics 8.1 Dynamic characteristics for amplifier A Table 8. Dynamic characteristics for amplifier A Common source; Tamb = 25 °C; VG2-S = 4 V; VDS(A) = 5 V; ID(A) = 19 mA. Symbol Parameter Conditions |yfs| forward transfer admittance Tj = 25 °C 26 31 41 mS Ciss(G1) input capacitance at gate1 f = 100 MHz [1] - 2.2 2.7 pF f = 100 MHz [1] - 3.0 - pF f = 100 MHz [1] - 0.9 - pF reverse transfer capacitance f = 100 MHz [1] - 20 - fF Ciss(G2) Coss Crss input capacitance at gate2 output capacitance BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 4 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET Table 8. Dynamic characteristics for amplifier A …continued Common source; Tamb = 25 °C; VG2-S = 4 V; VDS(A) = 5 V; ID(A) = 19 mA. Symbol Parameter Gtr transducer power gain Conditions BS = BS(opt); BL = BL(opt) f = 200 MHz; GS = 2 mS; GL = 0.5 mS NF noise figure cross modulation [1] Calculated from S-parameters. [2] Measured in Figure 32 test circuit. Max Unit 31 35 39 dB 27 31 35 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 22 26 30 dB f = 11 MHz; GS = 20 mS; BS = 0 S - 3 - dB f = 400 MHz; YS = YS(opt) - 0.9 1.5 dB - 1.2 1.9 dB at 0 dB AGC 90 - - dBµV at 10 dB AGC - 90 - dBµV at 20 dB AGC - 99 - dBµV at 40 dB AGC 100 105 - dBµV input level for k = 1 %; fw = 50 MHz; funw = 60 MHz BF1210_1 Product data sheet Typ f = 400 MHz; GS = 2 mS; GL = 1 mS f = 800 MHz; YS = YS(opt) Xmod Min [1] [2] © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 5 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 8.1.1 Graphs for amplifier A 001aaf476 40 001aaf477 30 (1) ID (mA) ID (mA) (1) (2) (3) 30 (2) (3) 20 (4) (4) (5) 20 (6) (5) (7) 10 10 (8) (6) (9) (7) 0 0 0 0.5 1.0 1.5 2.0 0 2 VG1-S (V) 6 VDS (V) (1) VG2-S = 4.0 V. (1) VG1-S(A) = 1.8 V. (2) VG2-S = 3.5 V. (2) VG1-S(A) = 1.7 V. (3) VG2-S = 3.0 V. (3) VG1-S(A) = 1.6 V. (4) VG2-S = 2.5 V. (4) VG1-S(A) = 1.5 V. (5) VG2-S = 2.0 V. (5) VG1-S(A) = 1.4 V. (6) VG2-S = 1.5 V. (6) VG1-S(A) = 1.3 V. (7) VG2-S = 1.0 V. (7) VG1-S(A) = 1.2 V. VDS(A) = 5 V; Tj = 25 °C. 4 (8) VG1-S(A) = 1.1 V. (9) VG1-S(A) = 1.0 V. VG2-S = 4 V; Tj = 25 °C. Fig 2. Amplifier A: transfer characteristics; typical values Fig 3. Amplifier A: output characteristics; typical values BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 6 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf478 100 001aaf479 36 (1) IG1 (µA) (1) Yfs (mS) (2) 80 (2) 24 (3) 60 (3) (4) 40 12 (4) (5) 20 (5) (6) (6) (7) (7) 0 0 0 0.5 1.0 1.5 2.0 0 12 24 VG1-S (V) 36 ID (mA) (1) VG2-S = 4.0 V. (1) VG2-S = 4.0 V. (2) VG2-S = 3.5 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3.0 V. (3) VG2-S = 3.0 V. (4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2.0 V. (5) VG2-S = 2.0 V. (6) VG2-S = 1.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1.0 V. (7) VG2-S = 1.0 V. VDS(A) = 5 V; Tj = 25 °C. VDS(A) = 5 V; Tj = 25 °C. Fig 4. Amplifier A: gate1 current as a function of gate1 voltage; typical values 001aaf480 20 ID (mA) Fig 5. Amplifier A: forward transfer admittance as a function of drain current; typical values 001aaf481 20 ID (mA) 16 15 12 10 8 5 4 0 0 0 20 40 60 0 IG1 (µA) 2 3 4 5 VGG (V) VDS(A) = 5 V; VG2-S = 4 V; Tj = 25 °C. VDS(A) = 5 V; VG2-S = 4 V; RG1(A) = 59 kΩ; Tj = 25 °C. Fig 6. Amplifier A: drain current as a function of gate1 current; typical values Fig 7. Amplifier A: drain current as a function of gate1 supply voltage (VGG); typical values BF1210_1 Product data sheet 1 © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 7 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf482 25 001aaf483 30 (1) ID (mA) 20 (2) ID (mA) (1) 20 (2) 15 (3) (4) (5) 10 (3) 10 (4) (5) 5 (6) (7) 0 0 0 1 2 3 4 5 VGG = VDS (V) 0 1 (1) RG1(A) = 47 kΩ. (1) VGG = 5.0 V. (2) RG1(A) = 59 kΩ. (2) VGG = 4.5 V. (3) RG1(A) = 68 kΩ. (3) VGG = 4.0 V. (4) RG1(A) = 82 kΩ. (4) VGG = 3.5 V. (5) RG1(A) = 100 kΩ. (5) VGG = 3.0 V. 2 3 4 5 VG2-S (V) Tj = 25 °C; RG1(A) = 59 kΩ (connected to VGG). (6) RG1(A) = 120 kΩ. (7) RG1(A) = 150 kΩ. VG2-S = 4 V; Tj = 25 °C. Fig 8. Amplifier A: drain current as a function of VDS and VGG; typical values Fig 9. Amplifier A: drain current as a function of gate2 voltage; typical values BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 8 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf484 0 gain reduction (dB) 10 001aaf485 110 Vunw (dBµV) 100 20 30 90 40 80 50 0 1 2 3 4 0 10 20 VAGC (V) VDS(A) = 5 V; VGG = 5 V; ID(nom)(A) = 19 mA; RG1(A) = 59 kΩ; f = 50 MHz; Tamb = 25 °C; see Figure 32. 30 40 50 gain reduction (dB) VDS(A) = 5 V; VGG = 5 V; VG2-S(nom) = 4 V; RG1(A) = 59 kΩ; fw = 50 MHz; funw = 60 MHz; ID(nom)(A) = 19 mA; Tamb = 25 °C; see Figure 32. Fig 10. Amplifier A: typical gain reduction as a function of the AGC voltage; typical values Fig 11. Amplifier A: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 001aaf486 30 ID (mA) 20 10 0 0 10 20 30 40 50 gain reduction (dB) VDS(A) = 5 V; VGG = 5 V; VG2-S(nom) = 4 V; RG1(A) = 59 kΩ; f = 50 MHz; ID(nom)(A) = 19 mA; Tamb = 25 °C; see Figure 32. Fig 12. Amplifier A: typical drain current as a function of gain reduction; typical values BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 9 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf487 102 001aaf488 102 −102 bis, gis (mS) Yfs Yfs (mS) 10 ϕfs (deg) bis 1 −10 10 ϕfs gis 10−1 10−2 10 102 1 103 10 −1 103 102 f (MHz) f (MHz) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 19 mA. VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 19 mA. Fig 13. Amplifier A: input admittance as a function of frequency; typical values 001aaf489 103 Yrs (µS) −103 ϕrs (deg) ϕrs 102 −102 Fig 14. Amplifier A: forward transfer admittance and phase as a function of frequency; typical values 001aaf490 10 bos, gos (mS) 1 bos 10-1 gos Yrs −10 10 1 10 −1 103 102 10-2 10 102 103 f (MHz) f (MHz) VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 19 mA. VDS(A) = 5 V; VG2-S = 4 V; VDS(B) = 0 V; ID(A) = 19 mA. Fig 15. Amplifier A: reverse transfer admittance and phase as a function of frequency; typical values Fig 16. Amplifier A: output admittance as a function of frequency; typical values BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 10 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 8.1.2 Scattering parameters for amplifier A Table 9. Scattering parameters for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA; VDS(B) = 0 V; VG1-S(B) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) 40 0.9861 −3.2 3.14 176.75 0.00054 87.97 0.9934 −1.19 100 0.9883 −7.84 3.14 171.53 0.00104 87.69 0.9925 −2.85 200 0.9844 −15.7 3.12 163.1 0.00205 80.77 0.9918 −5.69 300 0.9761 −23.52 3.08 154.65 0.00295 76.33 0.9904 −8.51 400 0.9635 −31.26 3.03 146.33 0.00375 72.34 0.9888 −11.33 500 0.9486 −38.78 2.97 138.15 0.00437 67.97 0.9870 −14.13 600 0.9305 −46.2 2.90 130.12 0.00483 64.86 0.9847 −16.87 700 0.9105 −53.33 2.81 122.26 0.0051 62.13 0.9832 −19.61 800 0.8911 −60.2 2.73 114.65 0.0052 59.88 0.9817 −22.35 900 0.8723 −67.03 2.65 107.2 0.00515 58.8 0.9796 −25.03 1000 0.8521 −73.74 2.56 99.78 0.00498 58.03 0.9785 −27.08 8.2 Noise data for amplifier A Table 10. Noise data for amplifier A VDS(A) = 5 V; VG2-S = 4 V; ID(A) = 19 mA, Tamb = 25 °C; typical values. f (MHz) Γopt NFmin (dB) rn (ratio) (ratio) (deg) 400 0.9 0.749 23.7 0.667 800 1.2 0.688 48.65 0.583 8.3 Dynamic characteristics for amplifier B Table 11. Dynamic characteristics for amplifier B Common source; Tamb = 25 °C; VG2-S = 4 V; VDS(B) = 5 V; ID(B) = 13 mA. Symbol Parameter Conditions |yfs| Tj = 25 °C Ciss(G1) forward transfer admittance input capacitance at gate1 Min Typ Max Unit 28 33 43 mS f = 100 MHz [1] - 1.9 2.4 pF Ciss(G2) input capacitance at gate2 f = 100 MHz [1] - 3.4 - pF Coss output capacitance f = 100 MHz [1] - 0.85 - pF reverse transfer capacitance f = 100 MHz [1] - 20 - fF transducer power gain [1] Crss Gtr NF noise figure BS = BS(opt); BL = BL(opt) f = 200 MHz; GS = 2 mS; GL = 0.5 mS 32 36 40 dB f = 400 MHz; GS = 2 mS; GL = 1 mS 29 33 37 dB f = 800 MHz; GS = 3.3 mS; GL = 1 mS 27 31 35 dB f = 11 MHz; GS = 20 mS; BS = 0 S - 4 - dB f = 400 MHz; YS = YS(opt) - 0.9 1.5 dB f = 800 MHz; YS = YS(opt) - 1.2 1.9 dB BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 11 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET Table 11. Dynamic characteristics for amplifier B …continued Common source; Tamb = 25 °C; VG2-S = 4 V; VDS(B) = 5 V; ID(B) = 13 mA. Symbol Parameter Xmod Conditions cross modulation Min Typ Max Unit at 0 dB AGC 90 - - dBµV at 10 dB AGC - 88 - dBµV at 20 dB AGC - 94 - dBµV at 40 dB AGC 100 103 - dBµV [2] input level for k = 1 %; fw = 50 MHz; funw = 60 MHz [1] Calculated from S-parameters. [2] Measured in Figure 32 test circuit. 8.3.1 Graphs for amplifier B 001aaf491 50 001aaf492 30 (1) ID (mA) 40 ID (mA) (1) (2) (3) (2) (3) 20 (4) 30 (4) (5) (5) 20 (6) 10 (7) (6) 10 (7) 0 0 0 0.5 1.0 1.5 2.0 0 2 VG1-S (V) (1) VG1-S(B) = 1.6 V. (2) VG2-S = 3.5 V. (2) VG1-S(B) = 1.5 V. (3) VG2-S = 3 V. (3) VG1-S(B) = 1.4 V. (4) VG2-S = 2.5 V. (4) VG1-S(B) = 1.3 V. (5) VG2-S = 2 V. (5) VG1-S(B) = 1.2 V. (6) VG2-S = 1.5 V. (6) VG1-S(B) = 1.1 V. (7) VG2-S = 1 V. (7) VG1-S(B) = 1.0 V. VG2-S = 4 V; Tj = 25 °C. Fig 17. Amplifier B: transfer characteristics; typical values Fig 18. Amplifier B: output characteristics; typical values BF1210_1 Product data sheet 6 VDS (V) (1) VG2-S = 4 V. VDS(B) = 5 V; Tj = 25 °C. 4 © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 12 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf493 160 001aaf494 48 Yfs (mS) IG1 (µA) (1) 120 (1) 36 (2) (2) (3) 80 24 (3) (4) (5) 40 (4) 12 (5) (6) (6) (7) (7) 0 0 0 0.5 1.0 1.5 2.0 0 12 24 36 VG1-S (V) 48 ID (mA) (1) VG2-S = 4 V. (1) VG2-S = 4 V. (2) VG2-S = 3.5 V. (2) VG2-S = 3.5 V. (3) VG2-S = 3 V. (3) VG2-S = 3 V. (4) VG2-S = 2.5 V. (4) VG2-S = 2.5 V. (5) VG2-S = 2 V. (5) VG2-S = 2 V. (6) VG2-S = 1.5 V. (6) VG2-S = 1.5 V. (7) VG2-S = 1 V. (7) VG2-S = 1 V. VDS(B) = 5 V; Tj = 25 °C. VDS(B) = 5 V; Tj = 25 °C. Fig 19. Amplifier B: gate1 current as a function of gate1 voltage; typical values 001aaf495 24 Fig 20. Amplifier B: forward transfer admittance as a function of drain current; typical values 001aaf496 16 ID (mA) ID (mA) 12 16 8 8 4 0 0 10 20 30 40 50 IG1 (µA) VDS(B) = 5 V; VG2-S = 4 V; Tj = 25 °C. 0 0 2 3 4 5 VGG (V) VDS(B) = 5 V; VG2-S = 4 V; RG1(B) = 150 kΩ; Tj = 25 °C. Fig 21. Amplifier B: drain current as a function of gate1 current; typical values Fig 22. Amplifier B: drain voltage as a function of gate1 supply voltage (VGG); typical values BF1210_1 Product data sheet 1 © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 13 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf497 25 001aaf498 16 (1) ID (mA) (1) 20 (2) ID (mA) (2) (3) (4) 12 (5) 15 8 10 (3) (4) (5) 5 4 (6) (7) 0 0 0 1 2 3 4 5 VGG = VDS (V) 0 1 (1) RG1(B) = 68 kΩ. (1) VGG = 5.0 V. (2) RG1(B) = 82 kΩ. (2) VGG = 4.5 V. (3) RG1(B) = 100 kΩ. (3) VGG = 4.0 V. (4) RG1(B) = 120 kΩ. (4) VGG = 3.5 V. (5) RG1(B) = 150 kΩ. (5) VGG = 3.0 V. 2 3 4 5 VG2-S (V) RG1(B) = 150 kΩ; Tj = 25 °C. (6) RG1(B) = 180 kΩ. (7) RG1(B) = 220 kΩ. VG2-S = 5 V; RG1(B) connected to VGG; Tj = 25 °C. Fig 23. Amplifier B: drain current as a function of VDS and VGG; typical values Fig 24. Amplifier B: drain current as a function of gate2 voltage; typical values BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 14 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf499 0 001aaf500 110 Vunw (dBµV) gain reduction (dB) 105 20 100 95 40 90 85 60 0 1 2 3 4 0 10 20 VAGC (V) VDS(B) = 5 V; VG2-S(nom) = 4 V; RG1(B) = 150 kΩ; ID(nom)(B) = 13 mA; Tamb = 25 °C; see Figure 32. 30 40 50 gain reduction (dB) VDS(B) = 5 V; VG2-S(nom) = 4 V; RG1(B) = 150 kΩ; ID(nom)(B) = 13 mA; fw = 50 MHz; funw = 60 MHz; Tamb = 25 °C; see Figure 32. Fig 25. Amplifier B: typical gain reduction as a function of the AGC voltage; typical values Fig 26. Amplifier B: unwanted voltage for 1 % cross modulation as a function of gain reduction; typical values 001aaf501 15 ID (mA) 12 9 6 3 0 0 10 20 30 40 50 gain reduction (dB) VDS(B) = VGG = 5 V; VG2-S(nom) = 4 V; RG1(B) = 150 kΩ; ID(nom)(B) = 13 mA; f = 50 MHz; Tamb = 25 °C; see Figure 32. Fig 27. Amplifier B: typical drain current as a function of gain reduction; typical values BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 15 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 001aaf502 102 001aaf503 102 bis, gis (mS) Yfs Yfs (mS) 10 −102 ϕfs (deg) bis 1 −10 10 ϕfs gis 10−1 10−2 10 102 1 103 10 −1 103 102 f (MHz) f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 13 mA. VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 13 mA. Fig 28. Amplifier B: input admittance as a function of frequency; typical values 001aaf504 103 Yrs (mS) 103 ϕrs (deg) ϕrs 102 102 Fig 29. Amplifier B: forward transfer admittance and phase as a function of frequency; typical values 001aaf505 10 bos, gos (mS) 1 bos 10−1 gos Yrs 10 10 1 10 1 103 102 10−2 10 102 103 f (MHz) f (MHz) VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 13 mA. VDS(B) = 5 V; VG2-S = 4 V; VDS(A) = 0 V; ID(B) = 13 mA. Fig 30. Amplifier B: reverse transfer admittance and phase as a function of frequency; typical values Fig 31. Amplifier B: output admittance as a function of frequency; typical values BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 16 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 8.3.2 Scattering parameters for amplifier B Table 12. Scattering parameters for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 13 mA; VDS(A) = 0 V; VG1-S(A) = 0 V; Tamb = 25 °C; typical values. f (MHz) s11 s21 s12 s22 Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) Magnitude (ratio) Angle (deg) 40 0.9874 −2.79 3.41 177.08 0.00054 89.27 0.992 −1.26 100 0.9883 −6.8 3.41 172.57 0.00113 90.81 0.9900 −2.91 200 0.9844 −13.52 3.39 165.23 0.00224 89.67 0.9897 −5.81 300 0.9777 −20.2 3.36 157.88 0.00336 89.02 0.9889 −8.7 400 0.9684 −26.83 3.32 150.6 0.00447 88.43 0.9881 −11.61 500 0.9578 −33.32 3.27 143.38 0.0055 87.64 0.9870 −14.52 600 0.9442 −39.8 3.21 136.22 0.00649 87.53 0.9851 −17.39 700 0.9291 −46.08 3.16 129.15 0.00741 87.51 0.9838 −20.3 800 0.9147 −52.18 3.08 122.25 0.00828 87.7 0.9825 −23.2 900 0.9002 −58.35 3.08 115.4 0.00914 88.14 0.9803 −26.06 1000 0.8836 −64.49 2.93 108.49 0.00997 88.26 0.9789 −29.03 8.4 Noise data for amplifier B Table 13. Noise data for amplifier B VDS(B) = 5 V; VG2-S = 4 V; ID(B) = 13 mA, Tamb = 25 °C; typical values. f (MHz) Γopt NFmin (dB) rn (ratio) (ratio) (deg) 400 0.9 0.743 20.27 0.65 800 1.2 0.687 42.08 0.581 9. Test information VAGC R1 10 kΩ C1 C3 4.7 nF 4.7 nF C2 RGEN 50 Ω VI 4.7 nF R2 50 Ω DUT L1 ≈ 2.2 µH RL 50 Ω C4 RG1 VGG 4.7 nF VDS 001aad926 Fig 32. Cross modulation test setup (for one MOSFET) BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 17 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 10. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 c bp Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 33. Package outline SOT363 BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 18 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 11. Abbreviations Table 14. Abbreviations Acronym Description AGC Automatic Gain Control DC Direct Current MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor UHF Ultra High Frequency VHF Very High Frequency 12. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes BF1210_1 20061025 Product data sheet - - BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 19 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 13.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 13.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] BF1210_1 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 01 — 25 October 2006 20 of 21 BF1210 NXP Semiconductors Dual N-channel dual gate MOSFET 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.2 8.3 8.3.1 8.3.2 8.4 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics for amplifier A. . . . . . . 4 Graphs for amplifier A . . . . . . . . . . . . . . . . . . . . 6 Scattering parameters for amplifier A . . . . . . . 11 Noise data for amplifier A . . . . . . . . . . . . . . . . 11 Dynamic characteristics for amplifier B. . . . . . 11 Graphs for amplifier B . . . . . . . . . . . . . . . . . . . 12 Scattering parameters for amplifier B . . . . . . . 17 Noise data for amplifier B . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 17 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 October 2006 Document identifier: BF1210_1