19-6080; Rev 11/11 DS1315 Phantom Time Chip www.dalsemi.com DESCRIPTION The DS1315 Phantom Time Chip is a combination of a CMOS timekeeper and a nonvolatile memory controller. In the absence of power, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM. The watch keeps track of hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with fewer than 31 days, including leap year correction. The watch operates in one of two formats: a 12-hour mode with an AM/PM indicator or a 24-hour mode. The nonvolatile controller supplies all the necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The DS1315 can be interfaced with either RAM or ROM without leaving gaps in memory. 16 VCC1 15 VCC0 14 BAT2 4 13 RST GND 5 12 OE D 6 11 CEI Q 7 10 CEO GND 8 9 1 X2 2 WE 3 BAT1 DS1315 Real-Time Clock Keeps Track of Hundredths of Seconds, Seconds, Minutes, Hours, Days, Date of the Month, Months, and Years Automatic Leap Year Correction Valid Up to 2100 No Address Space Required to Communicate with RTC Provides Nonvolatile Controller Functions for Battery Backup of SRAM Supports Redundant Battery Attachment for High-Reliability Applications Full ±10% VCC Operating Range +3.3V or +5V Operation Industrial (-40°C to +85°C) Operating Temperature Ranges Available PIN DESCRIPTION X1, X2 WE PIN CONFIGURATIONS X1 FEATURES ROM/RAM BAT1 GND D Q ROM/ RAM CEO CEI OE RST BAT2 VCC0 VCC1 PDIP (300 mils) Pin Configurations continued at end of data sheet. 1 of 21 - 32.768kHz Crystal Connection - Write Enable - Battery 1 Input - Ground - Data Input - Data Output - ROM/RAM Mode Select - Chip Enable Output - Chip Enable Input - Output Enable - Reset - Battery 2 Input - Switched Supply Output - Power Supply Input DS1315 Phantom Time Chip ORDERING INFORMATION PART DS1315-33+ DS1315N-33+ TEMP RANGE 0°C to +70°C VOLTAGE PIN-PACKAGE (V) 3.3 16 PDIP (300 mils) TOP MARK* DS1315 336 -40°C to +85°C 3.3 16 PDIP (300 mils) DS1315 336 0°C to +70°C 5 16 PDIP (300 mils) DS1315 56 DS1315N-5+ -40°C to +85°C 5 16 PDIP (300 mils) DS1315 56 DS1315E-33+ 0°C to +70°C 3.3 20 TSSOP (4.4mm) DS1315E XXXX-336 DS1315EN-33+ -40°C to +85°C 3.3 20 TSSOP (4.4mm) DS1315E XXXX-336 DS1315EN-33+T&R -40°C to +85°C 3.3 20 TSSOP (4.4mm) DS1315E XXXX-336 0°C to +70°C 5 20 TSSOP (4.4mm) DS1315E XXXX-56 DS1315EN-5+ -40°C to +85°C 5 20 TSSOP (4.4mm) DS1315E XXXX-56 DS1315EN-5+T&R -40°C to +85°C 5 20 TSSOP (4.4mm) DS1315E XXXX-56 0°C to +70°C 3.3 16 SO (300 mils) DS1315 336 -40°C to +85°C 3.3 16 SO (300 mils) DS1315 336 0°C to +70°C 5 16 SO (300 mils) DS1315 56 -40°C to +85°C 5 16 SO (300 mils) DS1315S 56 0°C to +70°C 5 16 SO (300 mils) DS1315S 56 DS1315-5+ DS1315E-5+ DS1315S-33+ DS1315SN-33+ DS1315S-5+ DS1315SN-5+ DS1315S-5+T&R +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *A “+” symbol located anywhere on the top mark indicates a lead-free device. An “N” located in the bottom right-hand corner of the top of the package denotes an industrial device. “xxxx” can be any combination of characters. 2 of 21 DS1315 Phantom Time Chip Figure 1. Block Diagram 3 of 21 DS1315 Phantom Time Chip Operation Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the chip enable output pin ( CEO ). After recognition is established, the next 64 read or write cycles either extract or update data in the Time Chip and CEO remains high during this time, disabling the connected memory. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable input ( CEI ), output enable ( OE ), and write enable ( WE ). Initially, a read cycle using the CEI and OE control of the Time Chip starts the pattern recognition sequence by moving pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CEI and WE control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip. When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched. (This bit pattern is shown in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition sequence or data transfer sequence to the Time Chip. A standard 32.768kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6 pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Maxim Real-Time Clocks (RTCs). 4 of 21 DS1315 Phantom Time Chip Figure 2. Time Chip Comparison Register Definition Note: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 1019. 5 of 21 DS1315 Phantom Time Chip Nonvolatile Controller Operation The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the ROM/ RAM select pin. When ROM/ RAM is connected to ground, the controller is set in the RAM mode and performs the circuit functions required to make CMOS RAM and the timekeeping function nonvolatile. A switch is provided to direct power from the battery inputs or VCCI to VCCO with a maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninterrupted power to CMOS SRAM. The DS1315 also performs redundant battery control for high reliability. On power-fail, the battery with the highest voltage is automatically switched to VCCO. If only one battery is used in the system, the unused battery input should be connected to ground. The DS1315 safeguards the Time Chip and RAM data by power-fail detection and write protection. Power-fail detection occurs when VCCI falls below VPF which is set by an internal bandgap reference. The DS1315 constantly monitors the VCCI supply pin. When VCCI is less than VPF, power-fail circuitry forces the chip enable output ( CEO ) to VCCI or VBAT-0.2 volts for external RAM write protection. During nominal supply conditions, CEO will track CEI with a propagation delay. Internally, the DS1315 aborts any data transfer in progress without changing any of the Time Chip registers and prevents future access until VCCI exceeds VPF. A typical RAM/Time Chip interface is illustrated in Figure 3. When the ROM/ RAM pin is connected to VCCO, the controller is set in the ROM mode. Since ROM is a read-only device that retains data in the absence of power, battery backup and write protection is not required. As a result, the chip enable logic will force CEO low when power fails. However, the Time Chip does retain the same internal nonvolatility and write protection as described in the RAM mode. A typical ROM/Time Chip interface is illustrated in Figure 4. Figure 3. DS1315-to-RAM/Time Chip Interface 6 of 21 DS1315 Phantom Time Chip Figure 4. ROM/Time Chip Interface Time Chip Register Information Time Chip information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the Time Chip registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure 5. Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping though all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. AM/PM/12/24-Mode Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the 20-hour bit (20-23 hours). Oscillator and Reset Bits Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin input. When the reset bit is set to logic 1, the reset input pin is ignored. When the reset bit is set to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other in-puts. Bit 5 controls the oscillator. When set to logic 0, the oscillator turns on and the real time clock/calendar begins to increment. 7 of 21 DS1315 Phantom Time Chip Zero Bits Registers 1, 2, 3, 4, 5, and 6 contain 1 or more bits that will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable. Figure 5. Time Chip Register Definition 8 of 21 DS1315 Phantom Time Chip ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range, Commercial Operating Temperature Range, Industrial Storage Temperature Range Soldering Temperature (reflow) Lead Temperature (soldering, 10s) -0.3V to +6.0V 0°C to +70°C -40°C to +85°C -55°C to +125°C +260°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED OPERATING CONDITIONS (TA = Over the operating range.) PARAMETER SYMBOL 5V Power-Supply Voltage VCC Operation 3.3V Input Logic 1 VIH Input Logic 0 VIL Battery Voltage VBAT1 or VBAT1, VBAT2 VBAT2 MIN 4.5 3.0 2.2 -0.3 TYP 5.0 3.3 2.5 MAX 5.5 3.6 VCC + 0.3 +0.6 UNITS NOTES V 1 V V 1 1 3.7 V MAX UNITS NOTES 6 mA 6 150 mA 7 4 mA 6 1.3 mA 6 +1 µA 10 +1 µA DC OPERATING ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±10%, TA = Over the operating range.) PARAMETER SYMBOL MIN Average VCC Power-Supply ICC1 Current VCC Power-Supply Current, ICC01 (VCC0 = VCCI - 0.3) TTL Standby Current ICC2 ( CEI = VIH) CMOS Standby Current ICC3 ( CEI = VCCI - 0.2) Input Leakage Current IIL -1 (any input) Output Leakage Current IOL -1 (any input) Output Logic 1 Voltage VOH 2.4 (IOUT = -1.0 mA) Output Logic 0 Voltage VOL (IOUT = 4.0 mA) Power-Fail Trip Point VPF 4.25 Battery Switch Voltage VSW 9 of 21 TYP VBAT1, VBAT2 V 2 0.4 V 2 4.5 V 13 DS1315 Phantom Time Chip DC POWER-DOWN ELECTRICAL CHARACTERISTICS (VCC < 4.5V, TA = Over the operating range.) PARAMETER SYMBOL MIN VCCI - 0.2 or VCEO CEO Output Voltage VBAT1,2 0.2 VBAT1 or VBAT2 Battery IBAT Current Battery Backup Current ICCO2 @ VCCO = VBAT-0.2V TYP MAX UNITS NOTES V 8 0.5 µA 6 10 µA 9 AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/ RAM = GND (VCC = 5.0V ±10%, TA = Over the operating range.) PARAMETER SYMBOL MIN Read Cycle Time tRC 65 tCO CEI Access Time tOE OE Access Time tCOE 5 CEI to Output Low-Z tOEE 5 OE to Output Low-Z tOD CEI to Output High-Z t OE to Output High-Z ODO Read Recovery tRR 10 Write Cycle tWC 65 Write Pulse Width tWP 55 Write Recovery tWR 10 Data Setup tDS 30 Data Hold Time tDH 0 tCW 55 CEI Pulse Width tOW 55 OE Pulse Width t 65 RST Pulse Width RST TYP MAX 55 55 25 25 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 4 5 5 AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/ RAM = VCCO (VCC = 5.0V ±10%, TA = Over the operating range.) PARAMETER SYMBOL MIN Read Cycle Time tRC 65 tCO CEI Access Time tOE OE Access Time tCOE 5 CEI to Output Low Z tOEE 5 OE to Output Low Z tOD CEI to Output High Z t OE to Output High Z ODO Address Setup Time tAS 5 Address Hold Time tAH 5 Read Recovery tRR 10 10 of 21 TYP MAX 55 55 25 25 UNITS ns ns ns ns ns ns ns ns ns ns NOTES DS1315 Phantom Time Chip PARAMETER Write Cycle CEI Pulse Width OE Pulse Width Write Recovery Data Setup Data Hold Time RST Pulse Width SYMBOL tWC tCW tOW tWR tDS tDH tRST MIN 65 55 55 10 30 0 65 TYP MAX UNITS ns ns ns ns ns ns ns NOTES MAX UNITS NOTES 3 mA 6 100 mA 7 2 mA 6 1.1 mA 6 +1 µA +1 µA 4 5 5 DC OPERATING ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, TA = Over the operating range.) PARAMETER SYMBOL MIN Average VCC Power-Supply ICC1 Current Average VCC Power-Supply Current, ICC01 (VCCO = VCCI - 0.3) TTL Standby Current ICC2 ( CEI = VIH) CMOS Standby Current ICC3 ( CEI = VCCI - 0.2) Input Leakage Current IIL -1 (any input) Output Leakage Current ILO -1 (any input) Output Logic 1 Voltage VOH 2.4 (IOUT = 0.4 mA) Output Logic 0 Voltage VOL (IOUT = 1.6 mA) Power-Fail Trip Point VPF 2.8 Battery Switch Voltage VSW TYP VBAT1, VBAT2, or VPF V 2 0.4 V 2 2.97 V 14 DC POWER-DOWN ELECTRICAL CHARACTERISTICS (VCC < 2.97V, TA = Over the operating range.) PARAMETER SYMBOL MIN VCCI or VBAT1,2 - 0.2 TYP MAX UNITS NOTES V 8 CEO Output Voltage VCEO VBAT1 OR VBAT2 Battery Current IBAT 0.5 µA 6 Battery Backup Current at VCCO = VBAT - 0.2 ICCO2 10 µA 9 11 of 21 DS1315 Phantom Time Chip AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/ RAM = GND (VCC = 3.3V ±10%, TA = Over the operating range.) PARAMETER SYMBOL MIN Read Cycle Time tRC 120 t CEI Access Time CO t Access Time OE OE tCOE 5 CEI to Output Low-Z tOEE 5 OE to Output Low-Z tOD CEI to Output High-Z tODO OE to Output High-Z Read Recovery tRR 20 Write Cycle tWC 120 Write Pulse Width tWP 100 Write Recovery tWR 20 Data Setup tDS 45 Data Hold Time tDH 0 tCW 100 CEI Pulse Width tOW 100 OE Pulse Width tRST 120 RST Pulse Width 12 of 21 TYP MAX 100 100 40 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 4 5 5 DS1315 Phantom Time Chip AC ELECTRICAL OPERATING CHARACTERISTICS—ROM/ RAM = VCCO (VCC = 3.3V ±10%, TA = Over the operating range.) PARAMETER SYMBOL MIN Read Cycle Time tRC 120 t CEI Access Time CO t Access Time OE OE tCOE 5 CEI to Output Low-Z tOEE 5 OE to Output Low-Z tOD CEI to Output High-Z tODO OE to Output High-Z Address Setup Time tAS 10 Address Hold Time tAH 10 Read Recovery tRR 20 Write Cycle tWC 120 tCW 100 CEI Pulse Width tOW 100 OE Pulse Width Write Recovery tWR 20 Data Setup tDS 45 Data Hold Time tDH 0 t 120 RST Pulse Width RST TYP MAX 100 100 40 40 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES UNITS pF pF NOTES 4 5 5 CAPACITANCE (TA = +25°C) PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN 13 of 21 TYP MAX 10 10 DS1315 Phantom Time Chip Figure 6. Timing Diagram: Read Cycle to Time Chip ROM/ RAM = GND Figure 7. Timing Diagram: Write Cycle to Time Chip ROM/ RAM = GND 14 of 21 DS1315 Phantom Time Chip Figure 8. Timing Diagram: Read Cycle to Time Chip ROM/ RAM = VCCO Figure 9. Timing Diagram: Write Cycle to Time Chip ROM/ RAM = VCCO 15 of 21 DS1315 Phantom Time Chip Figure 10. Timing Diagram: Reset Pulse tRST RST 5V DEVICE POWER-UP/POWER-DOWN CHARACTERISTICS— ROM/ RAM = VCCO OR GND (TA = 0°C to +70°C) PARAMETER Recovery Time at Power-Up VCC Slew Rate Power-Down VPF(max) to VPF(min) VCC Slew Rate Power-Down VPF(min) to VSW VCC Slew Rate Power-Up VPF(min) to VPF(max) CEI High to Power-Fail CEI Propagation Delay SYMBOL tREC MIN 1.5 tF UNITS ms NOTES 11 300 µs 11 tFB 10 µs 11 tR 0 µs 11 µs ns 11 2, 3, 11 tPF tPD TYP MAX 2.5 0 5 Figure 11. 5V Power-Up Condition 16 of 21 DS1315 Phantom Time Chip Figure 12. 5V Power-Down Condition 3.3V DEVICE POWER-UP POWER-DOWN CHARACTERISTICS— ROM/ RAM = VCCO OR GND (TA = 0°C to +70°C) PARAMETER Recovery Time at Power-Up VCC Slew Rate Power-Down VPF(max) to VPF(min) VCC Slew Rate Power-Up VPF(min) to VPF(max) CEI High to Power-Fail CEI Propagation Delay SYMBOL tREC MIN 1.5 tF UNITS ms NOTES 12 300 µs 12 tR 0 µs 12 tPF tPD 0 µs ns 12 2, 3, 11 17 of 21 TYP MAX 2.5 10 DS1315 Phantom Time Chip NOTES: 1) 2) 3) 4) All voltages are referenced to ground. Measured with load shown in Figure 15. Input pulse rise and fall times equal 10ns. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 5) tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 6) Measured without RAM connected. 7) ICCO1 is the maximum average load current the DS1315 can supply to external memory. 8) Applies to CEO with the ROM/ RAM pin grounded. When the ROM/ RAM pin is connected to VCCO, CEO will go to a low level as VCCI falls below VBAT. 9) ICCO2 is the maximum average load current that the DS1315 can supply to memory in the battery backup mode. 10) Applies to all input pins except RST . RST is pulled internally to VCCI. 11) See Figures 11 and 12. 12) See Figures 13 and 14. 13) VSW is determined by the larger of VBAT1 and VBAT2. 14) VSW is determined by the smaller of VBAT1, VBAT2, and VPF. Figure 13. 3.3V Power-Up Condition 18 of 21 DS1315 Phantom Time Chip Figure 14. 3.3V Power-Down Condition Figure 15. Output Load 19 of 21 DS1315 Phantom Time Chip PIN CONFIGURATIONS (continued) X1 1 16 VCC1 X1 1 20 VCC1 X2 2 15 VCC0 X2 2 19 VCC0 WE 3 14 BAT2 WE 3 18 BAT2 BAT1 4 13 RST 5 12 OE 17 16 NC GND NC BAT1 4 D 6 11 CEI GND 15 OE Q 7 10 CEO NC 6 7 14 NC GND 8 9 D 8 13 CEI Q 9 12 CEO GND 10 11 ROM/RAM ROM/RAM 16-Pin SO (300 mil) 5 RST 20-Pin TSSOP PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 16 PDIP 16 TSSOP 16 SO PACKAGE CODE P16+1 U20+1 W16+2 20 of 21 OUTLINE NO. 21-0043 21-0066 21-0042 LAND PATTERN NO. — 90-0116 90-0107 DS1315 Phantom Time Chip REVISION HISTORY REVISION DATE 11/11 DESCRIPTION Updated the Features, Ordering Information, AM/PM/12/24-MODE, Absolute Maximum Ratings, and Package Information sections PAGES CHANGED 1, 2, 7, 9, 20 21 of 21 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc