GPIO ICs Series GPIO Expander IC No.09098EAT01 BU8272GUW ●Description GPIO expander is useful especially for the application that is in short of IO ports. It can 2 1. Control GPIO output states by I C write protocol. 2 2. Know GPIO input states by I C read protocol. Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander. GPIO expander are also equipped with Built-in power on reset, 3V tolerant input,and NMOS open-drain output. ●Features 1) 400Kbps, 2-Wire serial interface 2) Interrupt output 3) 20-bit General purpose input/output interface 8-bit and 12-bit IO groups are designed for different power supply voltages from the device core voltage supply ● Absolute Maximum Ratings (Ta=25℃) Item Supply Voltage Symbol Value Unit comment VDD -0.3 ~ +2.5 V - VDDI2C -0.3 ~ +3.5 V - VDDIO -0.3 ~ +3.5 -0.3 ~ VDD +0.5 Input voltage VI -0.3 ~ VDDI2C +0.5 -0.3 ~ VDDIO +0.5 Storage temperature range Tstg Package power V - *1 V CMOS Core *1 V CMOS I/O for 2-Wire V CMOS I/O *1 o -55 ~ +125 PD 310 *2 *1 The input voltage range doesn't exceed absolute maximum ratings even including +0.5 V. *2 Package dissipation will be reduced each 3.1mW/ oC when the ambient temperature increases beyond 25 oC. C - mW - This IC is not designed to be X-ray proof. ● Recommended Operating Conditions o o (Ta=-25 C ~+85 C) Limit Item Symbol Unit Condition 1.95 V Core - 3.45 V 2-Wire,INT,ADR, XRST 1.65 - 3.45 V GPIO[7:0] VVDDIO2 1.65 - 3.45 V GPIO[19:8] FI2C - - 400 KHz Slave Min Typ Max VVDD 1.65 1.80 Supply voltage（VDDI2C） VVDDI2C 1.65 Supply voltage（VDDIO1） VVDDIO1 Supply voltage（VDDIO2） 2-Wire operating Frequency Supply voltage (VDD） www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 1/17 2009.09 - Rev.A Technical Note BU8272GUW ● Package Specification（VBGA035W040） Fig.1 Package Specification www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 2/17 2009.09 - Rev.A Technical Note BU8272GUW ● Pin Diagram F VDD GPIO0 GPIO1 GPIO3 GPIO5 VDDIO1 E INT GND GPIO2 GPIO4 GPIO6 GPIO7 D SCL XRST GND GND GPIO9 GPIO8 C ADR SDA GND GND GPIO11 GPIO10 GPIO19 GPIO17 GPIO15 VDD GPIO12 VDDI2C GPIO18 GPIO16 GPIO14 GPIO13 VDDIO2 1 2 3 4 5 6 B A Fig.2 Pin Diagram（Bottom View） www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 3/17 2009.09 - Rev.A Technical Note BU8272GUW ● Block Diagram Functional Block Diagram Interrupt Logic INT INT_MASK VDDI2C IN/OUT Control VDDIO1 ADR SCL SDA XRST I2C Bus Control Input Filter 8bit GPIO [7:0] 8bit GPIO[7:0] 12bit GPIO [19:8] 12bit GPIO[19:8] Shift Register Reset VDDIO2 VDD Write Pulse Read Pulse Fig.3 Functional Block Diagram www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 4/17 2009.09 - Rev.A Technical Note BU8272GUW ● Electrical Specification o VDD=1.8V, VDDIO=3.0V, VDDI2C=3.0V, Ta=25 C，without output load conditions Limit Item Symbol Min. Typ. Max. Unit comment Input H Voltage VIH 0.75xVDDIO - - V - Input L Voltage VIL - - 0.25xVDDIO V - Input H Current IIH 0 - 3 A - Input L Current IIL -3 - 0 A - Output H Voltage VOH VDDIO－0.2 - - V IOH=-1.0mA Output L Voltage VOL - - 0.2 V IOL=1.0mA SCL clk frequency fSCL - - 400 KHz Bus free time tBUF 1.3 - - s （repeat）Start condition Setup Time tSU:STA 0.6 - - s （repeat）Start condition Hold Time tHD:STA 0.6 - - s SCL Low Time tLOW 1.3 - - s SCL High Time tHIGH 0.6 - - s Data Setup Time tSU:DAT 100 - - ns Data Hold Time tHD:DAT 0 - - ns Stop condition Setup Time tSU:STO 0.6 - - s Interrupt Valid tIV - - 0.1 s Interrupt Reset tIR - - 1.0 s Output Data Valid tDV - - 0.8 s Input Data Setup Time tDS 100 - - ns Input Data Hold Time tDH 0 - - s Standby Current ISTBY - - 3.0 A www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 5/17 2009.09 - Rev.A Technical Note BU8272GUW ● Pin-out Functional Descriptions 1. Pin table PIN No. Land number PIN name I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A1 (NC) C3 C1 C2 D1 D2 E1 E2 F1 F2 D3 F3 E3 F4 E4 F5 E5 F6 E6 D4 D6 D5 C6 C5 B6 B5 A6 A5 C4 A4 B4 A3 B3 A2 B2 VDDI2C GND ADR SDA SCL XRST INT GND VDD GPIO0 GND GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 VDDIO1 GPIO7 GND GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 VDD VDDIO2 GPIO13 GND GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 IN INOUT IN IN OUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT Power source system VDDI2C VDDI2C VDDI2C VDDI2C VDDI2C VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 INOUT INOUT INOUT INOUT INOUT INOUT INOUT VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 *1 *2 Function Serial data inout for 2-Wire Clock for 2-Wire Reset（Low Active） Interrupt signal *1 Cell Type XRST B A B B C Hi-z L -*3 General purpose inout. Pull-up to VDD *2 A Hi-z General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD *2 A A A A A A Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z General purpose inout. Pull-up to VDD *2 A Hi-z General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD *2 A A A A A Hi-z Hi-z Hi-z Hi-z Hi-z General purpose inout. Pull-up to VDD *2 A Hi-z General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD *2 A A A A A A Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 *2 The Low Active or High Active of interrupt output level and specific bit mask control are decided by internal register value. When IOSEL register is set to “1”, please pull-up IO output to the same value as VDDIO1 or VDDIO2 voltages respectively. www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 6/17 2009.09 - Rev.A Technical Note BU8272GUW 2. Equivalent IO circuit diagram A B C Fig.4 Equivalent IO circuit diagram www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 7/17 2009.09 - Rev.A Technical Note BU8272GUW ● Functional Description 1 2-Wire Bus Interface 1.1 Slave address Please pull-up SDA and SCL to the same potential of voltage as DVDDI2C. BU8272GUW is controlled by using an on-chip 2-Wire slave interface. Two kinds of the device address, “0001111” at ADR=”1” or “0001000” at ADR=”0” can be used. The transfer bit rate supports Fast-mode up to max 400Kbps. A7 A6 A5 A4 A3 A2 A1 ADR=0 0 0 0 1 0 0 0 ADR=1 0 0 0 1 1 1 2-Wire Slave address 1 W/R 0/1 Fig. 5 Slave address 1.2 Data transfer One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should keep the value. If SDA changes during SCL = “1”, a START condition or STOP condition occur and it is interpreted as a control signal. SDA SCL Data is valid when SDA is stable SDA is variable Fig. 6 Data transfer 1.3 START-STOP conditions When SDA and SCL are “1”, the data isn’t transferred on the 2-wire bus. If SCL remains “1” and SDA transfers from “1” to “0”, it means a “Start condition” is occurred and access is started. If SCL remains “1” and SDA transfers from “0” to “1”, it means a “Stop condition” is occurred and access is stopped. SDA SCL S P START condition STOP condition Fig. 7 START-STOP conditions www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 8/17 2009.09 - Rev.A Technical Note BU8272GUW 1.4 Acknowledge After start condition is occurred, 8 bits data will be transferred. Then the “Master” opens SDA and “Slave” de-asserts SDA to “0” as an “Acknowledge” returned. SDA output from “Master” Not acknowledge SDA output from “Slave” SCL Acknowledg e 1 S 2 8 9 Clock pulse For Acknowledgs START condition Fig. 8 Acknowledge 1.5 Writing protocol A writing protocol is shown in Fig.8-5 below. GPIO register address in BU8272GUW is transferred after one byte of slave address with a write commend. The 3rd byte data is written to internal register which defined by the 2nd byte. After the each byte transfer, the register address will be automatically increased. However, when the register address increased to the final address (09h), it will be reset to (00h) after the byte transfer. GPIO register address (00h) is assigned to GPIO register[7:0], the register address (01h) is assigned to GPIO register[15:8], and the register address (02h) is assigned to GPIO register[19:16]. Only the 4 bits LSB data are valid in the register with GPIO register address (02h). S X X X X X X X 0 A X X X X A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A Slave address Register address D7 D6 D5 D4 D3 D2 D1 D0 A P data data R/W=0(write) Register address increment Transmit from master Register address increment A=acknowledge A=not acknowledge S=Start condition P=Stop condition Transmit from slave Fig. 9 Writing protocol www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 9/17 2009.09 - Rev.A Technical Note BU8272GUW 1.6 Reading protocol After Writing the slave address and Read/Write commend bits, the next byte is read. The reading register address is next of previous accessed address. Therefore, the data is read with address increment. When the address in increased to the last, the following read address will be reset to (00h). When the GPIO port [19:16] is read, 4 bits of “0” will be added from MSB, and the value of 4 bits from GPIO port [19:16] is read from 2-wire interface. S X X X X X X X 1 A D7 D6 D5 D4 D3 D2 D1 D0 A Salve address D7 D6 D5 D4 D3 D2 D1 D0 A P data data R/W=1(Read) Register Address increment Register address increment A=acknowledge A=not acknowledge S=Start condition P=Stop condition Transmit fronm master Transmit from slave Fig. 10 Readout protocol 1.7 Complex reading protocol After the specifying the internal register address, a resending start condition occurs and the direction of data transfer is changed then reading access is done. Therefore, the data is read followed by address increment. If the address is increased to the last, it will be reset to (00h). S X X X X X X X 0 A X X X X A3 A2 A1 A0 A Sr X X X X X X X 1 A Slave address Slave address Register address R/W=0(write) R/W=1(read) D7 D6 D5 D4 D3 D2 D1 D0 A P D7 D6 D5 D4 D3 D2 D1 D0 A data Transmit from master data Register address increment Transmit from slave A=acknowledge A=not aclnowledge S=Start condition P=Stop condition Sr=Start condition Register address increment Fig. 11 Complex reading protocol www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 10/17 2009.09 - Rev.A Technical Note BU8272GUW 1.8 Timing Diagram Transfer state (Repeat) Start condition tSU;STA BIT 7 BIT 6 Ack tLOW tHIGH 1/fSCLK Stop condition SCL SDA tBUF tHD;STA tSU;DAT tHD;DAT tSU;STO Fig. 12 Timing Diagram www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 11/17 2009.09 - Rev.A Technical Note BU8272GUW 2. GPIO･INT Interface The default mode of all GPIO [19:0] ports are input mode upon the power-on. By setting the specific bit of Interrupt Mask Sel register to “1”, the corresponding bit of Interrupt will be masked. There are two kinds of ways to control input / output operations. The first way is to change read / write register value in each corresponding bit. Second way is to write each GPIO register a “0” value for ‘Output operation’ and a “1” value for ‘input operation’. It is necessary to pull up the output to the same voltage value as the corresponding I/O power supply in the second way. Interrupt Logic Please pull up the output to the same voltage value as the corresponding I/O power supply Interrupt Mask GPI Reg Read Data Register S XRST Read Configuration Pulse 0 1 GPIO[19:0] GPO Reg Data From Shift Register Write Configuration Pulse 0 1 S IOSEL Reg R/W Reg Data From Shift Register S Fig. 13 GPIO・INT system www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 12/17 2009.09 - Rev.A Technical Note BU8272GUW 2.1 Write to GPIO Port After setting the internal register address, the data from master is written from MSB. After Acknowledge is returned, the value of each GPIO port will be changed. ・IOSEL=1 In the condition that IOSEL register is “1”, after sending Acknowledge, a value “0” is output from the GPIO port which the corresponding bit is transferred as ‘0’, and a input-mode(Hi-Z) is output from GPIO port which the corresponding bit is transferred as ‘1’. SCL 1 SDA S 2 X 3 X 4 X 5 X 6 X 7 X 8 X 0 9 Ack MSB Reg Address LSB Ack MSB Data1 (GPIO[7:0]) LSB Ack MSB Data2 (GPIO[15:8]) LSB Ack P Acknowledge From Slave Start Condition Write Acknowledge From Slave Acknowledge From Slave Stop Condition GPIO [7:0] Data1 Valid tDV tDV GPIO [15:8] Data2 Valid Fig. 14 Write to GPIO port （Pull-up-mode） ・IOSEL=0 In the condition that IOSEL register is “0”, data input or output is defined by the value of RWSEL register. Therefore, after “0” is written to each bit of RWSEL register, the data is output from GPIO port. If “0” is written to RWSEL register at first, the data will be output immediately from the GPIO port after the acknowledge signaling. 1 SCL SDA S X 2 X 3 X 4 X 5 X 6 X 7 X 8 0 9 Ack MSB Reg Address LSB Ack MSB Data1 (GPIO[7:0]) LSB Ack MSB RWSEL = Write Mode LSB Ack P Acknowledge From Slave Start Condition Write Acknowledge From Slave Acknowledge From Slave Stop Condition Data1 Valid GPIO [7:0] tDV GPIO [15:8] Data2 Valid tDV Fig. 15 Write to GPIO port （RWSEL-mode） www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 13/17 2009.09 - Rev.A Technical Note BU8272GUW 2.2 Read From GPIO Port After slave address and R/W bit is written, the GPIO ports value will be read into the GPIO registers. (refer to section 8.1.6 for 2-wire reading protocol.) The data fixed between tow consecutive acknowledges will be transferred to the Master. SCL SDA 1 S X 2 X 3 X 4 X 5 X 6 X 7 8 X 1 9 Ack MSB Data0 LSB Ack MSB Data1 LSB NA P Acknowledge From Master Start Condition Read Acknowledge From Slave Stop Condition No Acknowledge From Master GPIO Data0 Data1 Data2 tDS tDH Fig. 16 Read from GPIO port 2.3 Interrupt Valid/Reset The transition of each GPIO port de-asserts the interrupt signal (INT), generates the interrupt signal by asserting the INT after each acknowledge signaling. Either a “High-Active” or a “Low-Active” interrupt signaling can be defined by changing the INTSEL register value beforehand. SCL SDA 1 S X 2 X 3 X 4 X 5 X 6 X 7 X 8 1 9 Ack MSB Data2 LSB Ack MSB Data3 LSB NA P Acknowledge From Master Start Condition Read Acknowledge From Slave Stop Condition No Acknowledge From Master GPIO Data1 Data2 Data3 INT tIV tIR Fig. 17 Interrupt Valid/Reset www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 14/17 2009.09 - Rev.A Technical Note BU8272GUW ● The Setting Registers When setting address is written beyond 00h~09h, the register address will be forced to value 00h. When the final address is set to 09h, then the next address 00h will be written. By making XRST “Low”, the setting register value will be initialed shown in following register map. 1. Register map Addr Init Type D7 D6 D5 D4 D3 D2 D1 D0 00h ffh R/W GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 01h ffh R/W GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 02h 0fh R/W - - - - GPIO19 GPIO18 GPIO17 GPIO16 03h 00h R/W MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 04h 00h R/W MASK15 MASK14 MASK13 MASK12 MASK11 MASK10 MASK9 MASK8 05h 00h R/W - - - - MASK19 MASK18 MASK17 MASK16 06h ffh R/W R/W RWSEL5 RWSEL1 3 RWSEL4 RWSEL1 2 RWSEL8 0fh R/W - - - - 09h 03h R/W - - - - RWSEL2 RWSEL1 0 RWSEL1 8 INTSEL RWSEL9 08h RWSEL3 RWSEL1 1 RWSEL1 9 - RWSEL0 ffh RWSEL6 RWSEL1 4 RWSEL1 07h RWSEL7 RWSEL1 5 RWSEL1 7 IOSEL2 RWSEL1 6 IOSEL1 2. Register functional explanations Symbol Addr Init GPIO7 ～ GPIO0 00h ffh Read or write data of GPIO bit 0 to 7. GPIO15 ～ GPIO8 01h ffh Read or write data of GPIO bit 8 to 15. GPIO19 ～ GPIO16 02h 0fh Read or write data of GPIO bit 16 to bit 19. In writing mode, 4 bits of MSB is ignored and in reading mode, 4 bits of “0” is filled up from MSB. MASK7 ～ MASK0 03h 00h 0: Interrupt is not masked when “0” is written to GPIO bit 0 to 7 1: Interrupt is masked when “0” is written to GPIO bit 0 to 7 MASK15 ～ MASK8 04h 00h 0: Interrupt is not masked When “0” is written to GPIO bit 8 to 15 1: Interrupt is masked When “0” is written to GPIO bit 8 to 15 MASK19 ～ MASK16 05h 00h 0: Interrupt is not masked when “0” is written to GPIO bit 16 to 19 1: Interrupt is masked when “0” is written to GPIO bit 16 to 19 In writing mode, 4 bit of MSB is ignored and in reading mode, 4 bits of “0” is filled up from MSB. RWSEL7 ～ RWSEL0 06h ffh 0: GPIO bit 0 through 7 becomes output mode. 1: GPIO bit 0 through 7 becomes input mode. RWSEL15 ～ RWSEL8 07h Ffh 0: GPIO bit 8 through 15 becomes output mode. 1: GPIO bit 8 through 15 becomes input mode. RWSEL19 ～ RWSEL16 08h 0fh 0: GPIO bit 16 through 19 becomes output mode. 1: GPIO bit 16 through 19 becomes input mode. 1h 0: RWSEL bit 0 through 7 becomes available. 1: Change to pull-up mode. 1h 0: RWSEL bit 8 through 19 becomes available. 1: Change to pull-up mode. 0h 0: Make Interrupt “Low active”. 1: Make Interrupt “High active”. IOSEL1 IOSEL2 INTSEL 09h www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Description 15/17 2009.09 - Rev.A Technical Note BU8272GUW ● Appendix 1. About difference between I2C and 2-Wire 2-wire interface logic uses a normal IN/OUT cell (Hi-Z or only “0” output) instead of an Open-Drain cell in normal I2C interface. For this reason, the VDDI2C voltage level must be same as the connected other normal I2C masters’. Therefore, any other I2C slave with same bus level can be connected to the bus. 2 .In case of illegal access *1 during 2-Wire data transference The current data will be canceled and next access is necessary. *1 In case of a consecutive Start-condition and Stop-condition occurred. In case of Resend-condition or Stop-condition occurred during a slave address or R/W bit witting cycles. In case of Resend-condition or Stop-condition occurred during data witting cycles. 3. About the handling of the no using GPIO port Any no using GPIO port must be pulled-up or connected to GND. In order to prevent from any unexpected interrupt happening when a no using GPIO is connected to GND, the corresponding bit of GPIO Mask register must be disabled by Mask register access, or simply read the GPIO value into corresponding internal GPIO port register. The no using GPIO port power supply (VDDIO1 or VDDIO2) must be connected to the voltage value defined in this specification, never left it open. 4. Caution of power on sequence The BU8272GUW can not works correctly even one of the power supply among the core power supply (VDD) and the I/O power supply ( VDDI2C, VDDIO1, VDDIO2) is not connected to specified conditions described in this specification. The power on sequence must be designed to give core power supply first then I/O power. Inversely, the I/O power supply must be switched off before the core power down in the device power down sequence. 5. Reset release timing Core power supply (VDD) and I/O power supply (VDDI2C, VDDIO1, VDDIO2) first. Afterwards, release XRST. VD VDDI2C , VDDIO1(2) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. Release XRST 16/17 2009.09 - Rev.A Technical Note BU8272GUW ●Ordering part number B U 8 Part No. 2 7 2 G Part No. U W Package GUW: VBGA035W040 - E 2 Packaging and forming specification E2: Embossed tape and reel VBGA035W040 <Tape and Reel information> 4.0 ± 0.1 35- φ 0.295±0.05 φ 0.05 M S AB A P=0.5×5 0.5 F E D C B A Embossed carrier tape (with dry pack) Quantity 2500pcs Direction of feed E2 The direction is the 1pin of product is at the upper left when you hold ( reel on the left hand and you pull out the tape on the right hand ) S B P=0.5×5 0.08 S 0.75 ± 0.1 Tape 0.75 ± 0.1 0.10 0.9MAX. 4.0 ± 0.1 1PIN MARK 1pin 1 2 3 4 5 6 Reel (Unit : mm) www.rohm.com © 2009 ROHM Co., Ltd. All rights reserved. 17/17 Direction of feed ∗ Order quantity needs to be multiple of the minimum quantity. 2009.09 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. 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