CY2040-2/3 32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input Features • • • • Precision RTC 32 kHz and 24 MHz output Power-down mode (32 kHz on) is < 50 uA Suspend mode (V24M = off) is typically 5 uA Low RMS period Jitter (< 40 ps) • 16-pin TSSOP package • 3.3V + 5% Voltage Supply • CY2040-2 multiplier 32.000 kHz × 750 = 24.0 MHz (requires a single 32.000 kHz crystal) • CY2040-3 enables the 32 kHz and 24.0 MHz oscillators (requires a 32.768 kHz and 24.000 MHz crystal) Logic Block Diagram XIN32K XOUT32K Pin Configuration 32kHz OSC OUT32K NC 32K P LLE N P D24M # Q=INPUT PLL DIVIDER 1 16 2 15 3 14 VSS O UT24M O UT32KPLL V32K 4 13 O UT32K V24M 5 12 XO UT24M X IN 3 2 K 6 11 X IN 2 4 M XO UT32K 7 10 VSS NC 8 9 POST DIVIDER NC P=FEEDBACK DIVIDER OUT24M XIN24M XOUT24M 24MHz OSC OUT32KPLL PD24M# CONTROL LOGIC 32KPLLEN Cypress Semiconductor Corporation Document #: 38-07122 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 14, 2002 CY2040-2/3 Pin Description Pin # Symbol Type Description 1 NC NC No connection (leave it floating). 2 32KPLLEN I, PU OUT32KPLL (pin 14) output enable (OE). 1 = running, 0 = 3-state. Weak pull-up. 3 PD24M# I, PU Power down pin to turn off OUT32M, OUT32KPLL, PLL, post divider and 24-MHz crystal oscillator. Active Low. 1 = running, 0 = power down. Weak pull-up. 4 V32K[1] P 3.3V supply for the 32 kHz oscillator circuit (Vbatt). 5 V24M[1] P 3.3V supply for the 24 MHz oscillator and PLL circuits (VDD). 6 XIN32K I Crystal connection input for OSC1. Recommend using CLoad = 6 pF crystal with ESR <= 55 kΩ. 7 XOUT32K O Oscillator output pin connected to crystal OSC1. 8 NC NC No connection (leave it floating). 9 NC NC No connection (leave it floating). 10 VSS P Power supply ground. 11 Xin24M I Crystal connection input for OSC2. Recommend to use CLoad = 10pF crystal with ESR <= 20Ω. Can be left floating if 24M crystal is not used (CY2040-2). 12 OUT24M O Oscillator output pin connected to crystal OSC2. Leave this pin unconnected if 24M crystal is not used (CY2040-2). 13 OUT32K O 3.3V 32 kHz buffered output of the reference crystal. 14 OUT32KPLL O 32 kHz output. Can be enabled/disabled by 32KPLLEN pin. 15 OUT24M O 3.3V 24 MHz buffered output: either 32 kHz × 750 (-2) or from 24.0 MHz OSC2 (-3). 16 VSS P Power supply ground. Device Configuration Device Input Crystals Output Frequency CY2040-2 32.000 kHz crystal with CLoad = 6pF and ESR <= 55 kΩ. OUT32K = 32.000 kHz; OUT24M = 24.000 MHz, OUT32KPLL=32.000kHz CY2040-3 32.768 kHz crystal with CLoad = 6pF and ESR <= 55 kΩ. OUT32K = 32.768 kHz; OUT24M = 24.000 MHz, 24.000 MHz crystal with CLoad = 10pF and ESR <= 20 Ω. OUT32KPLL = 32.768 kHz Note: 1. The two power supply pins, V32K and V24M, should be shorted externally. Document #: 38-07122 Rev. *A Page 2 of 7 CY2040-2/3 Absolute Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ................................... –0.5V to +7.0V Storage Temperature (Non-Condensing) ..............................–55°C to +150°C Junction Temperature .........................+150°C Static Discharge Voltage..................... > 2000V (per MIL-STD-883, Method 3015) Input Voltage ...................................... –0.5V to V24M +0.5 Operating Conditions Parameter Description Conditions Min. Max. Unit V32K Vbatt, Supply voltage Relative to VSS 3.135 3.465 V V24M VDD, Supply voltage Relative to VSS 3.135 3.465 V TA Operating Temperature, Ambient Operating Temperature Range, Ambient 0 70 °C CL Load Capacitance Max Capacitive Load on OUT32K, OUT32KPLL, and OUT24M 15 pF tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 50 ms 0.05 DC Characteristics Parameter Description Test Conditions Min. Typ. Max. Unit 0.2 VDD V VIL Input low voltage (PD24M# and 32KPLLEN Pins) V24M = 3.3 + 5% VIH Input high voltage (PD24M# and 32KPLLEN Pins) V24M = 3.3 + 5% IIL Input low current (PD24M# and 32KPLLEN Pins) VIN = 0V <1 10 µA IIH Input high current (PD24M# and 32KPLLEN Pins) VIN = V24M <1 5 µA IDD Dynamic Supply Current with V24M = V32K = 3.3 + 5%, no load at outputs. fOUT32K = 32.768kHz or 32.000kHz, fOUT24M = 24MHz, fOUT32KPLL = 3-state. 10 25 mA IPT Power-down Supply Current V24M = V32K = 3.3 + 5% (PD24M# = “0”) 20 50 µA 0.4 V 0.4 V 50 µA 0.4 V 0.7 VDD V OUT32K (V32K = 3.3V +5%) VOL Output low voltage V32K = 3.3 + 5%, IOL= 8 mA VOH Output high voltage V32K = 3.3 + 5%, IOH= – 8 mA V32K – 0.4 OUT24M (V24M = 3.3V +5%) VOL Output low voltage V24M = 3.3 + 5%, IOL= 8 mA VOH Output high voltage V24M = 3.3 + 5%, IOH= – 8 mA IOZ Output leakage current (OUT24M) V24M = 3.3 + 5%, with output disabled V24M – 0.4 1 OUT32KPLL (V24M = 3.3V +5%) VOL Output low voltage V24M = 3.3 + 5%, IOL= 8 mA VOH Output high voltage V24M = 3.3 + 5%, IOH= –8 mA Document #: 38-07122 Rev. *A V24M – 0.4 Page 3 of 7 CY2040-2/3 DC Characteristics Parameter IOZ Description Output leakage current (OUT32KPLL) Test Conditions Min. V24M = 3.3 + 5%, with output disabled Typ. Max. Unit 1 50 µA Max. Unit AC Characteristics Parameter Description Test Conditions Min. Typ. OUT32K AC Characteristics tr1 OUT32K Rise time 20% to 80% V32K tf1 OUT32K Fall time 80% to 20% V32K dc1 OUT32K Duty Cycle CLT = 15 pF, measured at V32K/2 tj1 Pk-Pk Period jitter 32.000 kHz output directly from oscillator (with crystal), measured at V32K/2 40 20 7.0 ns 7.0 ns 60 % 40 ns 4.0 ns 4.0 ns 60 % OUT24M AC Characteristics tr2 OUT24M Rise Time V24M = 3.3 + 5%; 20% to 80% V24M tf2 OUT24M Fall Time V24M = 3.3 + 5%; 80% to 20% V24M dc2 OUT24M Duty cycle V24M = 3.3 + 5%; measured at V24M/2 tj2 RMS Period Jitter (CY2040-2, PLL output) V24M = V32K = 3.3 + 5%; 32 kHz as input to PLL; measured at V24M/2 40 ps RMS Period Jitter (CY2040-3, osc. output) V24M = V32K = 3.3 + 5%; 24 MHz output directly from oscillator; measured at V24M/2 40 ps RMS Long-term Jitter (CY2040-2, PLL output) V24M = V32K = 3.3 + 5%; 32 kHz as input to PLL; measured at V24M/2 on the 750th output rising edge. 1.5 ns tj3 40 OUT32KPLL AC Characteristics tr3 OUT32KPLL Rise Time V24M = 3.3 + 5%; 20% to 80% V24M 7.0 ns tf3 OUT32KPLL Fall Time V24M = 3.3 + 5%; 80% to 20% V24M 7.0 ns dc3 OUT32KPLL Duty cycle V24M = 3.3 + 5%; measured at V24M/2 60 % tj4 Pk-Pk Period Jitter (32 kHz osc. output) 32.000 kHz output directly from oscillator, measured at V24M/2 40 ns 3 sec T/2 T+25 ns 40 20 Other AC Characteristics tstart Osc start up time From power on (V32K = 3.3 + 5%). Decided by 32.768 kHz/32.000 kHz crystal startup. tPD Power down delay time on OUT24M; SYNC PD24M# pin high to low (T = OUT24M clock period) tPU Power up time on OUT24M; ASYNC (CY2040-2) From power down mode; PD24M# pin low to high. 1 5 ms Power up time on OUT24M; ASYNC (CY2040-3) From power down mode; PD24M# pin low to high. Decided by 24 MHz crystal start-up. 6 10 ms Document #: 38-07122 Rev. *A Page 4 of 7 CY2040-2/3 Switching Waveforms Duty Cycle Timing (dc1, dc2, dc3) t1A OUTPUT t1B Output Rise/Fall Time VDD OUTPUT 0V tf tr Power Down and Power up Timing (synchronous modes) VDD POWER DOWN/UP VIL 0V VIH tPU High Impedance CLKOUT (synchronous) T tPD 1/f Crystal Start-up Timing VDD CRYSTAL START-UP 0V VDD – 10% tstart min. 30us max. 30ms CLKOUT 1/f Document #: 38-07122 Rev. *A Page 5 of 7 CY2040-2/3 Application Circuits CY2040-3 CY2040-2 1 NC Note 2 Vdd 2 32KPLLEN 3 PD24M# 4 V32K 0.1uF 5 V24M Vss 16 Note 2 out24M 15 Out32K 13 2 32KPLLEN GND Vdd Out32KPLL 14 CY2040-3 6 Xin32K 32.768KHz Crystal 1 NC Vss 16 24.000MHz Crystal Xout24M 12 4 V32K 0.1uF Xin24M 11 7 Xout32K Vss 10 8 NC NC 9 3 PD24M# 5 V24M GND GND Out32KPLL 14 Out32K 13 CY2040-2 6 Xin32K 32.000kHz Crystal out24M 15 Xout24M 12 Xin24M 11 7 Xout32K Vss 10 8 NC NC 9 GND Note: 2. To disable the OUT32KPLL output, the 32KPLLEN pin should be connected to GND. To enable the OUT32KPLL output, the 32KPLLEN pin should be connected to VDD. Ordering Code Package Name Package Type Operating Range CY2040ZC-2 Z16 16LD TSSOP 0–70°C CY2040ZC-3 Z16 16LD TSSOP 0–70°C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07122 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2040-2/3 Document Title: CY2040-2/3 32 kHz and 24 MHz Clock Generator with Precision 32 kHz Input Document Number: 38-07122 REV. ECN NO. Issue Date Orig. of Change ** 109574 01/17/02 CKN New Data Sheet *A 121821 12/14/02 RBI Power up requirements added to Operating Conditions Information Document #: 38-07122 Rev. *A Description of Change Page 7 of 7