CAT5112 32-Tap Digitally Programmable Potentiometer (DPP™) with Buffered Wiper FEATURES DESCRIPTION 32-position linear taper potentiometer The CAT5112 is a single digitally programmable potentiometer (DPP™) designed as a electronic replacement for mechanical potentiometers. Ideal for automated adjustments on high volume production lines, they are also well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. Non-volatile EEPROM wiper storage; buffered wiper Low power CMOS technology Single supply operation: 2.5 V - 6.0 V Increment up/down serial interface Resistance values: 10 kΩ, 50 kΩ and 100 kΩ The CAT5112 contains a 32-tap series resistor array connected between two terminals RH and RL. An up/down counter and decoder that are controlled by three input pins, determines which tap is connected to the wiper, RWB. The CAT5112 wiper is buffered by an op amp that operates rail to rail. The wiper setting, stored in non-volatile memory, is not lost when the device is powered down and is automatically recalled when power is returned. The wiper can be adjusted to test new system values without effecting the stored setting. Wiper-control of the CAT5112 is accompli¯¯ , U/D ¯ , and INC ¯¯¯. shed with three input control pins, CS ¯¯¯ The INC input increments the wiper in the direction ¯ input. which is determined by the logic state of the U/D ¯¯ The CS input is used to select the device and also store the wiper position prior to power down. Available in PDIP, SOIC, TSSOP and MSOP packages APPLICATIONS Automated product calibration Remote control adjustments Offset, gain and zero control Tamper-proof calibrations Contrast, brightness and volume controls Motor controls and feedback systems Programmable analog functions The digitally programmable potentiometer can be used as a buffered voltage divider. For applications where the potentiometer is used as a 2-terminal variable resistor, please refer to the CAT5114. The buffered wiper of the CAT5112 is not compatible with that application. For Ordering Information details, see page 10. FUNCTIONAL DIAGRAM RH VCC RH U/D INC Control and Memory CS Power On Recall + + RWB – – RWB RL RL GND © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice Electronic Potentiometer Implementation 1 Doc. No. MD-2002 Rev. O CAT5112 PIN CONFIGURATION PDIP 8-Lead (L) SOIC 8 Lead (V) MSOP 8 Lead (Z) PIN DESCRIPTIONS Name Function TSSOP 8 Lead (Y) ¯¯¯ 1 INC 8 VCC ¯¯ 1 CS 8 RL ¯ 2 U/D ¯¯ 7 CS VCC 2 7 RWB 6 RL ¯¯¯ 3 INC 5 RWB ¯ 4 U/D RH 3 CAT GND 4 CAT ¯¯¯ INC ¯ U/D Increment Control RH Potentiometer High Terminal Up/Down Control GND Ground 6 GND RWB 5 RH Buffered Wiper Terminal RL Potentiometer Low Terminal ¯¯ CS Chip Select VCC Supply Voltage PIN DESCRIPTION ¯¯¯ and U/D ¯ inputs will not high state, activity on the INC affect or change the position of the wiper. ¯¯¯ : Increment Control Input INC ¯¯¯ input (on the falling edge) moves the wiper in The INC the up or down direction determined by the condition ¯ input. of the U/D DEVICE OPERATION The CAT5112 operates like a digitally controlled potentiometer with RH and RL equivalent to the high and low terminals and RWB equivalent to the mecha– nical potentiometer's wiper. There are 32 available tap positions including the resistor end points, RH and RL. There are 31 resistor elements connected in series between the RH and RL terminals. The wiper terminal is connected to one of the 32 taps and controlled by ¯¯¯, U/D ¯ and CS ¯¯ . These inputs control a three inputs, INC five-bit up/down counter whose output is decoded to select the wiper position. The selected wiper position can be stored in nonvolatile memory using the INC ¯¯ inputs. and CS ¯ : Up/Down Control Input U/D ¯ input controls the direction of the wiper The U/D ¯¯ is low, any movement. When in a high state and CS ¯¯¯ will cause the wiper to high-to-low transition on INC move one increment toward the RH terminal. When in ¯¯ is low, any high-to-low transition a low state and CS ¯¯¯ will cause the wiper to move one increment on INC towards the RL terminal. RH: High End Potentiometer Terminal RH is the high end terminal of the potentiometer. It is not required that this terminal be connected to a potential greater than the RL terminal. Voltage applied to the RH terminal cannot exceed the supply voltage, VCC or go below ground, GND. ¯¯ set LOW the CAT5112 is selected and will With CS ¯ and INC ¯¯¯ inputs. HIGH to LOW respond to the U/D ¯¯¯ wil increment or decrement the transitions on INC ¯ input and wiper (depending on the state of the U/D five-bit counter). The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The value of the ¯¯ counter is stored in nonvolatile memory whenever CS ¯¯¯ input is also HIGH. transitions HIGH while the INC When the CAT5112 is powered-down, the last stored wiper counter position is maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the counter is set to the value stored. RWB: Wiper Potentiometer Terminal (Buffered) RWB is the buffered wiper terminal of the potentio– meter. Its position on the resistor array is controlled by ¯¯¯, U/D ¯ and CS ¯¯ . the control inputs, INC RL: Low End Potentiometer Terminal RL is the low end terminal of the potentiometer. It is not required that this terminal be connected to a potential less than the RH terminal. Voltage applied to the RL terminal cannot exceed the supply voltage, VCC or go below ground, GND. RL and RH are electrically interchangeable. ¯¯¯ set low, the CAT5112 may be deselected With INC and powered down without storing the current wiper position in nonvolatile memory. This allows the system to always power up to a preset value stored in nonvolatile memory. ¯¯ : Chip Select CS The chip select input is used to activate the control input of the CAT5112 and is active low. When in a Doc. No. MD-2002 Rev. O 2 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5112 OPERATION MODES RH ¯¯¯ INC ¯¯ CS ¯ U/D Operation High to Low Low High Wiper toward RH High to Low Low Low Wiper toward RL High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby CH RWI RWB CW CL Potentiometer Equivalent Circuit RL ABSOLUTE MAXIMUM RATINGS(1) Parameters Supply Voltage VCC to GND Inputs ¯¯ to GND CS ¯¯¯ to GND INC ¯ to GND U/D RH to GND RL to GND RWB to GND Ratings Units -0.5 to +7 V -0.5 to VCC +0.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -0.5 to VCC +0.5 V V V V V V Parameters Operating Ambient Temperature Commercial (‘C’ or Blank suffix) Industrial (‘I’ suffix) Junction Temperature Storage Temperature Lead Soldering (10s max) Ratings Units 0 to 70 -40 to +85 +150 -65 to 150 +300 ºC ºC ºC ºC ºC Max Units RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min VZAP(2) ILTH(2) (3) Typ ESD Susceptibility MIL-STD-883, Test Method 3015 2000 V Latch-Up JEDEC Standard 17 100 mA TDR Data Retention MIL-STD-883, Test Method 1008 100 Years NEND Endurance MIL-STD-883, Test Method 1003 1,000,000 Stores DC ELECTRICAL CHARACTERISTICS VCC = +2.5 V to +6 V unless otherwise specified Power Supply Symbol Parameter VCC Operating Voltage Range ICC1 Supply Current (Increment) ICC2 Supply Current (Write) ISB1(3) Supply Current (Standby) Conditions Min Typ Max Units 2.5 – 6 V VCC = 6 V, f = 1 MHz, IW = 0 – – 200 µA VCC = 6 V, f = 250 kHz, IW = 0 – – 100 µA Programming, VCC = 6 V – – 1000 µA VCC = 3 V ¯¯ = VCC - 0.3 V CS ¯ , INC ¯¯¯ = VCC - 0.3 V or GND U/D – – 500 µA – 75 150 µA Notes: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) Latch-up protection is provided for stresses up to 100mA on address and data pins from -1 V to VCC + 1 V (4) IW = source or sink (5) These parameters are periodically sampled and are not 100% tested. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 3 Doc. No. MD-2002 Rev. O CAT5112 Logic Inputs Symbol Parameter Conditions IIH Input Leakage Current IIL Input Leakage Current VIH1 TTL High Level Input Voltage VIL1 TTL Low Level Input Voltage VIH2 CMOS High Level Input Voltage VIL2 CMOS Low Level Input Voltage Min Typ VIN = VCC – – 10 µA VIN = 0 V – – -10 µA 2 – VCC V 0 – 0.8 V VCC x 0.7 – VCC + 0.3 V -0.3 – VCC x 0.2 V 4.5 V ≤ VCC ≤ 5.5 V 2.5 V ≤ VCC ≤ 6 V Max Units Potentiometer Characteristics Symbol RPOT Parameter Potentiometer Resistance Conditions Min Typ -10 Device 10 -50 Device 50 -00 Device 100 Pot. Resistance Tolerance Max Units kΩ ±20 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 1 % INL Integral Linearity Error IW ≤ 2 µA 0.5 1 LSB DNL Differential Linearity Error IW ≤ 2 µA 0.25 0.5 LSB ROUT Buffer Output Resistance 0.05VCC ≤ VWB ≤ 0.95VCC, VCC = 5 V 1 Ω IOUT Buffer Output Current 0.05VCC ≤ VWB ≤ 0.95VCC, VCC = 5 V 3 mA TCRPOT TC of Pot Resistance 300 ppm/ºC TCRATIO Ratiometric TC 20 ppm/ºC 8/8/25 pF 1.7 MHz CRH/CRL/CRW Potentiometer Capacitances fc Frequency Response Passive Attenuator, 10kΩ VWB(SWING) Output Voltage Range IOUT ≤ 100 µA, VCC = 5 V Doc. No. MD-2002 Rev. O 4 0.01VCC 0.99VCC © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5112 AC CONDITIONS OF TEST VCC Range 2.5V ≤ VCC ≤ 6V Input Pulse Levels 0.2VCC to 0.7VCC Input Rise and Fall Times 10 ns Input Reference Levels 0.5VCC AC OPERATING CHARACTERISTICS VCC = +2.5 V to +6.0 V, VH = VCC, VL = 0 V, unless otherwise specified Symbol tCI tDI tID tIL tIH tIC tCPH tCPH tIW tCYC (2) tR, tF tPU (2) tWR Parameter Min Typ(1) Max Units ¯¯ to INC ¯¯¯ Setup CS ¯ to INC ¯¯¯ Setup U/D 100 – – ns 50 – – ns ¯ to INC ¯¯¯ Hold U/D ¯¯¯ LOW Period INC 100 – – ns 250 – – ns ¯¯¯ HIGH Period INC ¯¯¯ Inactive to CS ¯¯ Inactive INC 250 – – ns 1 – – µs ¯¯ Deselect Time (NO STORE) CS ¯¯ Deselect Time (STORE) CS 100 – – ns 10 – – ms ¯¯¯ to VOUT Change INC ¯¯¯ Cycle Time INC – 1 5 µs 1 – – µs ¯¯¯ Input Rise and Fall Time INC – – 500 µs Power-up to Wiper Stable – – 1 ms Store Cycle – 5 10 ms A.C. TIMING CS tCYC tCI tIL tIC tIH (store) tCPH 90% INC 90% 10% tDI tID tF tR U /D tIW MI(3) RWB Notes: (1) (2) (3) Typical values are for TA = 25ºC and nominal supply voltage. This parameter is periodically sampled and not 100% tested. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 5 Doc. No. MD-2002 Rev. O CAT5112 PACKAGE OUTLINE DRAWINGS PDIP 8-Lead 300 mil (L) (1)(2) SYMBOL MIN NOM A E1 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 e PIN # 1 IDENTIFICATION MAX 2.54 BSC E1 6.10 eB 7.87 L 2.92 6.35 7.11 10.92 3.30 3.80 D TOP VIEW E A2 A A1 c b2 L e eB b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC Specification MS-001. Doc. No. MD-2002 Rev. O 6 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5112 SOIC 8-LEAD Narrow Body (150 mil) (V) (1)(2) SYMBOL E1 E MIN MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 D 4.80 5.00 E 5.80 6.20 E1 3.80 e PIN # 1 IDENTIFICATION NOM 4.00 1.27 BSC h 0.25 0.50 L 0.40 1.27 θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC Specification MS-012. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 7 Doc. No. MD-2002 Rev. O CAT5112 TSSOP 8-Lead (Y) (1)(2) b SYMBOL MIN NOM A E1 E MAX 1.20 A1 0.05 A2 0.80 b 0.19 c 0.09 D 2.90 0.15 0.90 1.05 0.30 0.20 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 θ1 0° 0.60 0.75 8° e TOP VIEW D A2 A1 A c θ1 L1 L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC Standard MO-153 Doc. No. MD-2002 Rev. O 8 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5112 MSOP 8-Lead (Z) (1)(2) SYMBOL MIN NOM MAX A1 0.05 0.10 A2 0.75 0.85 b 0.22 0.38 c 0.13 0.23 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 A E E1 1.10 e L 0.15 0.95 0.65 BSC 0.40 0.60 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW θ L2 L L1 DETAIL A Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC Specification MS-187. © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice 9 Doc. No. MD-2002 Rev. O CAT5112 EXAMPLE OF ORDERING INFORMATION Prefix Device # CAT (1) Suffix 5112 V Optional Company ID I -10 – Temperature Range I = Industrial (-40ºC to 85ºC) Product Number 5112 T3 Tape & Reel T: Tape & Reel 3: 3000/Reel Resistance -10: 10 kΩ -50: 50 kΩ -00: 100 kΩ Package L: PDIP V: SOIC Y: TSSOP Z: MSOP G(4) Lead Finish Blank: Matte-Tin G: NiPdAu ORDERING INFORMATION Orderable Part Number Resistance (kΩ) CAT5112LI-10-G 10 CAT5112LI-50-G 50 CAT5112LI-00-G 100 CAT5112VI-10-GT3 10 CAT5112VI-50-GT3 50 CAT5112VI-00-GT3 100 CAT5112YI-10-GT3 10 CAT5112YI-50-GT3 50 CAT5112YI-00-GT3 100 CAT5112ZI-10-GT3 10 CAT5112ZI-50-GT3 50 CAT5112ZI-00-GT3 100 Package-Pins Lead Finish (4) PDIP-8 SOIC-8 NiPdAu TSSOP-8 MSOP-8 Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) This device used in the above example is a CAT5112VI-10-GT3 (SOIC, Industrial Temperature, 10 kΩ, NiPdAu, Tape & Reel). (4) For Matte-Tin finish, contact factory. Doc. No. MD-2002 Rev. O 10 © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice CAT5112 REVISION HISTORY Date 10-Mar-07 29-Mar-04 12-Apr-04 Rev. J K L 04-Jun-07 M 20-Nov-08 N 10-Jul-09 O Description Updated Potentiometer Parameters Change Green Package marking for SOIC from W to V Update Reel Ordering Information Add Package Outline Drawings Update Example of Ordering Information Add MD- to the Document Number Update Package Outline Drawings Change logo and fine print to ON Semiconductor Update Ordering Information table ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: [email protected] © 2009 SCILLC. All rights reserved. Characteristics subject to change without notice N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center: Phone: 81-3-5773-3850 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative Doc. No. MD-2002 Rev. O