H CAT524 EE GEN FR ALO Configured Digitally Programmable Potentiometer (DPP™): Programmable Voltage Applications LE A D F R E ETM FEATURES ■ Single supply operation: 2.7V - 5.5V ■ Four 8-bit DPPs configured as programmable ■ Setting read-back without effecting outputs voltage sources in DAC-like applications ■ Common reference inputs ■ Buffered wiper outputs APPLICATIONS ■ Non-volatile NVRAM memory wiper storage ■ Automated product calibration ■ Output voltage range includes both supply rails ■ Remote control adjustment of equipment ■ 4 independently addressable buffered ■ Offset, gain and zero adjustments in self-calibrating and adaptive control systems output wipers ■ 1 LSB accuracy, high resolution ■ Tamper-proof calibrations ■ Serial Microwire-like interface ■ DAC (with memory) substitute DESCRIPTION The CAT524 is a quad, 8-bit digitally-programmable potentiometer (DPP™) configured for programmable voltage and DAC-like applications. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for self-calibrating systems and for applications where equipment which requires periodic adjustment is either difficult to access or in a hazardous environment. effecting the stored settings, and stored settings can be read back without disturbing the DPP’s output. The CAT524 is controlled with a simple 3-wire serial, Microwire-like interface. A Chip Select pin allows several devices to share a common serial interface. Communication back to the host controller is via a single serial data line thanks to the Tri-Stated CAT524 Data Output pin. A RDY/BSY output working in concert with an internal low voltage detector signals proper operation of the non-volatile NVRAM memory Erase/Write cycle. The four independently programmable DPPs have an output range which includes both supply rails. The wipers are buffered by rail to rail op amps. Wiper settings, stored in non-volatile NVRAM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each wiper can be dithered to test new output values without The CAT524 is available in the 0˚C to 70˚C commercial and -40˚C to 85˚C industrial operating temperature ranges. Both 14-pin plastic DIP and SOIC packages are offered. FUNCTIONAL DIAGRAM RDY/BSY 3 V DD 1 PIN CONFIGURATION V REFH 14 DIP Package (P, L) 24kΩ(4) PROG 7 PROGRAM CONTROL + 13 – DI CLK CS 5 2 + SERIAL CONTROL 12 – WIPER CONTROL REGISTERS AND NVRAM V OUT1 V OUT2 VDD 1 14 CLK 2 13 RDY/BSY 3 CS + 11 – 4 DI DO V OUT3 PROG + 10 – SERIAL DATA OUTPUT REGISTER SOIC Package (J, W) 12 CAT 4 11 524 5 10 6 9 7 8 VREFH VOUT1 VDD CLK 1 14 2 13 VREFH VOUT1 VOUT2 VOUT3 RDY/BSY 3 VOUT4 VREFL DI DO 12 4 CAT 11 524 5 10 6 9 VOUT2 VOUT3 VOUT4 VREFL 7 GND GND CS PROG 8 VOUT4 6 DO CAT524 9 8 GND V REFL © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 2006, Rev. E CAT524 Operating Ambient Temperature Commercial (‘C’ or Blank suffix) 0°C to +70°C Industrial (‘I’ suffix) -40°C to +85°C Junction Temperature +150°C Storage Temperature -65°C to +150°C Lead Soldering (10 sec max) +300°C ABSOLUTE MAXIMUM RATINGS Supply Voltage* VDD to GND Inputs CLK to GND CS to GND DI to GND RDY/BSY to GND PROG to GND VREFH to GND VREFL to GND Outputs D0 to GND VOUT 1– 4 to GND -0.5V to +7V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V -0.5V to VDD +0.5V * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time. -0.5V to VDD +0.5V -0.5V to VDD +0.5V RELIABILITY CHARACTERISTICS Symbol Parameter Min VZAP(1) ILTH(1)(2) ESD Susceptibility Latch-Up 2000 100 Max Units Test Method Volts mA MIL-STD-883, Test Method 3015 JEDEC Standard 17 NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V. POWER SUPPLY Symbol Parameter Conditions IDD1 Supply Current (Read) IDD2 Supply Current (Write) VDD Min Typ Max Units Normal Operating — 400 600 µA Programming, VDD = 5V — 1600 2500 µA VDD = 3V — 1000 1600 µA 2.7 — 5.5 V Min Typ Max Units Operating Voltage Range LOGIC INPUTS Symbol Parameter Conditions IIH Input Leakage Current VIN = VDD — — 10 µA IIL Input Leakage Current VIN = 0V — — -10 µA VIH High Level Input Voltage 2 — VDD V VIL Low Level Input Voltage 0 — 0.8 V Min Typ Max Units VDD -0.3 — — V LOGIC OUTPUTS Symbol Parameter Conditions VOH High Level Output Voltage IOH = -40µA VIL Low Level Output Voltage IOL = 1 mA, VDD = +5V — — 0.4 V IOL = 0.4 mA, VDD = +3V — — 0.4 V Doc. No. 2006, Rev. E 2 CAT524 POTENTIOMETER CHARACTERISTICS VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions RPOT Potentiometer Resistance See Note 3 Min Typ Max Units 24 RPOT to RPOT Match — +0.5 Pot Resistance Tolerance kΩ +1 % +20 % Voltage on VREFH pin 2.7 VDD V Voltage on VREFL pin 0V VDD - 2.7 V Resolution 0.4 % INL Integral Linearity Error 0.5 1 LSB DNL Differential Linearity Error 0.25 0.5 LSB ROUT Buffer Output Resistance 10 Ω IOUT Buffer Output Current 3 mA TCRPOT TC of Pot Resistance 300 ppm/˚C CH/CL Potentiometer Capacitances 8/8 pF AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units 150 100 0 50 50 — — — — — 150 700 500 300 DC — — — — — — — 400 400 4 — — — — — — — — — — 150 150 — — 5 — — — — 1 ns ns ns ns ns ns ns ns ns ms ns ns ns ns MHz — — 3 6 10 10 µs µs Digital tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tBUSY tPS tPROG tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Cycle Time PROG Setup Time Minimum Pulse Width Minimum CLK High Time Minimum CLK Low Time Clock Frequency CL=100pF, see note 1 Analog tDS DPP Settling Time to 1 LSB CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. 3. The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ +20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value. 3 Doc. No. 2006, Rev. E Doc. No. 2006, Rev. E 4 RDY/BSY PROG DO DI CS CLK to to t LZ t DIS t CSS 1 1 t DO1 t DIH 2 2 t CLK H 3 t PROG t PS t CLK L 3 t DO0 4 t BUSY t CSH 4 t HZ t CSMIN 5 5 FROM TIMING TO Rising PROG edge to next rising CLK edge Falling CS edge to D0 becoming high impedance (Tri-State) t BUSY Falling CLK edge after PROG=H to rising RDY/BSY edge t PROG Rising PROG edge to falling PROG edge t PS t HZ Rising CLK edge to D0 = high Rising CS edge to D0 becoming high low impedance (active output) t LZ t DO1 Rising CLK edge to D0 = low Rising CLK edge to end of data valid t DO0 t DIH Max Min Min (Max) Max (Max) Max Min Min Data valid to first rising CLK edge after CS = high t DIS Min Min Rising CS edge to next rising CLK edge t CSMIN Falling CS edge to rising CS edge t CSS Min t CSH Falling CLK edge for last data bit (DI) to falling CS edge Min Min MIN/MAX t CLK L Falling CLK edge to CLK rising edge t CLK H Rising CLK edge to falling CLK edge PARAM NAME CAT524 A. C. TIMING DIAGRAM CAT524 PIN DESCRIPTION Pin Name 1 2 3 4 5 6 7 VDD CLK RDY/BSY CS DI DO PROG 8 9 10 11 12 13 14 GND VREFL VOUT4 VOUT3 VOUT2 VOUT1 VREFH DPP addressing is as follows: Function Power supply positive. Clock input pin.Clock input pin. Ready/Busy Output Chip Select Serial data input pin. Serial data output pin. Non-volatile Memory Programming Enable Input Power supply ground. Minimum DPP output voltage. DPP output channel 4. DPP output channel 3. DPP output channel 2. DPP output channel 1. Maximum DPP output voltage. DEVICE OPERATION DPP OUTPUT A0 A1 VOUT1 0 0 VOUT2 1 0 VOUT3 0 1 VOUT4 1 1 read and write operations. When CS is high data may be read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DPP control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DPP outputs to the settings stored in nonvolatile memory and switches DO to its high impedance Tri-State mode. The CAT524 is a quad 8-bit configured digitally programmable potentiometer (DPP) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile memory and will not be lost when power is removed from the chip. Upon power up the DPPs return to the settings stored in non-volatile memory. Each DPP can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT524’s clock controls both data flow in and out of the IC and non-volatile memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock’s rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to non-volatile memory, even though the data being saved may already be resident in the DPP wiper control register. DIGITAL INTERFACE The CAT524 employs a 3 wire serial, Microwire-like control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic “1” as a start bit. The DPP address and data are clocked into the DI pin on the clock’s rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. No clock is necessary upon system power-up. The CAT524’s internal power-on reset circuitry loads data from non-volatile memory to the DPPs without using the external clock. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit. CHIP SELECT Chip Select (CS) enables and disables the CAT524’s 5 Doc. No. 2006, Rev. E CAT524 VREF (CS) and Program (PROG). With CS high, a start bit followed by a two bit DPP address and eight data bits are clocked into the DPP control register via the DI pin. Data enters on the clock’s rising edge. The DPP output changes to its new setting on the clock cycle following D7, the last data bit. VREF, the voltage applied between pins VREFH andVREFL, sets the configured DPP’s Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH andVREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. Programming is achieved by bringing PROG high for a minimum of 3 ms. PROG must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DPP wiper control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the non-volatile cells. The CAT524 non-volatile memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. /BUSY READY/BUSY When saving data to non-volatile memory, the Ready/ Busy ouput (RDY/BSY) signals the start and duration of the non-volatile erase/write cycle. Upon receiving a command to store data (PROG goes high) RDY/BSY goes low and remains low until the programming cycle is complete. During this time the CAT524 will ignore any data appearing at DI and no data will be output on DO. RDY/BSY is internally ANDed with a low voltage detector circuit monitoring VDD. If VDD is below the minimum value required for non-volatile programming, RDY/BSY will remain high following the program command indicating a failure to record the desired data in non-volatile memory. READING DATA Each time data is transferred into a DPP wiper control register currently held data is shifted out via the D0 pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DPP’s output. This feature allows µPs to poll DPPs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in non-volatile memory so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the non-volatile memory setting is reloaded into the DPP wiper control register. DATA OUTPUT Data is output serially by the CAT524, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 524s to share a single serial data line and simplifies interfacing multiple 524s to a microprocessor. WRITING TO MEMORY Programming the CAT524’s non-volatile memory is accomplished through the control signals: Chip Select Figure 1. Writing to Memory to 1 2 3 4 5 6 7 8 9 10 Figure 2. Reading from Memory 11 12 N to N+1 N+2 1 2 3 4 5 6 7 8 9 10 11 12 CS CS NEW DPP DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 DI D6 D7 DO 1 A0 A1 CURRENT DPP DATA CURRENT DPP DATA DO D0 D1 D2 D3 D4 D5 D1 D2 D3 D4 D5 PROG PROG DPP OUTPUT D0 CURRENT DPP VALUE NON-VOLATILE Doc. No. 2006, Rev. E NEW DPP VALUE VOLATILE NEW DPP VALUE NON-VOLATILE DPP OUTPUT CURRENT DPP VALUE NON-VOLATILE 6 D6 D7 CAT524 Since this value is the same as that which had been there previously no change in the DPP’s output is noticed. Had the value held in the control register been different from that stored in non-volatile memory then a change would occur at the read cycle’s conclusion. this feature, the new value must be reloaded into the DPP control register prior to programming. This is because the CAT524’s internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. TEMPORARILY CHANGE OUTPUT Figure 3. Temporary Change in Output The CAT524 allows temporary changes in DPP’s output to be made without disturbing the settings retained in non-volatile memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2 CS NEW DPP DATA 1 DI Figure 3 shows the control and data signals needed to effect a temporary output change. DPP wiper settings may be changed as many times as required and can be made to any of the four DPPs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DPPs will return to the output values stored in non-volatile memory. A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 CURRENT DPP DATA D0 DO D1 D2 D3 D4 D5 D6 D7 PROG CURRENT DPP VALUE NON-VOLATILE DPP OUTPUT NEW DPP VALUE VOLATILE CURRENT DPP VALUE NON-VOLATILE When it is desired to save a new setting acquired using APPLICATION CIRCUITS DPP INPUT DPP OUTPUT ANALOG OUTPUT +5V CODE (V - V VDPP = ——— FS ZERO ) + V ZERO 255 MSB 1111 LSB 1111 1000 0000 0111 1111 0000 0001 0000 0000 Ri Vi VFS = 0.99 VREF VZERO = 0.01 V REF VREF = 5V R I = RF 255 (.98 V —— REF) + .01 VREF = .990 V REF 255 +15V VDD V OUT= +4.90V 128 (.98 V —— ) + .01 V = .502 V REF REF REF 255 127 —— (.98 V ) + .01 V = .498 V 255 REF REF REF 1 (.98 V —— ) + .01 V = .014 V 255 REF REF REF V 0 (.98 V —— ) + .01 V = .010 V REF REF REF 255 V V V OUT OUT OUT OUT RF CONTROL & DATA VREFH + CAT524 = +0.02V GND VOUT – OP 07 -15V VREFL = -0.02V VDPP (Ri+ RF ) -Vi R F Ri = -4.86V VOUT = = -4.90V For R i = RF VOUT = 2VDPP -Vi Bipolar DPP Output +5V Ri RF +15V VDD CONTROL & DATA VREFH – CAT524 OPT 504 GND + VOUT OP 07 -15V VREFL RF VOUT = (1 + –––) V DPP RI Amplified DPP Output 7 Doc. No. 2006, Rev. E CAT524 APPLICATION CIRCUITS (Cont.) +5V VREF RC = ————— 256 * 1 µA +5V VDD VREF VREFH FINE ADJUST DPP VDD Fine adjust gives ± 1 LSB change in V OFFSET VREF when V OFFSET = ——— 2 +VREF VREFH 127RC FINE ADJUST DPP + (+VREF ) - (VOFFSET ) RC = ——————————— 1 µA 127RC (-VREF ) + (VOFFSET+ ) Ro = ——————————— 1 µA RC COARSE ADJUST DPP +V COARSE ADJUST DPP RC V OFFSET GND + +V Ro VOFFSET -VREF – GND VREFL + – VREFL -V Coarse-Fine Offset Control by Averaging DPP Outputs for Single Power Supply Systems Coarse-Fine Offset Control by Averaging DPP Outputs for Dual Power Supply Systems 28 - 32V V+ I > 2 mA 15K 10 µF VDD CONTROL & DATA 1N5231B VREF = 5.000V VREFH VDD VREFH 5.1V 10K CAT524 OPT 505 GND LT 1029 CONTROL & DATA CAT514 CAT524 GND VREFL VREFL + – MPT3055EL LM 324 OUTPUT 4.02 K 1.00K Digitally Trimmed Voltage Reference Doc. No. 2006, Rev. E Digitally Controlled Voltage Reference 8 10 µF 35V 0 - 25V @ 1A CAT524 APPLICATION CIRCUITS (Cont.) +5V VIN VREF 1.0 µF LM 339 + 10K – VDD +5V VREFH WINDOW 1 + CAT524 VREF – WINDOW 1 DPP 1 + – 10K +5V WINDOW 2 VOUT1 + CS WINDOW 2 – + DPP 2 DI VOUT2 10K – +5V WINDOW 3 WINDOW 3 + DO – DPP 3 PROG VOUT3 + – WINDOW 4 10K +5V WINDOW 4 VOUT4 + CLK – DPP 4 WINDOW 5 + GND 10K – +5V WINDOW 5 + VREFL GND WINDOW STRUCTURE – Staircase Window Comparator +5V VIN VREF 1.0 F + LM 339 10K – VDD VREFH CAT524 +5V WINDOW 1 + VREF – WINDOW 1 DPP 1 + – 10K +5V WINDOW 2 VOUT1 + CS DI WINDOW 2 – VOUT2 + DPP 2 10K – +5V WINDOW 3 WINDOW 3 + DO PROG – DPP 3 VOUT3 + – WINDOW 4 10K +5V WINDOW 4 VOUT4 + CLK – DPP 4 WINDOW 5 + GND 10K – +5V WINDOW 5 + GND VREFL WINDOW STRUCTURE – Overlapping Window Comparator 9 Doc. No. 2006, Rev. E CAT524 APPLICATION CIRCUITS (Cont.) +5V 2.2K VDD VREFH 4.7 uF LM385-2.5 ISINK = 2 - 255 mA +15V + DPP +5V CONTROL & DATA 10K CAT524 1 mA steps 2N7000 – 39 Ω 1W 10K 39 Ω 1W + DPP 5 µA steps 2N7000 – VREFL GND 5M 5M 3.9K 10K 10K – TIP 30 + Current Sink with 4 Decades of Resolution -15V +15V 51K + TIP 29 – 10K 10K +5V VDD VREFH 5M 5M 39 Ω 1W DPP 39 Ω 1W CONTROL & DATA – CAT524 BS170P + 5M 5M 1 mA steps 3.9K DPP GND – VREFL BS170P 5 µA steps + LM385-2.5 -15V ISOURCE = 2 - 255 mA Current Source with 4 Decades of Resolution Doc. No. 2006, Rev. E 10 CAT524 APPLICATION CIRCUITS (Cont.) +12V 10K 1N914 1.0 µF +12V .005 µF 74C14 VCC 1N914 13 0.1 µF 2.5 µF TREB CAP 0.47 µF 2 INPUT 1 IN 1 BASS CAP 4 0.01 µF 8 0.39 µF 20V IN5250B 3 Vpp VDD CAT524 OPT 504 CHIP SELECT. PROGRAM DATA IN DATA OUT CLOCK 4 7 5 6 2 VREFH 14 DI DO CLK VOUT1 VOUT2 VOUT3 VOUT4 VREFL GND 13 12 11 10 VZ OUTPUT 1 10 OUT 1 LM1040 1.0 µF 9 CS PROG 19 1 47K 14 47K 11 47K 5 47K 16 0.22 µF 0.22 µF 0.22 µF 0.22 µF LOUDNESS VOLUME BALANCE TREBLE BYPASS BASS 1 47 µF 7 10 µF 18 10 µF 9 8 OUTPUT 2 0.47 µF 23 INPUT 2 3 IN 2 BASS CAP STEREO TREB CAP 15 17 22 ENHANCE 4.7K GND GND 0.39 µF 21 24 0.1 µF OUT 2 0.01 µF 12 Digital Stereo Control 11 Doc. No. 2006, Rev. E CAT524 ORDERING INFORMATION Prefix Device # Suffix CAT 524 J Optional Company ID Product Number I Package P: PDIP J: SOIC L: PDIP (Lead free, Halogen free) W: SOIC (Lead free, Halogen free) Temperature Range Blank = Commercial (0˚C to +70˚C) I = Industrial (-40˚C to +85˚C) Notes: (1) The device used in the above example is a CAT524JI-TE13 (SOIC, Industrial Temperature, Tape & Reel) Doc. No. 2006, Rev. E 12 -TE13 Tape & Reel TE13: 2000/Reel CAT524 REVISION HISTORY Date Rev. Reason 3/16/2004 D Updated Potentiometer Characteristics 7/12/2004 E Updated Functional Diagram Updated Potentiometer Characteristics Added Note 3 to Potentiometer/AC characteristics tables Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com Publication #: Revison: Issue date: Type: 13 2006 E 7/12/04 Final Doc. No. 2006, Rev. E