CYPRESS CY7C1303BV25_12

CY7C1303BV25
18-Mbit Burst of Two-Pipelined SRAM
with QDR® Architecture
18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture
Features
Functional Description
■
Separate independent read and write data ports
❐ Supports concurrent transactions
■
167 MHz clock for high bandwidth
❐ 2.5 ns clock-to-valid access time
■
Two word burst on all accesses
■
Double data rate (DDR) interfaces on both read and write ports
(data transferred at 333 MHz) at 167 MHz
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches.
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
2.5 V core power supply with HSTL inputs and outputs
■
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
The CY7C1303BV25 is 2.5 V synchronous pipelined SRAM
equipped with QDR® architecture. QDR architecture consists of
two separate ports to access the memory array. The read port
has dedicated data outputs to support read operations and the
write port has dedicated data inputs to support write operations.
Access to each port is accomplished through a common address
bus. The Read address is latched on the rising edge of the K
clock and the Write address is latched on the rising edge of K
clock. QDR has separate data inputs and data outputs to
completely eliminate the need to “turn around” the data bus
required with common I/O devices. Accesses to the
CY7C1303BV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock (K).
In order to maximize data throughput, both Read and Write ports
are equipped with Double Data Rate (DDR) interfaces.
Therefore, data can be transferred into the device on every rising
edge of both input clocks (K and K) and out of the device on every
rising edge of the output clock (C and C, or K and K when in
single clock mode) thereby maximizing performance while
simplifying system design. Each address location is associated
with two 18-bit words (CY7C1303BV25) that burst sequentially
into or out of the device.
■
Variable drive HSTL output buffers
■
Expanded HSTL output voltage (1.4 V to 1.9 V)
■
JTAG Interface
■
Variable Impedance HSTL
Depth expansion is accomplished with a port select input for
each port. Each Port Selects allow each port to operate
independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1303BV25 – 1 M × 18
Selection Guide
CY7C1303BV25-167
Unit
Maximum operating frequency
Description
167
MHz
Maximum operating current
500
mA
Cypress Semiconductor Corporation
Document Number: 38-05627 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2012
CY7C1303BV25
Logic Block Diagram – CY7C1303BV25
D[17:0]
18
K
K
CLK
Gen.
Write
Data Reg
512 K × 18 512 K × 18
Memory
Memory
Array
Array
Read Add. Decode
19
Write Add. Decode
Address
Register
A(18:0)
Write
Data Reg
Address
Register
Control
Logic
Read Data Reg.
36
VREF
WPS
BWS0
Control
Logic
BWS1
Document Number: 38-05627 Rev. *F
18
Reg.
18
Reg. 18
Reg.
18
A(18:0)
19
RPS
C
C
18
Q[17:0]
Page 2 of 25
CY7C1303BV25
Contents
Pin Configuration ............................................................. 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
Single Clock Mode ...................................................... 6
Concurrent Transactions ............................................. 6
Depth Expansion ......................................................... 6
Programmable Impedance .......................................... 7
Application Example ........................................................ 7
Truth Table ........................................................................ 8
Write Cycle Descriptions ................................................. 8
IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 9
Disabling the JTAG Feature ........................................ 9
Test Access Port ......................................................... 9
Performing a TAP Reset ............................................. 9
TAP Registers ............................................................. 9
TAP Instruction Set ..................................................... 9
TAP Controller State Diagram ....................................... 11
TAP Controller Block Diagram ...................................... 12
TAP Electrical Characteristics ...................................... 12
TAP AC Switching Characteristics ............................... 13
TAP Timing and Test Conditions .................................. 14
Identification Register Definitions ................................ 15
Document Number: 38-05627 Rev. *F
Scan Register Sizes ....................................................... 15
Instruction Codes ........................................................... 15
Boundary Scan Order .................................................... 16
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
Neutron Soft Error Immunity ......................................... 17
Electrical Characteristics ............................................... 17
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 18
Thermal Resistance ........................................................ 18
Capacitance .................................................................... 18
AC Test Loads and Waveforms ..................................... 18
Switching Characteristics .............................................. 19
Switching Waveforms .................................................... 20
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC Solutions ..........................................................25
Page 3 of 25
CY7C1303BV25
Pin Configuration
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1303BV25 (1 M × 18)
1
2
3
Gnd/144 M NC/36 M
4
5
6
7
8
9
10
11
WPS
BWS1
K
NC
RPS
A
Gnd/72 M
NC
A
NC
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
A
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
NC
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document Number: 38-05627 Rev. *F
Page 4 of 25
CY7C1303BV25
Pin Definitions
Name
I/O
Description
D[x:0]
InputData input signals, sampled on the rising edge of K and K clocks during valid write operations.
Synchronous CY7C1303BV25 – D[17:0]
WPS
InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous Write operation is initiated. Deasserting deselects the Write port. Deselecting the Write port causes D[x:0]
to be ignored.
BWS0,
BWS1
InputByte Write Select 0 and 1- active LOW. Sampled on the rising edge of the K and K clocks during Write
Synchronous operations. Used to select which byte is written into the device during the current portion of the Write
operations.
CY7C1303BV25 - BWS0 controls D[8:0] and BWS1 controls D[17:9].]
Bytes not written remain unaltered. Deselecting a Byte Write Select causes the corresponding byte of
data to be ignored and not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active Read operations and on the
Synchronous rising edge of K for Write operations. These address inputs are multiplexed for both Read and Write
operations. Internally, the device is organized as 1 M × 18 (2 arrays each of 512 K × 18) for
CY7C1303BV25. Therefore, only 19 address inputs are needed to access the entire memory array of
CY7C1303BV25. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during Read operations or K and K when in
single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated.
CY7C1303BV25 - Q[17:0]
RPS
InputRead Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous Read operation is initiated. Deasserting causes the Read port to be deselected. When deselected, the
pending access is allowed to complete and the output drivers are automatically three-stated following
the next rising edge of the K clock. Each read access consists of a burst of two sequential 18-bit transfers.
C
Input-Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
C
Input-Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input-Clock
Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive out data
through Q[x:0] when in single clock mode.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected between
ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left unconnected.
ZQ
TDO
Output
TDO pin for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC/36M
N/A
Address expansion for 36M. This pin is not connected to the die and so can be tied to any voltage level
on CY7C1303BV25
GND/72M
Input
Address expansion for 72 M. This pin has to be tied to GND on CY7C1303BV25.
GND/144M
Input
Address expansion for 144 M. This pin has to be tied to GND on CY7C1303BV25.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
Document Number: 38-05627 Rev. *F
Page 5 of 25
CY7C1303BV25
Pin Definitions (continued)
Name
VREF
VDD
VSS
VDDQ
I/O
Description
InputReference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as
well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Functional Overview
The CY7C1303BV25 are synchronous pipelined Burst SRAM
equipped with both a Read port and a Write port. The Read port
is dedicated to Read operations and the Write port is dedicated
to Write operations. Data flows into the SRAM through the Write
port and out through the Read port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write ports, this
architecture completely eliminates the need to “turn-around” the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of two 18-bit
data transfers in the case of CY7C1303BV25, in one clock cycle.
Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timings are referenced to rising edge of output clocks
(C and C or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the output clocks (C and C, or K
and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
The following descriptions take CY7C1303BV25 as an example.
Read Operations
The CY7C1303BV25 is organized internally as 2 arrays of
512 K × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. Following
the next K clock rise the corresponding lower order 18-bit word
of data is driven onto the Q[17:0] using C as the output timing
reference. On the subsequent rising edge of C the higher order
data word is driven onto the Q[17:0]. The requested data is valid
2.5 ns from the rising edge of the output clock (C and C, or K and
K when in single clock mode, 167 MHz device).
Synchronous internal circuitry automatically three-states the
outputs following the next rising edge of the positive output clock
(C). This allows for a seamless transition between devices
without the insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched and stored into the
Document Number: 38-05627 Rev. *F
lower 18-bit Write Data register provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is stored into the Write Data register provided
BWS[1:0] are both asserted active. The 36-bits of data are then
written into the memory array at the specified location.
When deselected, the Write port ignores all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1303BV25. A
Write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS0 and BWS1 which are sampled with each set of 18-bit data
word. Asserting the appropriate Byte Write Select input during
the data portion of a write allows the data being presented to be
latched and written into the device. Deasserting the Byte Write
Select input during the data portion of a write allows the data
stored in the device for that byte to remain unaltered. This feature
can be used to simplify Read/Modify/Write operations to a Byte
Write operation.
Single Clock Mode
The CY7C1303BV25 can be used with a single clock mode. In
this mode the device recognizes only the pair of input clocks (K
and K) that control both the input and output registers. This
operation is identical to the operation if the device had zero skew
between the K/K and C/C clocks. All timing parameters remain
the same in this mode. To use this mode of operation, the user
must tie C and C HIGH at power-up.This function is a strap option
and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1303BV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user can
Read or Write to any location, regardless of the transaction on
the other port. Also, reads and writes can be started in the same
clock cycle. If the ports access the same location at the same
time, the SRAM delivers the most recent information associated
with the specified address location. This includes forwarding
data from a Write cycle that was initiated on the previous K clock
rise.
Depth Expansion
The CY7C1303BV25 has a Port Select input for each port. This
allows for easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
Page 6 of 25
CY7C1303BV25
does not affect the other port. All pending transactions (Read and
Write) are completed prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM, The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175  and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles to account for
drifts in supply voltage and temperature.
Application Example
Figure 2 shows four QDR I used in an application.
Figure 2. Application Example
Document Number: 38-05627 Rev. *F
Page 7 of 25
CY7C1303BV25
Truth Table
The truth table for CY7C1303BV25 follow. [1, 2, 3, 4, 5, 6]
Operation
K
RPS
WPS
Write cycle:
Load address on the rising edge of K clock; input write data on K and
K rising edges.
L–H
X
L
D(A+0) at
K(t) 
D(A+1) at
K(t) 
Read cycle:
Load address on the rising edge of K clock; wait one cycle; read data
on 2 consecutive C and C rising edges.
L–H
L
X
Q(A+0) at
C(t+1)
Q(A+1) at
C(t+1) 
NOP: No operation
L–H
H
H
D=X
D=X
Q = High Z Q = High Z
Stopped
X
X
Previous
state
Standby: Clock stopped
DQ
DQ
Previous
state
Write Cycle Descriptions
The write cycle description table for CY7C1303BV25 follow. [7, 8]
BWS0
BWS1
K
K
L
L
L–H
–
During the data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
Comments
L
L
–
L–H
During the data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L
H
L–H
–
During the data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device.
D[17:9] remains unaltered.
L
H
–
L–H
During the data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device.
D[17:9] remains unaltered.
H
L
L–H
–
During the data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0]
remains unaltered.
H
L
–
L–H
During the data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0]
remains unaltered.
H
H
L–H
–
No data is written into the device during this portion of a write operation.
H
H
–
L–H
No data is written into the device during this portion of a write operation.
Notes
1. X = Do not Care, H = Logic HIGH, L = Logic LOW,  represents rising edge.
2. Device power-ups deselected and the outputs in a three-state condition.
3. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represent the addresses sequence in the burst.
4. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
5. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
6. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
7. X = Do not Care, H = Logic HIGH, L = Logic LOW,  represents rising edge.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1, in the case of CY7C1303BV25 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 38-05627 Rev. *F
Page 8 of 25
CY7C1303BV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1 to 1900. The TAP operates using JEDEC
standard 2.5 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device comes
up in a reset state which does not interfere with the operation of
the device.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 11. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 15).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 38-05627 Rev. *F
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in TAP Controller Block Diagram on
page 12. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can
be used to capture the contents of the Input and Output ring.
The Boundary Scan Order on page 16 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 15.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Codes on page 15. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Page 9 of 25
CY7C1303BV25
IDCODE
The IDCODE instruction causes a vendor specific, 32-bit code to
be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that are captured.
Repeatable results may not be possible.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while data captured is
shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST Output Bus Tri-state
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tri-state”, is
latched into the preload register during the “Update-DR” state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell latches into the preload
register. When the EXTEST instruction is entered, this bit directly
controls the output Q-bus pins. Note that this bit is pre-set HIGH
to enable the output when the device is powered-up, and also
when the TAP controller is in the “Test-Logic-Reset” state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
Document Number: 38-05627 Rev. *F
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 10 of 25
CY7C1303BV25
TAP Controller State Diagram
The state diagram for the TAP controller follows. [9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05627 Rev. *F
Page 11 of 25
CY7C1303BV25
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
106
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter [10, 11, 12]
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH voltage
IOH =2.0 mA
1.7
–
V
VOH2
Output HIGH voltage
IOH =100 A
2.1
–
V
VOL1
Output LOW voltage
IOL = 2.0 mA
–
0.7
V
VOL2
Output LOW voltage
IOL = 100 A
–
0.2
V
VIH
Input HIGH voltage
1.7
VDD + 0.3
V
VIL
Input LOW voltage
–0.3
0.7
V
IX
Input and output load current
5
5
A
GND  VI  VDDQ
Notes
10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 17.
11. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5 V (Pulse width less than tCYC/2).
12. All Voltage referenced to Ground.
Document Number: 38-05627 Rev. *F
Page 12 of 25
CY7C1303BV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [13, 14]
Description
Min
Max
Unit
50
–
ns
TCK clock frequency
–
20
MHz
TCK clock HIGH
20
–
ns
TCK clock LOW
20
–
ns
tTMSS
TMS setup to TCK clock rise
10
–
ns
tTDIS
TDI setup to TCK clock rise
10
–
ns
tCS
Capture setup to TCK rise
10
–
ns
tTCYC
TCK clock cycle time
tTF
tTH
tTL
Setup Times
Hold Times
tTMSH
TMS hold after TCK clock rise
10
–
ns
tTDIH
TDI hold after clock rise
10
–
ns
tCH
Capture hold after clock rise
10
–
ns
tTDOV
TCK clock LOW to TDO valid
–
20
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
Output Times
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05627 Rev. *F
Page 13 of 25
CY7C1303BV25
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [15]
Figure 3. TAP Timing and Test Conditions
1.25 V
All input pulses
50 
2.5 V
1.25 V
TDO
0V
Z0 = 50 
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTMSH
tTMSS
tTCYC
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Note
15. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document Number: 38-05627 Rev. *F
Page 14 of 25
CY7C1303BV25
Identification Register Definitions
Value
Instruction Field
Description
CY7C1303BV25
Revision Number (31:29)
000
Cypress Device ID (28:12)
01011010010010101
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 38-05627 Rev. *F
Page 15 of 25
CY7C1303BV25
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
1
6P
27
11H
54
7B
81
3G
28
10G
55
6B
82
2G
2
6N
29
9G
56
6A
83
1J
3
7P
30
11F
57
5B
84
2J
4
7N
31
11G
58
5A
85
3K
5
7R
32
9F
59
4A
86
3J
6
8R
33
10F
60
5C
87
2K
7
8P
34
11E
61
4B
88
1K
8
9R
35
10E
62
3A
89
2L
9
11P
36
10D
63
1H
90
3L
10
10P
37
9E
64
1A
91
1M
11
10N
38
10C
65
2B
92
1L
12
9P
39
11D
66
3B
93
3N
13
10M
40
9C
67
1C
94
3M
14
11N
41
9D
68
1B
95
1N
15
9M
42
11B
69
3D
96
2M
16
9N
43
11C
70
3C
97
3P
17
11L
44
9B
71
1D
98
2N
18
11M
45
10B
72
2C
99
2P
19
9L
46
11A
73
3E
100
1P
20
10L
47
Internal
74
2D
101
3R
21
11K
48
9A
75
2E
102
4R
22
10K
49
8B
76
1E
103
4P
23
9J
50
7C
77
2F
104
5P
24
9K
51
6C
78
3F
105
5N
25
10J
52
8A
79
1G
106
5R
26
11J
53
7A
80
1F
Document Number: 38-05627 Rev. *F
Page 16 of 25
CY7C1303BV25
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Range
Ambient
Temperature (TA)
Commercial
Storage temperature ............................... –65 °C to + 150 °C
0 °C to + 70 °C
VDD[17]
VDDQ[17]
2.5 ± 0.1 V 1.4 V to 1.9 V
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage on VDD relative to GND ......–0.5 V to + 3.6 V
Neutron Soft Error Immunity
Supply voltage on VDDQ relative to GND ..... –0.5 V to + VDD
Parameter
DC applied to outputs
in High Z state ..................................–0.5 V to VDDQ + 0.5 V
LSBU
Logical
single-bit
upsets
25 °C
LMBU
Logical
multi-bit
upsets
Single event
latch-up
DC input
voltage[16]
............................ –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Description
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch-up Current ................................................... > 200 mA
SEL
Test
Conditions Typ
Max*
Unit
320
368
FIT/
Mb
25 °C
0
0.01
FIT/
Mb
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note, Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates – AN54908.
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [18]
Description
Test Conditions
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
Output HIGH voltage
Note 19
VOL
Output LOW voltage
Note 20
VOH(LOW)
Output HIGH voltage
IOH = –0.1 mA, nominal impedance
VOL(LOW)
Output LOW voltage
IOL = 0.1 mA, nominal impedance
VIH
Input HIGH voltage [16]
[16, 21]
Min
Typ
Max
Unit
2.4
2.5
2.6
V
1.4
1.5
1.9
V
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VDDQ – 0.2
–
VDDQ
V
VSS
–
0.2
V
VREF + 0.1
–
VDDQ + 0.3
V
–0.3
–
VREF – 0.1
V
0.68
0.75
0.95
V
VIL
Input LOW voltage
VREF
Input Reference voltage [22]
IX
Input Leakage current
GND  VI  VDDQ
–5
–
5
A
IOZ
Output Leakage current
GND  VI  VDDQ, output disabled
–5
–
5
A
Typical value = 0.75 V
Notes
16. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5 V (Pulse width less than tCYC/2).
17. Power-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
18. All Voltage referenced to Ground.
19. Output are impedance controlled. IOH = –VDDQ/2)/(RQ/5) for values of 175  < RQ < 350 .
20. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175  < RQ < 350 .
21. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2 V.
22. VREF(Min.) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF(Max.) = 0.95 V or 0.54 VDDQ, whichever is smaller.
Document Number: 38-05627 Rev. *F
Page 17 of 25
CY7C1303BV25
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [18]
Min
Typ
Max
Unit
IDD
VDD operating supply
Description
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Test Conditions
–
–
500
mA
ISB1
Automatic power-down current
Max. VDD, both ports deselected,
VIN  VIH or VIN  VIL,
f = fMAX =1/tCYC, inputs static
–
–
240
mA
Min
Typ
Max
Unit
AC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VIH
Input HIGH voltage
VREF + 0.2
–
–
V
VIL
Input LOW voltage
–
–
VREF – 0.2
V
Thermal Resistance
Parameter [23]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
165-ball FBGA Unit
Package
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
16.7
C/W
6.5
C/W
Test Conditions
Max
Unit
5
pF
Capacitance
Parameter [23]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
6
pF
CO
Output capacitance
7
pF
TA = 25 °C, f = 1 MHz, VDD = 2.5 V, VDDQ = 1.5 V
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
VREF = 0.75 V
VREF
0.75 V
VREF
OUTPUT
Z0 = 50 
Device
Under
Test
R = 50 
All input pulses
RL = 50 
OUTPUT
Device
Under
VREF = 0.75 V Test ZQ
ZQ
0.75 V
RQ =
250 
[24]
1.25 V
0.75 V
5 pF
0.25 V
Slew Rate = 2 V/ns
RQ =
250 
(a)
(b)
Notes
23. Tested initially and after any design or process change that may affect these parameters.
24. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V,VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 4.
Document Number: 38-05627 Rev. *F
Page 18 of 25
CY7C1303BV25
Switching Characteristics
Over the Operating Range
Parameter [25]
167 MHz
Description
Cypress Consortium
Parameter Parameter
tPower[26]
Unit
Min
Max
VCC(typical) to the first access read or write
10
–
s
6.0
–
ns
Cycle Time
tCYC
tKHKH
K clock and C clock cycle time
tKH
tKHKL
Input clock (K/K and C/C) HIGH
2.4
–
ns
tKL
tKLKH
Input clock (K/K and C/C) LOW
2.4
–
ns
tKHKH
tKHKH
K/K clock rise to K/K clock rise and C/C to C/C rise (rising edge to rising
edge)
2.7
3.3
ns
tKHCH
tKHCH
K/K clock rise to C/C Clock rise (rising edge to rising edge)
0.0
2.0
ns
0.7
–
ns
Setup Times
tSA
tSA
Address setup to clock (K and K) Rise
tSC
tSC
Control setup to clock (K and K) Rise (RPS, WPS, BWS0, BWS1)
0.7
–
ns
tSD
tSD
D[x:0] setup to clock (K and K) Rise
0.7
–
ns
tHA
tHA
Address hold after clock (K and K) Rise
0.7
–
ns
tHC
tHC
Control signals hold after clock (K and K) Rise (RPS, WPS, BWS0, BWS1)
0.7
–
ns
tHD
tHD
D[x:0] hold after clock (K and K) Rise
0.7
–
ns
–
2.5
ns
1.2
–
ns
–
2.5
ns
1.2
–
ns
Hold Times
Output Times
tCO
tCHQV
C/C clock rise (or K/K in single clock mode) to data valid
tDOH
tCHQX
Data output hold after output C/C clock rise (active to active)
tCHZ
tCHZ
Clock (C and C) rise to high Z (active to high Z) [27, 28]
tCLZ
tCLZ
Clock (C and C) rise to low Z
[27, 28]
Notes
25. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, VREF = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 4 on page 18.
26. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read or
write operation can be initiated.
27. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
28. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of Figure 4 on page 18. Transition is measured ±100 mV from steady-state voltage.
Document Number: 38-05627 Rev. *F
Page 19 of 25
CY7C1303BV25
Switching Waveforms
Figure 5. Switching Waveforms [29, 30, 31]
READ
W R IT E
1
2
READ
WRITE
3
REA D
4
WRITE
NO P
W R IT E
NO P
7
8
9
6
5
10
K
t KH
t KL
t CYC
t KHKH
K
RPS
tSC
tHC
W PS
A
t SA
D
D10
A2
A1
A0
t HA
D11
t SA
A3
A4
A5
D31
D50
D51
t HA
D30
Q 00
Q
t KHCH
t CO
Q 01
tDOH
t CLZ
D60
t SD
t HD
t SD
t KHCH
A6
Q 20
D61
t HD
Q 21
Q 40
Q 41
t CHZ
tDOH
t CO
C
t KH
t KL
t KHKH
tCYC
C
DON’T CARE
UNDEFINE D
Notes
29. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
30. Outputs are disabled (High Z) one clock cycle after a NOP.
31. In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.
Document Number: 38-05627 Rev. *F
Page 20 of 25
CY7C1303BV25
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
Ordering Code
CY7C1303BV25-167BZC
Package
Diagram
Package Type
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
Operating
Range
Commercial
Ordering Code Definitions
CY
7
C 1303
B V25 - 167
BZ
X
C
Temperature range:
C = Commercial
X = Pb-free; X Absent = Leaded
Package Type:
BZ = 165-ball FBGA
Speed Grade: 167 MHz
V25 = 2.5 V
Process Technology: B  90 nm
1303 = Part Identifier
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05627 Rev. *F
Page 21 of 25
CY7C1303BV25
Package Diagram
Figure 6. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *E
Document Number: 38-05627 Rev. *F
Page 22 of 25
CY7C1303BV25
Acronyms
Acronym
Document Conventions
Description
Units of Measure
DDR
double data rate
FBGA
fine-pitch ball grid array
°C
degree Celsius
HSTL
high-speed transceiver logic
k
kilohm
I/O
input/output
MHz
megahertz
JEDEC
joint electron device engineering council
µA
microampere
JTAG
joint test action group
µs
microsecond
LMBU
logical multi-bit upsets
mA
milliampere
LSB
least significant bit
mV
millivolt
LSBU
logical single-bit upsets
mm
millimeter
MSB
most significant bit
ms
millisecond
PLL
phase-locked loop
ns
nanosecond
QDR
quad data rate

ohm
SEL
single event latch-up
%
percent
SRAM
static random access memory
pF
picofarad
TAP
test access port
ps
picosecond
TCK
test clock
V
volt
TDI
test data in
W
watt
TDO
test data out
TMS
test mode select
Document Number: 38-05627 Rev. *F
Symbol
Unit of Measure
Page 23 of 25
CY7C1303BV25
Document History Page
Document Title: CY7C1303BV25, 18-Mbit Burst of Two-Pipelined SRAM with QDR® Architecture
Document Number: 38-05627
Rev.
ECN
Orig. of
Change
Submission
Date
Description of Change
**
253010
SYT
08/13/04
New data sheet.
*A
436864
NXR
See ECN
Changed status from Preliminary to Final.
Updated Features (Changed C/C description).
Updated Selection Guide (Removed 133 MHz and 100 MHz from product
offering).
Updated Pin Definitions (Updated C/C description, updated ZQ description
(Alternately, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode.)).
Updated TAP AC Switching Characteristics (Changed minimum value of tTCYC
parameter from 100 ns to 50 ns, changed maximum value of tTF parameter
from 10 MHz to 20 MHz, changed minimum value of tTH and tTL parameters
from 40 ns to 20 ns).
Updated Maximum Ratings (Included Maximum Ratings for Supply Voltage on
VDDQ Relative to GND, changed the Maximum Ratings for DC Input Voltage
from VDDQ to VDD).
Updated Operating Range (Updated Note 17 (Modified test condition from
VDDQ < VDD to VDDQ  VDD), included the Industrial Operating Range).
Updated Electrical Characteristics (Changed description of IX parameter from
Input Load current to Input Leakage Current, removed 133 MHz and 100 MHz
from product offering).
Updated Ordering Information (Updated table and replaced Package Name
Column with Package Diagram).
*B
2755901
VKN
08/25/09
Added Neutron Soft Error Immunity.
Updated Ordering Information (Updated table by including parts that are
available, and modified the disclaimer for the Ordering information).
Updated Package Diagram.
*C
2998771
NJY
08/02/10
Updated Package Diagram.
Updated in new template.
*D
3310077
OSN
07/12/2011
Added Units of Measure.
Updated in new template.
*E
3534369
PRIT
02/24/2012
Updated Configurations (Removed CY7C1306BV25 related information).
Updated Functional Description (Removed CY7C1306BV25 related
information).
Updated Selection Guide (Removed CY7C1306BV25 related information).
Removed Logic Block Diagram – CY7C1306BV25.
Updated Pin Configuration (Removed CY7C1306BV25 related information).
Updated Pin Definitions (Removed CY7C1306BV25 related information).
Updated Functional Overview (Removed CY7C1306BV25 related
information).
Updated Truth Table (Removed CY7C1306BV25 related information).
Updated Write Cycle Descriptions (Removed CY7C1306BV25 related
information).
Updated Identification Register Definitions (Removed CY7C1306BV25 related
information).
Updated Operating Range (Removed Industrial Operating Range).
Updated Package Diagram.
*F
3690005
PRIT
07/24/2012
No technical changes. Completing sunset review.
Document Number: 38-05627 Rev. *F
Page 24 of 25
CY7C1303BV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
PSoC Solutions
cypress.com/go/automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
Optical & Image Sensing
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/USB
Wireless/RF
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05627 Rev. *F
®
®
Revised July 24, 2012
Page 25 of 25
Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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