CYPRESS CYIL2SM1300AA_09

CYIL2SM1300AA
LUPA 1300-2: High Speed CMOS
Image Sensor
Features
■
1280 x 1024 Active Pixels
■
14 µm X 14 µm Square Pixels
The peak responsivity of the 14 µm x 14 µm 6T pixel is 7350
V.m2/W.s. Dynamic range is measured at 57 dB. In full frame
video mode, the sensor consumes 1350 mW from the 2.5V
power supply. The sensors integrate A/D conversion, on-chip
timing for a wide range of operating modes, and has an LVDS
interface for easy system integration.
1” Optical Format
■ Monochrome or Color Digital Output
■
By removing the visually disturbing column patterned noise, this
sensor enables building a camera without any offline correction
or the need for memory. In addition, the on-chip column FPN
correction is more reliable than an offline correction, because it
compensates for supply and temperature variations. The sensor
requires one master clock for operations up to 500 fps.
■
500 fps Frame Rate
■
On-Chip 10-Bit ADCs
■
12 LVDS Serial Outputs
■
Random Programmable ROI Readout
■
Pipelined and Triggered Snapshot Shutter
■
On-Chip Column FPN Correction
■
Serial to Parallel Interface (SPI)
The LUPA 1300-2 is housed in a 168 pin µPGA package and is
available in a monochrome version and Bayer (RGB) patterned
color filter array. The monochrome version is available without
glass. Contact your local Cypress office.
■
Limited Supplies: Nominal 2.5V and 3.3V
Figure 1. LUPA 1300-2 Die Photo
■
0°C to 70°C Operational Temperature Range
■
168-Pin µPGA Package
■
Power Dissipation: 1350 mW
Applications
■
High Speed Machine Vision
■
Motion Analysis
■
Intelligent Traffic System
■
Medical Imaging
■
Industrial Imaging
Description
The LUPA 1300-2 is an integrated SXGA high speed, high
sensi¬tivity CMOS image sensor. This sensor targets high speed
machine vision and industrial monitoring applications. The LUPA
1300-2 sensor runs at 500 fps and has triggered and pipelined
shutter modes. It packs 24 parallel 10-bit A/D converters with an
aggregate conversion rate of 740 MSPS. On-chip digital column
FPN correction enables the sensor to output ready to use image
data for most applications. To enable simple and reliable system
integration, the 12 channels, 1 sync channel, 8 Gbps, and LVDS
serial link protocol supports skew correction and serial link
integrity monitoring.
Table 1. Marketing Part Number
Marketing Part Number
(ES Samples)
CYIL2SM1300AA-GZDC
Mono/Color
Package
mono with glass
168 pin
ceramic
µPGA
CYIL2SM1300AA-GWCES mono without glass[1]
CYIL2SC1300AA-GZDC
color with glass
Note
1. Contact your local sales office for the windowless option.
Cypress Semiconductor Corporation
Document Number: 001-24599 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 24, 2009
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Overview
Specifications
This data sheet describes the interface of the LUPA1300-2
image sensor. The SXGA resolution CMOS active pixel sensor
features synchronous shutter and a maximal frame rate of
500 fps in full resolution. The readout speed is boosted by sub
sampling and the windowed region of interest (ROI) readout.
FPN correction cannot be used in conjunction with sub-sampling
and windowed region of interest readout. High dynamic range
scenes can be captured using the double and multiple slope
functionality. User programmable row and column start and stop
positions enables windowing. Sub sampling reduces resolution
while maintaining the constant field of view and an increased
frame rate.
Table 2. General Specifications
The LUPA1300-2 sensor has 12 LVDS high speed outputs that
transfer image data over longer distances. This simplifies the
surrounding system. The LVDS interface can receive high speed
and wide bandwidth data signals and maintain low noise and
distortion. A special training mode enables the receiving system
to synchronize the coming data stream when switching to
master, slave, or triggered mode. The image sensor also
integrates a programmable offset and gain amplifier for each
channel.
A 10-bit ADC converts the analog data to a 10-bit digital word
stream. The sensor uses a 3-wire Serial-Parallel Interface (SPI).
It requires only one master clock for operation up to 500 fps.
The sensor is available in a monochrome version or Bayer (RGB)
patterned color filter array. It is placed in a 168-pin ceramic µPGA
package.
Document Number: 001-24599 Rev. *B
Parameter
Specifications
Active Pixels
1280 (H) x 1024 (V)
Pixel Size
14 µm x 14 µm
Pixel Type
6T pixel architecture
Pixel Rate
630 Mbps per channel (12 serial
LVDS outputs)
Shutter Type
Pipelined and Triggered Global
Shutter
Frame Rate
500 fps at 1.3 Mpixel (boosted by
subsampling and windowing)
Master Clock
315 MHz for 500 fps
Windowing (ROI)
Randomly programmable ROI read
out up to four multiple windows
Read Out
Windowed, flipped, mirrored, and
subsampled read out possible
ADC Resolution
10-bit, on-chip
Sensitivity
10.16 V/lux.s at 550 nm
Extended Dynamic
Range
Multiple slope (up to 90 dB optical
dynamic range)
Table 3. Electro Optical Specifications
Parameter
Value
Conversion gain
34µV/e-
Full well charge
30000e-
Responsivity
7350 V.m2/W.s at 680 nm
Fill factor
40%
Parasitic light sensitivity
< 1/10000
Dark noise
37e-
QE x FF
35% at 680 nm
FPN
2% rms of the output swing
PRNU
<1% rms of the output signal
Dark signal
170 mV/s at 30°C
Power dissipation
1350 mW
Page 2 of 41
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Photovoltaic Response Curve
Figure 2. Photo Voltaic Response of LUPA 1300-2
Spectral Response Curve
Figure 3. Spectral Response of LUPA 1300-2
Document Number: 001-24599 Rev. *B
Page 3 of 41
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Figure 4. Spectral Response of LUPA 1300-2 Color Sensor
0.2
0.18
0.16
0.14
0.12
RED
GREEN NEAR RED
GREEN NEAR BLUE
BLUE
0.1
0.08
0.06
0.04
0.02
0
400
500
Document Number: 001-24599 Rev. *B
600
700
800
900
1000
Page 4 of 41
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CYIL2SM1300AA
Electrical Specifications
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 4. Absolute Ratings [2]
Symbol
Parameter
Min
Max
Units
VDIG
Core digital supply voltage
-0.5
5.5
V
VIN
Analog supply voltage
-0.5
5.5
V
IIO
DC supply current
ESD: HBM
Human Body Model
2000
ESD: CDM
Charged Device Model
500
TJ
Temperature range
mA
V
V
0
70
°C
Table 5. Power Supply Ratings [3, 4, 5]
Boldface limits apply for TA=TMIN to TMAX, all other limits TA=+25°C. Clock = 315 MHz
Symbol
Power Supply
VANA, GNDANA Analog Supply
VDIG, GNDDIG
VPIX, GNDPIX
VLVDS,
GNDLVDS
Digital Supply
Pixel Supply
LVDS Supply
VADC, GNDADC ADC Supply
Parameter
Min
Typ
Max
Units
-5%
2.5
+5%
V
20
mA
Dynamic Current
Clock enabled, lux=0
7
Peak Current
Clock enabled, lux=0
16
Standby current
Shutdown mode, lux=0
Operating voltage
+5%
V
120
mA
Clock enabled, lux=0
80
Clock enabled, lux=0
130
Standby current
Shutdown mode, lux=0
52
-5%
Dynamic Current
Clock enabled, lux=0
Peak Current during FOT
Clock enabled, lux=0,
transient duration=9 µs
mA
2.5
Peak Current
Operating voltage
mA
1
-5%
Dynamic Current
mA
2.5
+5%
V
6
50
mA
1.4
A
Peak Current during ROT Clock enabled, lux=0,
transient duration=2.5 µs
35
mA
Standby current
1
mA
Shutdown mode, lux=0
Operating voltage
Dynamic Current
-5%
Clock enabled, lux=0
2.5
+5%
V
220
275
mA
Peak current
Clock enabled, lux=0
280
mA
Standby current
Shutdown mode, lux=0
100
mA
Operating voltage
2.5
+5%
V
Clock enabled, lux=0
210
275
mA
Peak Current
Clock enabled, lux=0
260
mA
Standby current
Shutdown mode, lux=0
3
mA
Dynamic Current
VBUF, GNDBUF Buffer Supply
Condition
Operating voltage
-5%
Operating voltage
Dynamic Current
-5%
Clock enabled, lux=0
2.5
+5%
V
30
50
mA
Peak Current
Clock enabled, lux=0
85
mA
Standby current
shutdown mode, lux=0
0.1
mA
Notes
2. Absolute ratings are those values beyond which damage to the device may occur.
3. All parameters are characterized for DC conditions after thermal equilibrium is established.
4. Peak currents were measured without the load capacitor from the LDO (Low Dropout Regulator). The 100 nF capacitor bank was connected to the pin in question.
5. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended that normal precautions
be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit.
Document Number: 001-24599 Rev. *B
Page 5 of 41
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Table 5. Power Supply Ratings [3, 4, 5] (continued)
Boldface limits apply for TA=TMIN to TMAX, all other limits TA=+25°C. Clock = 315 MHz
Symbol
VSAMPLE,
GNDSAMPLE
VRES
VRES_AB
VRES_DS
VRES_TS
VMEM_L
VMEM_H
VPRECH
Power Supply
Parameter
Sampling
Operating voltage
Circuitry Supply Dynamic Current
Reset Supply
Antiblooming
Supply
Reset Dual
Slope Supply
Reset Triple
Slope Supply
Memory
Element low
level supply
Condition
Min
Typ
Max
Units
-5%
2.5
+5%
V
Clock enabled, lux=0
2
mA
Peak Current
Clock enabled, lux=0
42
mA
Standby current
Shutdown mode, lux=0
Operating voltage
1
-5%
+5%
V
15
mA
Dynamic Current
Clock enabled, lux=0
2
Peak Current
Clock enabled, lux=0
65
Standby current
Shutdown mode, lux=0
Operating voltage
mA
3.5
mA
2
-10%
0.7
mA
+10%
V
Dynamic Current
Clock enabled, lux=0
1
mA
Peak Current following
edge reset
Clock enabled, lux=0
50
mA
Standby current
Shutdown mode, lux=0
1
mA
Operating voltage
-5%
Dynamic Current
Clock enabled, lux=0
Peak Current
Clock enabled, lux=0
Operating voltage
2.5
+5%
V
0.4
3
mA
36
-5%
+5%
2
Dynamic Current
Clock enabled, lux=0
0.3
Peak Current
Clock enabled, lux=0
14
Operating voltage
Dynamic Current
-5%
Clock enabled, lux=0
mA
1.8
V
mA
mA
2.5
+5%
V
0.2
1
mA
Peak Current during FOT
Clock enabled, lux=0
62
mA
Peak Current during FOT
Clock enabled, bright
30
mA
Memory
Element high
level supply
Operating voltage
Pre_charge
Driver Supply
Operating voltage
-5%
Dynamic Current
Clock enabled, lux=0
Peak Current during FOT
Clock enabled, lux=0
3.3
+5%
1
45
-10%
V
mA
mA
0.7
+10%
3
V
Dynamic Current
Clock enabled, lux=0
0.3
Peak Current during FOT
Clock enabled, lux=0
32
mA
Peak Current during FOT
Clock enabled, lux=bright
25
mA
Every module in the image sensor has its own power supply and
ground. The grounds can be combined externally, but not all
power supply inputs may be combined. Some power supplies
must be isolated to reduce electrical crosstalk and improve
shielding, dynamic range, and output swing. Internal to the
image sensor, the ground lines of each module are kept separate
to improve shielding and electrical crosstalk between them.
The LUPA 1300-2 contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
take normal precautions to avoid voltages higher than the
maximum rated voltages in this high impedance circuit. Unused
Document Number: 001-24599 Rev. *B
mA
inputs must always be tied to an appropriate logic level, for
example, VDD or GND. All cap_xxx pins must be connected to
ground through a 100 nF capacitor.
The recommended combinations of supplies are:
■
Analog group of +2.5V supply: VSAMPLE, VRES_DS, VMEM_L,
VADC, Vpix, VANA, VBUF
■
Digital Group of +2.5V supply: VDIG, VLVDS
Page 6 of 41
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Table 6. Power Dissipation [3]
These specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps
Parameter
Symbol
Condition
Typ
Units
PDOWN
Power down
no clock running
400
mW
Power
Average Power Dissipation
lux = 0
1350
mW
Table 7. AC Electrical Characteristics [3]
The following specifications apply for VDD = 2.5V, Clock = 315 MHz, 500 fps.
Parameter
Symbol
Condition
FCLK
Input Clock Frequency
DCCLK
Clock Duty Cycle
At maximum clock
fps
Frame rate
Maximum clock speed
Typ
fps = 500
Max
Units
315
MHz
500
fps
50
%
Sensor Architecture
The floor plan of the architecture is shown in Figure 5. The sensor consists of a pixel array, analog front end, data block, and LVDS
transmitters and receivers. Separate modules for the SPI, clock division, and sequencer are also integrated. The image sensor of
1280 x 1024 pixels is read out in progressive scan.
This architecture enables programmable addressing in the x-direction in steps of 24 pixels, and in the y-direction in steps of one pixel.
The starting point of the address can be uploaded by the serial parallel interface (SPI).
The AFE prepares the signal for the digital data block when the data is multiplexed and prepared for the LVDS interface.
Figure 5. Floor Plan of the Sensor
Image core
1280 x 1024
24 analog channels
SPI
31.5 Msps
Clk X & Clk Y
Analog front end
24x 10-bit digital channels
31.5 Msps
Sequencer
&
Logic
31.5 MHz
Clk in
Clock
Divider
Local register
Clk out
Data block
12x 10-bit digital channels
63 Msps
63 MHz
LVDS TX and RX
315 MHz
12x LVDS outputs at 630 Msps
Document Number: 001-24599 Rev. *B
Page 7 of 41
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The 6T Pixel
Windowing
To obtain the global shutter feature combined with a high
sensitivity and good parasitic light sensitivity (PLS), implement
the pixel architecture shown in Figure 6. This pixel architecture
is designed in a 14 µm x 14 µm pixel pitch. The pixel is designed
to meet the specifications listed in Table 2 and Table 3 on page
2. This architecture also enables pipelined or triggered mode, as
shown in Figure 6.
Windowing is easily achieved by SPI. The starting point of the x
and y address and the window size can be uploaded. The
minimum step size in the x-direction is 24 pixels (choose only
multiples of 24 as start or stop addresses). The minimum step
size in the y-direction is one line (every line can be addressed)
in normal mode, and two lines in sub sampling mode.
Figure 6. 6T Pixel Architecture
Vpix
The section Sequencer on page 10 discusses the use of
registers to achieve the desired ROI.
Table 9. Typical Frame Rates for 630 MHz Clock
Vmem
Sample
Select
Image
Frame Rate Frame Read
Resolution (X*Y)
(fps)
Out Time (µs)
Reset
1296x1025
507
1970
640 x 512
1842
550
256 x 256
6933
146
Analog to Digital Converter
The sensor has 24 10-bit pipelined ADCs on board. The ADCs
nominally operate at 31.5 Msamples/s.
Table 10. ADC Parameters
Frame Rate and Windowing
Parameter
Frame Rate
The frame rate depends on the input clock, the frame overhead
time (FOT), and the row overhead time (ROT). The frame period
is calculated by:
Frame period = FOT+Nr. Lines * (ROT + Nr. Pixels * clock period)
Table 8. Frame Rate Parameters
Parameter
FOT
Comment
Clarification
Frame Overhead
Time
Programmable: Default
315 MHz granularity clock
cycles (5 µs at 630 MHz)
ROT
Row Overhead
Time
Programmable: Default 13
granularity clock cycles
(206 ns at 630 MHz)
Nr. Lines
Number of lines
read out each
frame
Nr. Pixels
Number of pixels
read out each line
Clock Period 1/63 MHz = 15.9 ns Every channel works at
63 MHz Æ12 channels
result in 756 MHz data rate
Example
Specification
Data rate
31.5 Msamples/s
Quantization
10 bit
DNL
Typ. < 1 DN
INL
Typ. < 1 DN
Programmable Gain Amplifiers
The PGAs amplify the signal before sending it to the ADCs.
The amplification inside the PGA is controlled by one SPI setting:
afemode [5:3].
Six gain steps can be selected by the afemode<5:3> register.
Table 11 lists the six gain settings. The unity gain selection of the
PGA is done by the default afemode<5:3> setting.
Table 11. Gain Settings
afemode<5:3>
Gain
000
1
001
1.5
010
2
011
2.25
100
3
101
4
Readout of the full resolution at nominal speed (756 MHz pixel
rate = 1.32 ns)
Frame period = 5 µs + (1025 * (206 ns+1.32 ns*1296) = 1.97 ms
=> 507 fps
The real speed of the LUPA1300-2 is reduced to 500 fps,
because overhead pixels are read out for black level calibration
and other on board features.
Document Number: 001-24599 Rev. *B
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Operation and Signaling
Digital Signals
Depending on the operation mode (Master or Slave), the pixel array of the image sensor requires different digital control signals. The
function of each signal is listed in this table.
Table 12. Overview of Digital Signals
Signal Name
I/O
Comments
MONITOR_1
Output
Output pin for integration timing, high during integration
MONITOR_2
Output
Output pin for dual slope integration timing, high during integration
MONITOR_3
Output
Output pin for triple slope integration timing, high during integration
INT_TIME_3
Input
Integration pin triple slope
INT_TIME_2
Input
Integration pin dual slope
INT_TIME_1
Input
Integration pin first slope
RESET_N
Input
Sequencer reset, active LOW
CLK
Input
System clock (630 MHz)
SPI_CS
Input
SPI chip select
SPI_CLK
Input
Clock of the SPI
SPI_IN
Input
Data line of the SPI, serial input
SPI_OUT
Output
Data line of the SPI, serial output
Synchronous Shutter
In a synchronous (snapshot or global) shutter, light integration occurs on all pixels in parallel, although subsequent readout is
sequential. Figure 7 shows the integration and readout sequence for the synchronous shutter. All pixels are light sensitive at the same
period of time. The whole pixel core is reset simultaneously, and after the integration time, all pixel values are sampled together on
the storage node inside each pixel. The pixel core is read out line by line after integration. Note that the integration and readout cycle
can occur in parallel or in sequential mode (pipelined or triggered). Refer to the section Image Sensor Timing and Readout on page 18.
Figure 7. Synchronous Shutter Operation
COMMON SAMPLE&HOLD
COMMON RESET
Flash could occur here
Line number
Time axis
Integration Time
Document Number: 001-24599 Rev. *B
Burst Readout
ti
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Non Destructive Readout (NDR)
Figure 8. Principle of Non Destructive Readout
time
The sensor can also be read out in a nondestructive method. After a pixel is initially reset, it can be read multiple times, without being
reset. You can record the initial reset level and all intermediate signals. High light levels saturate the pixels quickly, but a useful signal
is obtained from the early samples. For low light levels, the later or latest samples must be used. Essentially, an active pixel array is
read multiple times, and reset only once. The external system intelligence interprets the data. Table 13 on page 10 summarizes the
advantages and disadvantages of nondestructive readout.
Table 13. Advantages and Disadvantages of Non Destructive Readout
Advantages
Disadvantages
Low noise, because it is true CDS
System memory required to record the reset level and the
intermediate samples
High sensitivity. The conversion capacitance is kept low.
Requires multiples readings of each pixel, so there is higher data
throughput
High dynamic range. The results include signals for short and Requires system level digital calculations
long integration times.
Note that the amount of samples taken with one initial reset is programmable in the nr_of_ndr_steps register. If nr_of_ndr_steps is
one, the sensor operates in the default method, that is one reset and one sample. This is called the disable nondestructive read out
mode.
When nr_of_ndr_steps is two, there is one reset and two samples, and so on. In the slave mode, nothing changes on the protocol of
the signals int_time_*. The sequencer suppresses the internal reset signal to the pixel array.
Sequencer
The sequencer generates the complete internal timing of the pixel array and the readout. The timing can be controlled by the user
through the SPI register settings. The sequencer operates on the same clock as the data block. This is a division by 10 of the input
clock (internally divided).
Table 14 lists the internal registers. These registers are discussed in detail in the section Detailed Description of Internal Registers on
page 15.
Table 14. Internal Registers
Block
Register Name
MBS (reserved) Fix1
Fix2
Fix3
Fix4
Fix5
Address [6..0]
0
1
2
3
4
Document Number: 001-24599 Rev. *B
Field
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Reset Value
0x00
0xFF
0x00
0x00
‘0x08’
Description
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Page 10 of 41
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Table 14. Internal Registers (continued)
Block
LVDS clk
divider
Register Name
lvdsmain
Address [6..0]
5
lvdspwd1
lvdspwd2
6
7
Fix6
afebias
afemode
8
9
10
Bias block
afepwd1
afepwd2
bandgap
11
12
13
Image Core
imcmodes
14
Fix7
Fix8
imcbias1
15
16
17
imcbias2
18
imcbias3
19
Imcbias4
20
AFE
Document Number: 001-24599 Rev. *B
Field
[3:0]
[7:4]
[7:0]
[5:0]
[6]
[7]
[7:0]
[3:0]
[2:0]
[5:3]
[6]
[7:0]
[3:0]
[0]
[1]
[2]
[5:3]
[0]
[1]
[2]
[3]
[4]
[5]
[7:0]
[7:0]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
Reset Value
‘0110’
0
0x00
0
0
0
0x00
‘1000’
‘111’
‘000’
0
0x00
0x00
‘0’
‘1’
‘0’
‘000’
0
‘1’
‘1’
0
‘1’
‘0’
0x00
0x00
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
‘1000’
Description
lvds trim
clkadc phase
Power down channel 7:0
Power down channel 13:8
Power down all channels
lvds test mode
Reserved, fixed value
afe current biasing
vrefp, vrefm settings
Pga settings
Power down AFE
Power down adc_channel_2x 7 to 0
Power down adc_channel_2x 11 to 8
Power down bandgap and currents
External resistor
External voltage reference
Bandgap trimming
Power down
Enable vrefcol regulator
Enable precharge regulator
Disable internal bias for vprech
Disable column load
clkmain invert
Reserved, fixed value
Reserved, fixed value
Bias colfpn DAC buffer
Bias precharge regulator
Bias pixel precharge level
Bias column ota
Bias column unip fast
Bias column unip slow
Bias column load
Bias column precharge
Page 11 of 41
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Table 14. Internal Registers (continued)
Block
Data Block
Register Name
Fix9
Fix10
dataconfig1
Address [6..0]
21
22
23
dataconfig2
Fix11
dacvrefadc
Fix12
Fix13
Fix14
datachannel0_1
datachannel0_2
datachannel1_1
Data Block
(continued)
24
25
26
27
28
29
30
31
32
datachannel1_2
33
datachannel12_1
54
datachannel12_2
Document Number: 001-24599 Rev. *B
55
Field
[7:0]
[7:0]
[1:0]
[2]
Reset Value
0x20
0xC0
0x00
0
[3]
[4]
[5]
[7:6]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[0]
[1]
[2]
0
0
0
0x03
0x2A
0
0x80
0x80
[3]
[5:4]
[7:0]
[0]
[1]
[2]
0
0x00
0x00
0
0
0
[3]
[5:4]
[7:0]
0
0x00
0x00
[0]
[1]
[2]
[3]
[5:4]
[7:0]
0
0
0
0
0
0
0
0x00
0x00
Description
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
‘1’: Enables user upload of dacvrefadc register value
‘0’: Keeps default value
Enable PRBS generation
Reserved, fixed value
Reserved, fixed value
Training pattern inserted to sync LVDS receivers
Training pattern inserted to sync LVDS receivers
Reserved, fixed value
Input to DAC to set the offset at the input of the ADC
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Bypass the data block
Enables the FPN correction
Overwrite incoming ADC data by the data in the
testpat register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
Bypass the data block
Enables the FPN correction
Overwrite incoming ADC data by the data in the
testpat register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
Bypass the data block
Enables the FPN correction
Overwrite incoming ADC data by the data in the
testpat register
Reserved, fixed value
Pattern inserted to generate a test image
Pattern inserted to generate a test image
Page 12 of 41
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Table 14. Internal Registers (continued)
Block
Sequencer
Register Name
Address [6..0]
seqmode1
56
Field
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
seqmode2
57
[4:0]
[6:5]
seqmode3
58
[0]
[1]
[2]
[5:3]
[6]
[7]
Document Number: 001-24599 Rev. *B
Reset Value
Description
0
Enables image capture
1
‘1’: Master mode, integration timing is generated
on-chip
‘0’: Slave mode, integration timing is controlled
off-chip through INT_TIME1, INT_TIME2 and
INT_TIME3 pins
0
‘0’: Pipelined mode
‘1’: Triggered mode
0
Enables(‘1’)/disables(‘0’) subsampling
0
‘1’: Color subsampling scheme: 1:1:0:0:1:1:0:0
‘0’: B&W subsampling scheme: 1:0:1:0:1
0
Enable dual slope
0
Enable triple slope
0
Enables continued row select (that is, assert row
select during pixel read out)
‘10000’
Must be overwritten with‘10001’ to this register after
startup, before readout.
‘00’
Number of active windows:
“00”: 1 window
“01”: 2 windows
“10”: 3 windows
“11”: 4 windows
‘1’
Enables the generation of the CRC10 on the data
and sync channels
‘0’
Not applicable
‘0’
Enable column fpn calibration
“001”
Number of frames in nondestructive read out:
“000”: invalid
“001”: one reset, one sample (default mode)
“010”: one reset, two samples
…
0
Controls the granularity of the timer settings (only for
those that have ‘granularity selectable’ in the
description):
‘0’: Expressed in number of lines
‘1’: Expressed in clock cycles (multiplied by
2**seqmode4[3:0])
0
Allows delaying the syncing of events that happen
outside of ROT to the next ROT. This avoids image
artefacts.
Page 13 of 41
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Table 14. Internal Registers (continued)
Block
Register Name
Address [6..0]
seqmode4
59
Field
[3:0]
[5:4]
window1_1
window1_2
60
61
window1_3
window1_4
62
63
window2_1
window2_2
64
65
window2_3
window2_4
66
67
window3_1
window3_2
68
69
window3_3
window3_4
70
71
window4_1
window4_2
72
73
window4_3
window4_4
74
75
res_length1
res_length2
res_dsts_length
76
77
78
[6]
[7]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[7:0]
[7:0]
tint_timer1
tint_timer2
tint_ds_timer1
79
80
81
[7:0]
[7:0]
[7:0]
tint_ds_timer2
82
[1:0]
tint_ts_timer1
83
[7:0]
tint_ts_timer2
84
[1:0]
Document Number: 001-24599 Rev. *B
Reset Value
Description
0x00
Multiplier factor (=2**seqmode4[3:0]) for the timers
when working in clock cycle mode
0x0
Selects the source signals to put on the digital test
pins (monitor pins):
“00”: integration time settings
“01”: EOS signals
“10”: frame sync signals
“11”: functional test mode
‘0’
Reverse read out in X direction
‘0’
Reverse read out in Y direction
0x00
Y start address for window 1
0x00
Y start address for window 1
0x00
X start address for window 1
0xFF
Y end address for window 1
0x3
Y end address for window 1
0x36
X width for window 1
0x00
Y start address for window 2
0x00
Y start address for window 2
0x00
X start address for window 2
0xFF
Y end address for window 2
0x3
Y end address for window 2
0x36
X width for window 2
0x00
Y start address for window 3
0x00
Y start address for window 3
0x00
X start address for window 3
0xFF
Y end address for window 3
0x3
Y end address for window 3
0x36
X width for window 3
0x00
Y start address for window 4
0x00
Y start address for window 4
0x00
X start address for window 4
0xFF
Y end address for window 4
0x3
Y end address for window 4
0x36
X width for window 4
0x02
Length of pix_rst (granularity selectable)
0x00
Length of pix_rst (granularity selectable)
0x01
Length of resetds and resetts (granularity
selectable)
0xFF
Length of integration time (granularity selectable)
0x03
Length of integration time (granularity selectable)
0x40
Length of DS integration time (granularity
selectable)
0x00
Length of DS integration time (granularity
selectable)
0x0C
Length of TS integration time (granularity
selectable)
0x00
Length of TS integration time (granularity
selectable)
Page 14 of 41
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Table 14. Internal Registers (continued)
Block
Register Name
tint_black_timer
rot_timer
fot_timer
fot_timer
prechpix_timer
prechpix_timer
prechcol_timer
Address [6..0]
85
86
87
88
89
90
91
Field
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
Reset Value
0x06
0x0D
0x36
0x01
0x7C
0x00
0x03
rowselect_timer
sample_timer
sample_timer
vmem_timer
vmem_timer
delayed_rdt_timer
92
93
94
95
96
97
[7:0]
[7:0]
[1:0]
[7:0]
[1:0]
[7:0]
0x09
0xF8
0x00
0x10
0x01
0
delayed_rdt_timer 98
[7:0]
0
[0]
[0]
[0]
[0]
[0]
[0]
0
0
0
0
0
0
Fix29
Fix30
Fix31
Fix32
Fix33
Fix34
99
100
101
102
103
104
Description
Reserved, fixed value
Length of ROT (granularity clock cycles)
Length of FOT (granularity clock cycles)
Length of FOT (granularity clock cycles)
Length of pixel precharge (granularity clock cycles)
Length of pixel precharge (granularity clock cycles)
Length of column precharge (granularity clock
cycles)
Length of rowselect (granularity clock cycles)
Length of pixel_sample (granularity clock cycles)
Length of pixel_sample (granularity clock cycles)
Length of pixel_vmem (granularity clock cycles)
Length of pixel_vmem (granularity clock cycles)
Readout delay for testing purposes (granularity
selectable)
Readout delay for testing purposes (granularity
selectable
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value
Reserved, fixed value, write 0x4 to it
Detailed Description of Internal Registers
Biasing Block
The registers must be changed only during idle mode, that is,
when seqmode1[0] is ‘0’. Uploaded registers have an immediate
effect on how the frame is read out. Parameters uploaded during
readout may have an undesired effect on the data coming out of
the images.
This block contains several registers for setting biasing currents
for the sensor. Default values after startup must remain
unchanged for normal operation of the sensor.
MBS Block
The register block contains registers for sensor testing and
debugging. All registers in this block must remain unchanged
after startup.
LVDS Clock Divider Block
Image Core Block
The registers in this block have an impact on the pixel array itself.
Default settings after startup must remain unchanged for normal
operation of the image sensor.
Data Block
The data block is positioned in between the analog front end
(output stage + ADCs) and the LVDS interface. It muxes the
outputs of 2 ADCs to one LVDS block and performs some minor
data handling:
This block controls division of the input clock for the LVDS
transmitters or receivers. This block also enables shutting down
one or all LVDS channels. For normal operation, this register
block must remain untouched after startup.
■
CRC calculation and insertion
AFE Block
■
Training and test pattern generation
This register block contains registers to shut down ADC
channels or the complete AFE block. This block also contains the
register for setting the PGA gain: AFE_mode[5:3]. Refer to
Electrical Specifications on page 5 for more details on the PGA
settings.
The most important registers in this block are:
Document Number: 001-24599 Rev. *B
Dataconfig. The dataconfig1[7:6] and dataconfig2[7:0] registers
insert a training pattern in the LVDS channels to sync the LVDS
receivers.
Page 15 of 41
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Datachannels. DatachannelX_1 and DatachannelX_2 (with
X=0 to 12) are registers that allow you to enable or disable the
FPN correction (DatachannelX_1[1]), and generate a test
pattern
if
necessary
(datachannelX_1[5:4]
and
datachannelX_2[7:0]).
Seqmode3[6]: Controls the granularity of the timer settings (only
for those that have 'granularity selectable' in the description). As
a result, all timer settings are set either in number of applied clock
cycles, or in the number of 'readout lines'.
Sequencer Block
'1': expressed in clock cycles (multiplied by 2**seqmode4 [3:0])
The sequencer block group registers allow enabling or disabling
image sensor features that are driven by the onboard sequencer.
This block consists of the following registers:
Seqmode1. The seqmode1 registers have the following
subregisters:
Seqmode1[0]: Enables image capture, must be '1' during image
acquisition.
Seqmode1[1]: This subregister has two modes:
'1': In this default mode the integration timing is generated
on-chip.
'0': expressed in number of lines
Seqmode3[7]: Allows syncing of events that happen outside of
ROT to be delayed to the next ROT to avoid image artifacts.
Seqmode4. This register consists of four subregisters:
Seqmode4[3:0]: Multiplier factor (2**seqmode4[3:0]) for the
timers when working in clock cycle mode.
Seqmode4[5:4]: Selects the source signals to be put on the
digital test pins (monitor1, monitor2, and monitor3 pins)
"00": integration time settings
"01": EOS signals
'0': In this slave mode, the integration timing must be generated
through the int_time1, int_time2, and int_time3 pins.
"10": frame sync signals
Seqmode1[2]: This bit enables pipelined (0) or triggered (1)
mode.
Seqmode4[6]: Enables (1) and disables (0) reverse X read out.
Seqmode1[3]: Enable (1) or disable (0) subsampling.
Seqmode1[4]: This bit sets the type of subsampling scheme
used when subsampling is enabled.
Y1_start (60 and 61, 10 bit). These registers set the Y start
address for window 1 (default window).
'1': Color (1:1:0:0:1:1:0:0:1…)
'0': Black and White (1:0:1:0:1)
Seqmode1[5]: This bit enables or disables the dual slope
integration.
Seqmode1[6]: This bit enables or disables the triple slope
integration.
Seqmode2. The seqmode2 register consists of only two
subregisters:
Seqmode2[4:0]: Default value after startup is '10000', but this
must be overwritten with the new value '10001' immediately after
startup.
Seqmode3[6:5]: These two bits set the number of active
windows:
'00': 1 window
'01': 2 windows
'10': 3 windows
'11': 4 windows (max)
Seqmode3. The seqmode3 register consists of the following
subregisters:
Seqmode3[0]: This bit enables or disables the CRC10
generation on the data and sync channels
Seqmode3[1]: Enables or disables black level calibration
Seqmode3[2]: Enables or disables column FPN correction
Seqmode3[5:3]: Enables or disables, and sets the number of
frames grabbed in nondestructive readout mode.
'000': Invalid
'001': Default, 1 reset, 1 sample
'010': 1reset, 2 samples
'011': 1 reset, 3 samples
Document Number: 001-24599 Rev. *B
"11": functional test mode
Seqmode4[7]: Enables (1) and disables (0) reverse Y read out.
X1_start (61, 6bit). This register sets the X start address for
window 1 (default window).
Y1_end (62 and 63, 10 bit). These registers set the Y end
address for window 1 (default window).
X1_kernels (63, 6 bit). This register sets the number of kernels
or X width to be read out for window 1 (default window).
Y2_start (64 and 65, 10 bit). These registers set the Y start
address for window 2 (if enabled).
X2_start (65, 6bit). This register sets the X start address for
window 2 (if enabled).
Y2_end (66 and 67, 10 bit). These registers set the Y end
address for window 2 (if enabled).
X2_kernels (67, 6 bit). This register sets the number of kernels
or X width to be read out for window 2 (if enabled).
Y3_start (68 and 69, 10 bit). These registers set the Y start
address for window 3 (if enabled).
X3_start (69, 6bit). This register sets the X start address for
window 3 (if enabled).
Y3_end (70 and 71, 10 bit). These registers set the Y end
address for window 3 (if enabled).
X3_kernels (71, 6 bit). This register sets the number of kernels
or X width to be read out for window 3 (if enabled).
Y4_start (72 and 73, 10 bit). These registers set the Y start
address for window 4 (if enabled).
X4_start (73, 6bit). This register sets the X start address for
window 4 (if enabled).
Y4_end (74 and 75, 10 bit). These registers set the Y end
address for window 4 (if enabled).
X4_kernels (75, 6 bit). This register sets the number of kernels
or X width to be read out for window 4 (if enabled).
Page 16 of 41
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Res_length (76 and 77). This register sets the length of the
internal pixel array reset (how long are all pixel reset
simultaneously). This value is expressed in 'number of lines' or
in clock cycles (depends on seqmode3[6]).
Res_dsts_length. This register sets the length of the internal
dual and triple slope reset pulses when enabled. This value is
expressed in 'number of lines' or in clock cycles (depends on
seqmode3[6]).
Tint_timer (79 and 80). This register sets the length of the
integration time. This value is expressed in 'number of lines' or
in clock cycles (depends on seqmode3[6]).
Tint_ds_timer (81 and 82). This register sets the length of the
dual slope integration time. This value is expressed in 'number
of lines' or in clock cycles (depends on seqmode3[6]).
Tint_ts_timer (83 and 84). This register sets the length of the
triple slope integration time. This value is expressed in 'number
of lines' or in clock cycles (depends on seqmode3[6]).
Data Interface (SPI)
The serial 4-wire interface (or Serial to Parallel Interface) uses a
serial input or output to shift the data in or out the register buffer.
The chip's configuration registers are accessed from the outside
world through the SPI protocol. A 4-wire bus runs over the chip
and connects the SPI I/Os with the internal register blocks.
The interface consists of:
■
cs_n: chip select, when LOW the chip is selected
■
clk: the spi clock
■
in: Master out, Slave in, the serial input of the register
■
out: Master in, Slave out, the serial output of the register
SPI Protocol
The information on the data 'in' line is:
■
A command bit C, indicating a write ('1') or a read ('0') access
■
7-bit address
■
8-bit data word (in case of a write access)
The data 'out' line is generally in High Z mode, except when a
read request is performed.
Data is always written on the bus on the falling edge of the clock,
and sampled on the rising edge, as seen in Figure 9 and
Figure 10. This is valid for both the 'in' and 'out' bus. The system
clock must be active to keep the SPI uploads stored on the chip.
The SPI clock speed must be slower by a factor of 30 when
compared to the system clock (315 MHz nominal speed).
Figure 9. Write Access (C='1')
The 'out' line is held to High Z. The data for the address A is transferred from the shift register to the active register bank (that is,
sampled) on a rising edge of cs_n. Only the register block with address A can write its data on the 'out' bus. The data on 'in' is ignored.
Figure 10. Read Access (C='0')
Document Number: 001-24599 Rev. *B
Page 17 of 41
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Image Sensor Timing and Readout
The timing of the sensor consists of two parts. The first part is
related to the exposure time and the control of the pixel. The
second part is related to the read out of the image sensor.
Integration and readout are in parallel or triggered. In the first
case, the integration time of frame I is ongoing during the readout
of frame I-1. Figure 11 shows this parallel timing structure.
groups of 24 (12 on rising edge, and 12 on the falling edge of the
internal clock). So in total, 54 kernels of 24 pixels are read out
every line. The internal timing is generated by the sequencer.
The sequencer can operate in two modes: master mode and
slave mode. In master mode, all internal timing is controlled by
the sequencer, based on the SPI settings. In slave mode, the
integration timing is directly controlled by over three pins, and the
readout timing is still controlled by the sequencer. The
seqmode1[1] register of the SPI selects between the master and
slave modes.
The readout of every frame starts with a FOT, during which the
analog value on the pixel diode is transferred to the pixel memory
element. After this FOT, the sensor is read out line by line. The
read out of every line starts with a ROT, during which the pixel
value is put on the column lines. Then the pixels are selected in
Figure 11. Global Readout Timing (Parallel)
Integration frame I+1
Integration frame I+2
Readout frame I
Readout frame I+1
Readout Lines
FOT
L1
L2
...
L1024
ROT
K1
K2
...
K54
Readout Pixels
Pipelined Shutter
Integration and readout occur in parallel and are continuous. You only need to start and stop the batch of image captures.
Integration of frame N is always ongoing during readout of frame N-1. The readout of every frame starts with a FOT, during which the
analog value on the pixel diode is transferred to the pixel memory element. After this FOT, the sensor is read out line by line. The
readout of every line starts with a ROT, during which the pixel value is put on the column lines. Then the pixels are muxed in the correct
ADCs, processed, and then sent to the LVDS output block.
Figure 12. Integration and Readout for Pipelined Shutter
Int. Time
Handling
Readout
Handling
Reset N Exposure Time N
FOT
Readout N-1
FOT
Reset
N+1
Exposure Time
Readout N
ROT
Line Readout
You have two options in the pipelined shutter mode. The first option is to program the reset and integration through the configuration
interface and let the sequencer handle integration time automatically. This mode is called master mode. The second option is to drive
the integration time through an external pin. This mode is called slave mode.
Document Number: 001-24599 Rev. *B
Page 18 of 41
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Programming the Exposure Time
In master mode, the exposure time is configured in two distinct methods (controlled by register seqmode3[6]):
■
#lines: Obvious, changing signals that control integration time. They are always changed during ROT to avoid any image artefacts.
■
#clock cycles: Must be multiplied by (2**seqmode4[3:0]). When the counter expires, changes are put into effect immediately. Asserting
the configuration signal (seqmode3[7]) forces delaying signal updates until the next ROT.
Table 15 lists the user programmable timer settings and how they are interpreted by the hardware.
Table 15. User Programmable Timer Settings
Setting
Granularity
reg_res_length
Lines/cycles
reg_tint_timer
Lines/cycles
reg_tint_ds_timer
Lines/cycles
reg_tint_ts_timer
Lines/cycles
reg_rot_timer
clock cycles
reg_fot_timer
clock cycles
reg_sel_pre_timer
clock cycles
reg_precharge_timer
clock cycles
reg_sample_timer
clock cycles
reg_vmem_timer
clock cycles
reg_delayed_rdt_timer
Lines/cycles
Note that the seqmode3[7] can also be used to sync the user signals in slave mode. The behavior is exactly the same.
Master Mode
In master mode the reset and exposure time is written in registers.
Figure 13. Integration and Image Readout in Master Mode
Ensure that the added value of the registers res_length and tint_timer always exceeds the number of lines that are read out. This is
because the sequencer samples a new image after integration is complete, without checking if image readout is finished. Enlarging
res_length to accommodate for this has no impact on image capture.
Document Number: 001-24599 Rev. *B
Page 19 of 41
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Slave Mode
In slave mode, the register values of res_length and tint_timer are ignored. The integration time is controlled by the int_time pin. The
relationship between the input pin and the integration time is shown in Figure 14. When the input pin int_time is asserted, the pixel
array goes out of reset and exposure can begin. When int_time goes low again and the desired exposure time is reached, the image
is sampled and read out can begin.
Figure 14. Integration and Image Readout in Slave Mode
Changing a pixel's reset level during line readout might result in image artefacts during a small transient period. As a result, it is advised
to only change the value of int_time during ROT.
Triggered Shutter
The two main differences in the pipelined shutter mode are:
■
One single image is read upon every user action.
■
Integration (and read out) is under control of the user through pin int_time.
This means that for every frame, you need to manually intervene. The pixel array is kept in reset state until you assert the int_time
input. Similar to the pipelined shutter mode, there is a master mode in which the sequencer can control the integration time, or a slave
mode in which you can define the integration time.
Figure 15. Integration and Readout for Triggered Shutter
int_time1
Int. Time
Handling
Reset Exposure Time N
Reset
Readout
Handling
FOT
Readout N
Exposure Time N Reset
FOT
Read
outN+1
N+1
ROT
Line
Readout
The possible applications for this triggered shutter mode are:
■
Synchronize external flash with exposure
■
Apply extremely long integration times (only in slave mode)
Document Number: 001-24599 Rev. *B
Page 20 of 41
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Master Mode
Slave Mode
In this mode, a rising edge on int_time1 pin is used to trigger the
start of integration and read out. The tint_timer defines the
integration time independent of the assertion of the input pin
int_time1. After the integration time counter runs out, the FOT
automatically starts and the image readout is done. During
readout, the image array is kept in reset. A request for a new
frame is started again when a new rising edge on int_time is
detected. The time of the falling edge is not important in this
mode.
Integration time control is identical to the pipelined shutter slave
mode. The int_time1 pin controls the start of integration. When
int_time is deasserted, the FOT starts (analog value on the pixel
diode is transferred to the pixel memory element). Only at that
time, image read out can start (similar to the pipelined read out).
During read out, the image array is kept in reset. A request for a
new frame is started when int_time goes high again.
Windowing
A fully configurable window can be selected for readout.
Figure 16. Window Selected for Readout
y start
1024 pixels
y_end
x kernel
x start
1280 pixels
The parameters to configure this window are:
x_start. The sensor reads out 24 pixels in one single clock cycle.
The granularity of configuring the X start position is also 24.
Every value written to the windowX_2 register must be multiplied
by 24 to find the corresponding column in the pixel array.
x_kernels. The number of columns that is read out
(x_kernels*24 in full frame mode) in subsampling mode
x_kernels*48 represents the number of columns over which
subsampling is done. The x_kernels value must be written to the
windowX_4 register.
y_end. The end line of the readout window, granularity of 1. In
all cases (even in reverse scan), y_end are larger than y_start.
Note that in subsample mode, the correct y_end position must
be uploaded (exact value depends on color or B/W subsampling
mode). This value must be written to the windowX_3 and
windowX_4 register.
In case of windowing, the effective readout time is smaller than
in full frame mode, because only the relevant part of the image
array is accessed. As a result, it is possible to achieve higher
frame rates.
y_start. The starting line of the readout window, granularity of 1.
Note that in subsample mode, the correct y_start position must
be uploaded (exact value depends on color or B/W subsampling
mode). This value must be written to the windowX_1 and
windowx_2 register.
Document Number: 001-24599 Rev. *B
Page 21 of 41
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Reverse Scan
Reverse scanning is supported in the X and Y direction. Line 0 (first line on the output) is the top line in normal mode and the bottom
line in reverse scanning, as shown in Figure 17. As a result, the line numbers always increment. When reverse scanning in X, the
operation is analogous. To enable reverse readout in X and Y, set the seqmode4[6:7] bits. In addition, the Y_start and X_start
addresses must be changed to the new starting address.
Figure 17. Normal and Reverse Scanning in Y
Multiple Windows
The sequencer supports the readout of four different windows, randomly positioned over the pixel array. The images are read out
sequentially. That is, window 1 is read out before window 2, even if both windows show some overlap. Next, windows 3 and 4 are
read out. You can configure the number of windows used in the application (one to four). Figure 18 shows how to configure two
windows spread over the image array.
Figure 18. Multiple Windows Read from the Same Pixel Array
Document Number: 001-24599 Rev. *B
Page 22 of 41
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CYIL2SM1300AA
Figure 19 shows the sequence of integration and read out for multiple windows. The handling of integration time is identical to the
single window mode (except that in this case, the maximum integration time is equal to the sum of the y_widths of the two windows).
Read out starts with a FOT that is similar to single window mode. After the FOT, all lines of window 1 are read, followed by the lines
of window 2.
Figure 19. Exposure and Read Out of Multiple Windows
Int. Time
Handling
Readout
Handling
Reset N
FOT
Reset
N+1
Exposure Time N
Readout N-1
Readout
FOT
N-1
Exposure Time
Readout N
Readout N
Window
2
Window 1
Window 2
ROT
Line Readout Window 1
Line Readout Window 2
If the X size of the windows are not identical, the integration time
in function of the number of lines read presents multiple slopes
(proportional to the X size of these windows). Because this can
cause confusion when programming the integration time, it is
easier to configure all timer registers using the clock cycle
configuration instead of the 'line' configuration.
Multiple Slopes
Dynamic range can be extended by the multiple slope
capabilities of the sensor. The four colored lines in Figure 20
represent analog signals of the photodiode of four pixels, which
decrease as a result of exposure. The slope is determined by the
amount of light at each pixel (the more light, the steeper the
slope). When the pixels reach the saturation level, the analog
does not change despite further exposure. Without the multiple
slope capabilities, the pixels p3 and p4 are saturated before the
end of the exposure time, and no signal is received. However,
when using multiple slopes, the analog signal is reset to a
second or third reset level (lower than the original) before the
integration time ends. The analog signal starts decreasing with
the same slope as before, and pixels that were saturated before
could be nonsaturated at read out time. For pixels that never
reach any of the reset levels (for example, p1 and p2) there is no
difference between single and multiple slope operation.
By choosing the time stamps of the double and triple slope resets
(typical at 90% and 99% of the integration, configurable by the
user), it is possible to have a nonsaturated pixel value even for
pixels that receive a huge amount of light.
Figure 20. Dynamic Range Extended by Multiple Slope Capability
t
Document Number: 001-24599 Rev. *B
Page 23 of 41
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CYIL2SM1300AA
The reset levels are configured through external (power) pins. In master mode, the time stamps of the double and triple slope resets
are configured in a method similar to configuring the exposure time. The time stamps are enabled through the registers seqmode1[5]
and seqmode1[6], and their values are expressed in line or clock cycles in the registers reg_tint_ds_timer and reg_tint_ts_timer.
Figure 21. Triple Slope Timing in Master Mode
In slave mode, the values of res_length, tint_timer, tint_DS_timer, and tint_TS_timer in the configuration registers are ignored. You
have full control through the pins int_time, int_time_ds, and int_time_ts. You must configure the multiple slope parameters for the
application and interpret the pixel data accordingly.
Figure 22. Triple Slope Timing in Slave Mode
Document Number: 001-24599 Rev. *B
Page 24 of 41
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CYIL2SM1300AA
Column FPN Correction
■
The column FPN of the sensor is improved by the offset
correction of the columns. At the start of every frame, before read
out of the actual lines is done, a fixed voltage is applied at the
columns and these values are read out like a real data line. Inside
the data block, the 'pixel' data for that line is stored in an on-chip
FPN memory. When the correction is enabled, the corresponding
FPN value is subtracted from the incoming pixel data.
This FPN correction must be enabled for every output separately.
The registers used to configure the correction are:
datachannelX_1 with X from 0 to 11. The field [1] of these
registers enables the offset corrections of the specific output
channel.
Note Do not change the settings of datachannel12_1. This
channel contains synchronization data, not pixel data. If fpn
correction is enabled on this channel, the synchronization data
becomes corrupt.
■
seqmode3. The field[2] must be '1'. It enables the generation
of the line of reference voltages at the columns.
Figure 23 and Figure 24 show the effect of enabling the column
FPN correction. These images are magnified up to five times.
Figure 23. Dark Image Without FPN Correction (5x Amplified)
Figure 24. Dark Image With FPN Correction Enabled (5x Amplified)
Document Number: 001-24599 Rev. *B
Page 25 of 41
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CYIL2SM1300AA
Image Format and Read Out Protocol
The active area read out by the sequencer in full frame mode is shown in Figure 25. Before the actual pixels are read out, one dummy
line is read to enable column FPN calibration. A reference voltage is applied to the columns and the entire line is read as if real pixel
values are placed on the columns.
Pixels are always read in multiples of 24 (one value to every channel in the AFE). The last time slot contains not only valid pixels, but
also two dummy columns, six grey columns, and eight black columns.
Figure 25. Sensor Read Out Format
Document Number: 001-24599 Rev. *B
Page 26 of 41
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CYIL2SM1300AA
The following sections discuss the appearance of the output (data and synchronization codes) in several relevant configurations.
Twelve output channels are connected to the 24 ADCs and handle the data. One additional channel contains all the synchronization
codes for the receiver. This indicates, for example, the start of a frame, the end of a frame, whether the data channels contain data,
CRC, a training pattern, and so on. The sequencer provides the synchronization channel with the correct synchronization or protocol
signals, as shown in Figure 26. The synchronization codes are listed in Table 16. Note that a FS also serves as LS, and vice versa.
Figure 26. Data and Sync Channel Overview
Table 16. Synchronization Codes
Sync code
Abbreviation
10-Bit Code
Frame Start
FS
0x059
Line Start
LS
0x056
Frame End
FE
0x05A
Line End
LE
0x055
Grey/Black Cols
GBC
0x0A9
CRC
CRC
0x0A6
FPN stored values
FPN
0x13C
Normal Data
D
0x193
Training Pattern
T
T
Document Number: 001-24599 Rev. *B
Page 27 of 41
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CYIL2SM1300AA
Full Frame Mode
In this operation mode, the entire sensor shown in Figure 25 on page 26 is read out. Figure 27 shows the internal state of the
sequencer, and the behavior of the data and sync channels (overview and detail of one line).
Figure 27. Full Frame Mode Read Out
Sequencer
internal state
FOT ROT
black
ROT line 0
ROT
line
line 1
line
ROT
1022
1023
Data channel
Sync Channel
Data Channel
T
Sync Channel
T
T
FS
D
D
D
D
D
D
D
L
E
timeslot timeslot timeslot
1
Document Number: 001-24599 Rev. *B
2
3
GB CR
C
T
C
timeslot timeslot
CRC
53
54
timeslot
Page 28 of 41
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CYIL2SM1300AA
This table provides a detailed overview of remapping one full row read out.
Table 17. Remapping Scheme for One Row
timeslot
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
ch8
ch9
ch10
ch11
1a
0
2
4
6
8
10
12
14
16
18
20
22
1b
1
3
5
7
9
11
13
15
17
19
21
23
2a
47
45
43
41
39
37
35
33
31
29
27
25
2b
46
44
42
40
38
36
34
32
30
28
26
24
3a
48
50
52
54
56
58
60
62
64
66
68
70
3b
49
51
53
55
57
59
61
63
65
67
69
71
4a
95
93
91
89
87
85
83
81
79
77
75
73
4b
94
92
90
88
86
84
82
80
78
76
74
72
5a
96
98
100
102
104
106
108
110
112
114
116
118
5b
97
99
101
103
105
107
109
111
113
115
117
119
6a
143
141
139
137
135
133
131
129
127
125
123
121
6b
142
140
138
136
134
132
130
128
126
124
122
120
7a
144
146
148
150
152
154
156
158
160
162
164
166
7b
145
147
149
151
153
155
157
159
161
163
165
167
8a
191
189
187
185
183
181
179
177
175
173
171
169
8b
190
188
186
184
182
180
178
176
174
172
170
168
9a
192
194
196
198
200
202
204
206
208
210
212
214
9b
193
195
197
199
201
203
205
207
209
211
213
215
10a
239
237
235
233
231
229
227
225
223
221
219
217
10b
238
236
234
232
230
228
226
224
222
220
218
216
11a
240
242
244
246
248
250
252
254
256
258
260
262
11b
241
243
245
247
249
251
253
255
257
259
261
263
12a
287
285
283
281
279
277
275
273
271
269
267
265
12b
286
284
282
280
278
276
274
272
270
268
266
264
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
53a
1248
1250
1252
1254
1256
1258
1260
1262
1264
1266
1268
1270
53b
1249
1251
1253
1255
1257
1259
1261
1263
1265
1267
1269
1271
54a
1295
1293
1291
1289
1287
1285
1283
1281
1279
1277
1275
1273
54b
1294
1292
1290
1288
1286
1284
1282
1280
1278
1276
1274
1272
CRC
Document Number: 001-24599 Rev. *B
Page 29 of 41
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CYIL2SM1300AA
Single Window Mode Containing Timeslot 54
In this operation mode, only part of the sensor is read out, as shown by the shaded area in Figure 28. A clear distinction is made with
the single window mode that does not contain the timeslot 54, because the output synchronization protocol is slightly different.
Figure 28. Single Window Containing Timeslot 54
Figure 29 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line)
for this window mode.
Figure 29. Waveform for Single Window Containing Timeslot 54
Sequencer internal state
FOT ROT
black
ROT line Ys
ROT Line
Ys+1
ROTline
Ye
Data Channel
Sync Channel
Data Channel
Sync Channel
T
T
T
L D
S
D
D
timeslot timeslot
X
X+1
Document Number: 001-24599 Rev. *B
D
D
F GB CR
E C C
T
timeslot timeslot CRC
53
54 timeslot
Page 30 of 41
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CYIL2SM1300AA
Single Window Mode Not Containing Timeslot 54
In this operation mode, only part of the sensor is read out, as shown in Figure 30. Although the window is defined as not containing
any data from timeslot 54, it is read out to provide information on grey and black columns to the user. This results in some minor
differences between the waveforms from Figure 29 on page 30 and Figure 31.
Figure 30. Single Window Not Containing Timeslot 54
Figure 31 shows the internal state of the sequencer, and the behavior of the data and sync channels (overview and detail of one line)
for this window mode.
Figure 31. Waveform for Single Window NOT Containing Timeslot 54
Sequencer
internal state
black
FOT ROT
ROT line Ys
ROT
line
Ys+1
ROTline
Ye
Data Channel
Sync Channel
T
T
T
L
S
D
D
D
timeslot timeslot
Xstart
D
D
D
L
E
T GB CR
C C
T
timeslot timeslot timeslot CRC
Xend-1 Xend
54 timeslot
Note that the dummy black line is read completely.
Reading out multiple windows does not differ from combining the windowed modes in sections Single Window Mode Containing
Timeslot 54 on page 30 and Single Window Mode Not Containing Timeslot 54. The dummy black line again spans the entire width of
the sensor and is processed only once, before all configured windows are read. The dummy black line is independent of the window
sizes.
Document Number: 001-24599 Rev. *B
Page 31 of 41
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CYIL2SM1300AA
Pin List
Table 18. Pin Placement Layout (Top View)
1
13
14
15
16
17
18
19
20
21
22
23 24
A 134 130 127 124 121 118 115 112 109 106 103 100 99
96
93
90
87
84
81
78
75
72
69 65
B
131 128 125 122 119 116 113 110 107 104 101 98
95
92
89
86
83
80
77
74
71
68
C 133 132 129 126 123 120 117 114 111 108 105 102 97
94
91
88
85
82
79
76
73
70
67 66
*
31
29
*
43
41
*
54
62
60
59 64
*
2
3
4
5
6
7
8
9
10
11
12
*
D
E
F
G
H
J
K
TOP VIEW
L
M
N
P
Q
R
S
T 135 139 140 137 145
*
5
U 136 144 141 138 146
*
8
V 149 147 142
*
1
3
9
W 150 148 143
*
2
4
10
12
Document Number: 001-24599 Rev. *B
7
*
17
19
*
6
*
20
18
*
*
30
32
*
42
44
*
53
61
55
58 63
11
13
15
21
23
25
27
33
35
37
39
45
47
*
52
57 50
14
16
22
24
26
28
34
36
38
40
46
48
*
51
56 49
Page 32 of 41
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CYIL2SM1300AA
Table 19. Pin List
Type
Direction
1
nr
clkoutp
Pin Name
LVDS
O
p clk output channel
Description
V5
Position
2
clkoutn
LVDS
O
n clk output channel
W5
3
chp[0]
LVDS
O
p output channel [0]
V6
4
chn[0]
LVDS
O
n output channel [0]
W6
5
gndlvds
Supply
I/O
LVDS ground
T7
6
gndadc
Supply
I/O
ADC ground
U8
7
vddadc
Supply
I/O
ADC power
T8
8
vddlvds
Supply
I/O
LVDS power
U7
9
chp[1]
LVDS
O
p output channel [1]
V7
10
chn[1]
LVDS
O
n output channel [1]
W7
11
chp[2]
LVDS
O
p output channel [2]
V8
12
chn[2]
LVDS
O
n output channel [2]
W8
13
chp[3]
LVDS
O
p output channel [3]
V9
14
chn[3]
LVDS
O
n output channel [3]
W9
15
chp[4]
LVDS
O
p output channel [4]
V10
16
chn[4]
LVDS
O
n output channel [4]
W10
17
gndlvds
Supply
I/O
LVDS ground
T10
18
gndadc
Supply
I/O
ADC ground
U11
19
vddadc
Supply
I/O
ADC power
T11
20
vddlvds
Supply
I/O
LVDS power
U10
21
chp[5]
LVDS
O
p output channel [5]
V11
22
chn[5]
LVDS
O
n output channel [5]
W11
23
chp[6]
LVDS
O
p output channel [6]
V12
24
chn[6]
LVDS
O
n output channel [6]
W12
25
chp[7]
LVDS
O
p output channel [7]
V13
26
chn[7]
LVDS
O
n output channel [7]
W13
27
chp[8]
LVDS
O
p output channel [8]
V14
28
chn[8]
LVDS
O
n output channel [8]
W14
29
gndlvds
Supply
I/O
LVDS ground
T15
30
gndadc
Supply
I/O
ADC ground
U14
31
vddadc
Supply
I/O
ADC power
T14
32
vddlvds
Supply
I/O
LVDS power
U15
33
chp[9]
LVDS
O
p output channel [9]
V15
34
chn[9]
LVDS
O
n output channel [9]
W15
35
chp[10]
LVDS
O
p output channel [10]
V16
36
chn[10]
LVDS
O
n output channel [10]
W16
37
chp[11]
LVDS
O
p output channel [11]
V17
38
chn[11]
LVDS
O
n output channel [11]
W17
39
n/a
not assigned
V18
40
n/a
not assigned
W18
41
gndlvds
Supply
I/O
LVDS ground
T18
42
gndadc
Supply
I/O
ADC ground
U17
Document Number: 001-24599 Rev. *B
Page 33 of 41
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CYIL2SM1300AA
Table 19. Pin List (continued)
nr
Pin Name
Type
Direction
Description
Position
43
vddadc
Supply
I/O
ADC power
T17
44
vddlvds
Supply
I/O
LVDS power
U18
45
clkinp
LVDS
I
LVDS input clock 315 MHz p-node
V19
46
clkinn
LVDS
I
LVDS input clock 315 MHz n-node
W19
47
syncp
LVDS
O
LVDS sync and output
V20
48
syncn
LVDS
O
LVDS sync and output
W20
49
gnddig
Supply
I/O
digital ground
W24
50
vdddig
Supply
I/O
digital power supply
V24
51
cap_vrefm
Analog
O
lower limit ADC range decoupling
W22
52
cap_vrefp
Analog
O
higher limit ADC range decoupling
V22
53
gndadc
Supply
I/O
ADC ground
U20
54
vddadc
Supply
I/O
ADC power supply
T20
55
gnddig
Supply
I/O
digital ground
U22
56
gndbuf
Supply
I/O
column buffers ground
W23
57
vddbuf
Supply
I/O
column buffers supply
V23
58
gndana
Supply
I/O
column buffers ground
U23
59
vddana
Supply
I/O
column buffers supply
T23
60
vpix
Supply
I/O
pixel core supply
T22
61
gndpix
Supply
I/O
pixel core ground
U21
62
vsamp
Supply
I/O
image core select and sample supply
T21
63
gndadc
Supply
I/O
ADC ground
U24
64
vdddig
Supply
I/O
digital power supply
T24
65
nbias_colload
Analog
O
column bias decouple
A24
66
test_ena
CMOS
I
scan pin for sequencer
C24
67
int_time1
CMOS
I
integration pin first slope
C23
68
int_time2
CMOS
I
integration pin dual slope
B23
69
int_time3
CMOS
I
integration pin triple slope
A23
70
monitor1
CMOS
O
output pin for integration timing, high during integration
C22
71
monitor2
CMOS
O
output pin for dual slope integration timing, high during
integration
B22
72
monitor3
CMOS
O
output pin for triple slope integration timing, high during
integration
A22
73
cap_vrefadc
Analog
O
ADC black reference decoupling
C21
74
vpix
Supply
I/O
pixel core supply
B21
75
cap_vrefcm
Analog
O
ADC common mode decoupling
A21
76
reset_n
CMOS
I/O
chip reset (active low)
C20
77
scan_en
CMOS
I
DFT scan enable
B20
78
scan_clk
CMOS
I
DFT clock
A20
79
scan_clk_en
CMOS
I
DFT clock enable
C19
80
gndpix
Supply
I/O
pixel core ground
B19
81
gnddig
Supply
I/O
digital ground
A19
82
vdddig
Supply
I/O
digital power supply
C18
83
vpix
Supply
I/O
pixel core supply
B18
Document Number: 001-24599 Rev. *B
Page 34 of 41
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CYIL2SM1300AA
Table 19. Pin List (continued)
nr
Pin Name
Type
Direction
Description
Position
84
pixdiode
Analog
O
pixel diode current pin
A18
85
gndpix
Supply
I/O
pixel core ground
C17
86
vsamp
Supply
I/O
image core select and sample supply
B17
87
vresetab
Supply
I/O
anti blooming lower reset level
A17
88
vprech
Supply
I/O
pixel precharge level/decoupling pin
C16
89
vmemh
Supply
I/O
pixel memory reference high
B16
90
vmeml
Supply
I/O
pixel memory reference low
A16
91
vreset
Supply
I/O
pixel reset level
C15
92
vresetds
Supply
I/O
pixel dual slope reset level/decoupling pin
B15
93
vresetts
Supply
I/O
pixel triple slope reset level/decoupling pin
A15
94
vresetab
Supply
I/O
anti blooming lower reset level
C14
95
gndpix
Supply
I/O
pixel core ground
B14
96
vresetts
Supply
I/O
pixel triple slope reset level/decoupling pin
A14
97
vresetds
Supply
I/O
pixel dual slope reset level/decoupling pin
C13
98
vreset
Supply
I/O
pixel reset level
B13
99
vsamp
Supply
I/O
image core select and sample supply
A13
100
vmeml
Supply
I/O
pixel memory reference low
A12
101
vmemh
Supply
I/O
pixel memory reference high
B12
102
vprech
Supply
I/O
pixel precharge level/decoupling pin
C12
103
n/a
not assigned
A11
104
gndpix
Supply
I/O
pixel core ground
B11
105
vresetab
Supply
I/O
anti blooming lower reset level
C11
106
vresetts
Supply
I/O
pixel triple slope reset level/decoupling pin
A10
107
vresetds
Supply
I/O
pixel dual slope reset level/decoupling pin
B10
108
vreset
Supply
I/O
pixel reset level
C10
109
vmeml
Supply
I/O
pixel memory reference low
A9
110
vmemh
Supply
I/O
pixel memory reference high
B9
111
vprech
Supply
I/O
pixel precharge level/decoupling pin
C9
112
vresetab
Supply
I/O
anti blooming lower reset level
A8
113
vsamp
Supply
I/O
image core select and sample supply
B8
114
gndpix
Supply
I/O
115
ibiaspre
Analog
I
pixel core ground
C8
external current bias for vprech (not connected by default)
A7
116
vpix
Supply
I/O
pixel core supply
B7
117
vdddig
Supply
I/O
digital power supply
C7
118
gnddig
Supply
I/O
digital ground
A6
119
gndpix
Supply
I/O
pixel core ground
B6
120
n/a
not assigned
C6
121
n/a
not assigned
A5
122
n/a
not assigned
B5
123
n/a
not assigned
C5
124
cap_vrefcm
Analog
O
ADC common mode decoupling
A4
125
vpix
Supply
I/O
pixel core supply
B4
126
cap_vrefadc
Analog
O
ADC black reference decoupling
C4
Document Number: 001-24599 Rev. *B
Page 35 of 41
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CYIL2SM1300AA
Table 19. Pin List (continued)
nr
Pin Name
Type
Direction
Description
Position
127
spics
CMOS
I
SPI chip select
A3
128
spiclk
CMOS
I
SPI clock
B3
129
spiin
CMOS
I
SPI serial input
C3
130
spiout
CMOS
O
SPI serial output
A2
131
mbsbus[0]
Analog
I/O
first mixed boundary scan bus
B2
132
mbsbus[1]
Analog
I/O
second mixed boundary scan bus
C2
133
refbg
Analog
I/O
134
cmdmbs
Analog
I
external bias resistor
C1
bias current for mbs buffers
A1
135
vdddig
Supply
136
gndadc
Supply
I/O
digital power supply
T1
I/O
ADC ground
U1
137
vsamp
Supply
I/O
image core select and sample supply
T4
138
gndpix
Supply
I/O
pixel core ground
U4
139
vpix
Supply
I/O
pixel core supply
T2
140
vddana
Supply
I/O
analog power supply
T3
141
gndana
Supply
I/O
analog ground
U3
142
vddbuf
Supply
I/O
column buffers supply
V3
143
gndbuf
Supply
I/O
column buffers ground
W3
144
gnddig
Supply
I/O
digital ground
U2
145
vddadc
Supply
I/O
ADC power supply
T5
146
gndadc
Supply
I/O
ADC ground
U5
147
cap_vrefp
Analog
I/O
higher limit ADC range decoupling
V2
148
cap_vrefm
Analog
I/O
lower limit ADC range decoupling
W2
149
vdddig
Supply
I/O
digital power supply
V1
150
gnddig
Supply
I/O
digital ground
W1
Document Number: 001-24599 Rev. *B
Page 36 of 41
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CYIL2SM1300AA
Package Information
Figure 32. Package Outline Drawing with Glass
001-44705 **
The total distance from the bottom of the µPGA package (same as the PCB plane) to the top of the die surface is 19.016 mm.
Document Number: 001-24599 Rev. *B
Page 37 of 41
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CYIL2SM1300AA
Figure 33. Pixel Active Area Dimensions
Package with Glass Cross Section
Figure 34. Package Cross Section
Document Number: 001-24599 Rev. *B
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CYIL2SM1300AA
Die Specifications
Figure 35. Die Specifications
1700 ±
50 um
1450
± 50
um
Document Number: 001-24599 Rev. *B
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CYIL2SM1300AA
Glass Lid
The LUPA 1300-2 monochrome and color image sensor uses a glass lid without any coatings. Figure 36 shows the transmission
characteristics of the glass lid.
As seen in Figure 36, no infrared attenuating color filter glass is used. You must provide this filter in the optical path when color devices
are used.
Figure 36. Transmission Characteristics of the Glass lid
Handling Precautions
Application Note References
For proper handling and storage conditions, refer to the Cypress
application note AN52561 at www.cypress.com.
■
Limited Warranty
Cypress Image Sensor Business Unit warrants that the image
sensor products mentioned here, if properly used and serviced,
conform to the seller's published specifications. They are free
from defects in material and workmanship for one (1) year
following the date of shipment.
Document Number: 001-24599 Rev. *B
AN54468: Interfacing the LUPA1300-2 with FPGA.
This application note describes the interface between the LUPA
1300-2 and the FPGA, as implemented in the LUPA 1300-2
demonstration kit CYIL2SM1300-EVAL. It also provides an
overview of the architecture of the demonstration kit and the
method used to synchronize channels.
■
AN54214: High Speed Layout Guidelines for the LUPA 1300-2
Image Sensor
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CYIL2SM1300AA
Document History Page
Document Title: CYIL2SM1300AA LUPA 1300-2: High Speed CMOS Image Sensor
Document Number: 001-24599
Revision
ECN
Orig. of Change
Submission Date
Description of Change
**
1438663
FPW
09/04/07
*A
2649816
NVEA/AESA
03/17/2009
Updated parameters in Table 5 on page 5.
Updated data sheet template.
Added Handling Precautions section.
Initial Cypress release.
*B
2745961
NVEA/AESA
07/29/2009
Updated “Features” on page 1, “Description” on page 1, and
“Overview” on page 2
Updated Table 1 on page 1
Updated Table 14 on page 10
Modified “Handling Precautions” on page 40
Added “Application Note References” on page 40
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications.
Consumer applications include solutions for fast growing high speed machine vision, motion monitoring, medical imaging, intelligent
traffic systems, security, and barcode applications. Cypress's customized CMOS image sensors are characterized by very high pixel
counts, large area, very high frame rates, large dynamic range, and high sensitivity.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. For more
information on Image sensors, please contact [email protected]
© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-24599 Rev. *B
Revised July 24, 2009
Page 41 of 41
All products and company names mentioned in this document may be the trademarks of their respective holders.
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