Order this document by SG3525A/D The SG3525A, SG3527A pulse width modulator control circuits offer improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on–chip +5.1 V reference is trimmed to ±1% and the error amplifier has an input common–mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. These devices also feature built–in soft–start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft–start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft–start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft–start capacitor when VCC is below nominal. The output stages are totem–pole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an off–state while the SG3527A utilized OR logic which gives a high output when off. • 8.0 V to 35 V Operation • • • • • • • • 5.1 V ± 1.0% Trimmed Reference PULSE WIDTH MODULATOR CONTROL CIRCUITS SEMICONDUCTOR TECHNICAL DATA N SUFFIX PLASTIC PACKAGE CASE 648 16 1 DW SUFFIX PLASTIC PACKAGE CASE 751B (SO–16L) 16 1 100 Hz to 400 kHz Oscillator Range Separate Oscillator Sync Pin Adjustable Deadtime Control PIN CONNECTIONS Input Undervoltage Lockout Latching PWM to Prevent Multiple Pulses Pulse–by–Pulse Shutdown Dual Source/Sink Outputs: ±400 mA Peak Inv. Input 1 16 Vref Noninv. Input 2 15 VCC Sync 3 14 Output B OSC. Output 4 13 VC CT 5 12 Ground RT 6 11 Output A Discharge 7 10 Shutdown Soft–Start 8 9 Representative Block Diagram 16 Vref 15 Reference Regulator VCC 12 VC 13 To Internal Circuitry Under– Voltage Lockout Ground OSC Output NOR 4 3 Sync RT Output A CT F/F Oscillator Q NOR Output B R 1 INV. Input 2 Noninv. Input – Error Amp + + – PWM – S Latch VREF 10 ORDERING INFORMATION Output A S 50µA 8 SG3525A Output Stage 13 VC OR 11 Device CSoft–Start Shutdown (Top View) 14 7 9 Compensation Compensation Q 6 5 Discharge 11 5.0k Operating Temperature Range Package Output B SG3525AN 5.0k OR Plastic DIP 14 SG3525ADW SG3527A Output Stage TA = 0° to +70°C SG3527AN Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA SO–16L Plastic DIP Rev 2 1 SG3525A SG3527A MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit VCC +40 Vdc VC +40 Vdc Logic Inputs –0.3 to +5.5 V Analog Inputs –0.3 to VCC V ±500 mA 50 mA 5.0 mA Supply Voltage Collector Supply Voltage Output Current, Source or Sink IO Reference Output Current Iref Oscillator Charging Current Power Dissipation (Plastic & Ceramic Package) TA = +25°C (Note 2) TC = +25°C (Note 3) PD mW 1000 2000 Thermal Resistance Junction–to–Air RθJA 100 °C/W Thermal Resistance Junction–to–Case RθJC 60 °C/W TJ +150 °C Tstg –55 to +125 °C TSolder +300 °C Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 seconds) NOTES: 1. Values beyond which damage may occur. 2. Derate at 10 mW/°C for ambient temperatures above +50°C. 3. Derate at 16 mW/°C for case temperatures above +25°C. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit VCC 8.0 35 Vdc Collector Supply Voltage VC 4.5 35 Vdc Output Sink/Source Current (Steady State) (Peak) IO 0 0 ±100 ±400 Reference Load Current Iref 0 20 mA Oscillator Frequency Range fosc 0.1 400 kHz Oscillator Timing Resistor RT 2.0 150 kΩ Oscillator Timing Capacitor CT 0.001 0.2 µF Deadtime Resistor Range RD 0 500 Ω Operating Ambient Temperature Range TA 0 +70 °C Supply Voltage mA APPLICATION INFORMATION Shutdown Options (See Block diagram, front page) Since both the compensation and soft–start terminals (Pins 9 and 8) have current source pull–ups, either can readily accept a pull–down signal which only has to sink a maximum of 100 µA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM 2 latch is immediately set providing the fastest turn–off signal to the outputs; and a 150 µA current sink begins to discharge the external soft–start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft–start capacitor, thus, allowing, for example, a convenient implementation of pulse–by–pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn–on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. MOTOROLA ANALOG IC DEVICE DATA SG3525A SG3527A ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.) Symbol Min Typ Max Unit Reference Output Voltage (TJ = +25°C) Vref 5.00 5.10 5.20 Vdc Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline – 10 20 mV Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload – 20 50 mV Temperature Stability ∆Vref/∆T – 20 – mV ∆Vref 4.95 – 5.25 Vdc Short Circuit Current (Vref = 0 V, TJ = +25°C) ISC – 80 100 mA Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25°C) Vn – 40 200 µVrms Long Term Stability (TJ = +125°C) (Note 5) S – 20 50 mV/khr – ±2.0 ±6.0 % Characteristics REFERENCE SECTION Total Output Variation Includes Line and Load Regulation over Temperature OSCILLATOR SECTION (Note 6, unless otherwise noted.) Initial Accuracy (TJ = +25°C) Frequency Stability with Voltage (+8.0 V ≤ VCC ≤ +35 V) ∆fosc D VCC – ±1.0 ±2.0 % Frequency Stability with Temperature ∆fosc D T – ±0.3 – % Minimum Frequency (RT = 150 kΩ, CT = 0.2 µF) fmin – 50 – Hz Maximum Frequency (RT = 2.0 kΩ, CT = 1.0 nF) fmax 400 – – kHz Current Mirror (IRT = 2.0 mA) 1.7 2.0 2.2 mA Clock Amplitude 3.0 3.5 – V Clock Width (TJ = +25°C) 0.3 0.5 1.0 µs Sync Threshold 1.2 2.0 2.8 V – 1.0 2.5 mA VIO – 2.0 10 mV Input Bias Current IIB – 1.0 10 µA Input Offset Current IIO – – 1.0 µA DC Open Loop Gain (RL ≥ 10 MΩ) AVOL 60 75 – dB Low Level Output Voltage VOL – 0.2 0.5 V High Level Output Voltage VOH 3.8 5.6 – V Common Mode Rejection Ratio (+1.5 V ≤ VCM ≤ +5.2 V) CMRR 60 75 – dB Power Supply Rejection Ratio (+8.0 V ≤ VCC ≤ +35 V) PSRR 50 60 – dB Minimum Duty Cycle DCmin – – 0 % Maximum Duty Cycle DCmax 45 49 – % Input Threshold, Zero Duty Cycle (Note 6) Vth 0.6 0.9 – V Input Threshold, Maximum Duty Cycle (Note 6) Vth – 3.3 3.6 V Input Bias Current IIB – 0.05 1.0 µA Sync Input Current (Sync Voltage = +3.5 V) ERROR AMPLIFIER SECTION (VCM = +5.1 V) Input Offset Voltage PWM COMPARATOR SECTION NOTES: 4. Tlow = 0° for SG3525A, 3527A Thigh = +70°C for SG3525A, 3527A 5. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 6. Tested at fosc = 40 kHz (RT = 3.6 kΩ, CT = 0.01 µF, RD = 0Ω). MOTOROLA ANALOG IC DEVICE DATA 3 SG3525A SG3527A ELECTRICAL CHARACTERISTICS (Continued) Characteristics Symbol Min Typ Max Unit Soft–Start Current (Vshutdown = 0 V) 25 50 80 µA Soft–Start Voltage (Vshutdown = 2.0 V) – 0.4 0.6 V Shutdown Input Current (Vshutdown = 2.5 V) – 0.4 1.0 mA – – 0.2 1.0 0.4 2.0 18 17 19 18 – – 7.0 8.0 V SOFT–START SECTION OUTPUT DRIVERS (Each Output, VCC = +20 V) Output Low Level (Isink = 20 mA) (Isink = 100 mA) VOL V Output High Level (Isource = 20 mA) (Isource = 100 mA) VOH Under Voltage Lockout (V8 and V9 = High) VUL 6.0 V IC(leak) – – 200 µA Rise Time (CL = 1.0 nF, TJ = 25°C) tr – 100 600 ns Fall Time (CL = 1.0 nF, TJ = 25°C) tf – 50 300 ns Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25°C) tds – 0.2 0.5 µs Supply Current (VCC = +35 V) ICC – 14 20 mA Collector Leakage, VC = +35 V (Note 7) NOTE: 7. Applies to SG3525A only, due to polarity of output pulses. Lab Test Fixture Vref 16 0.1 Clock PWM ADJ. 13 Flip/ Flop 3 O s c i l l a t o r RT 6 Deadtime 1.5k 7 Ramp 0.009 100Ω 5 Out A 11 A 1.0k, 1.0W (2) 14 B 0.001 0.1 VC 0.1 Sync 1.0k VCC 0.1 4 3.0k 15 Reference Regulator Out B Comp 10k 1 = VIO 2 = 1(+) 3 = 1(–) 1 2 – V/I Meter + 4 12 PWM Gnd 0.01 50µA + 2 1 3 2 5.0µF – 5.0k E/A 5.0k + 1 2 3 Softstart 8 1 3 1 2 3 9 10 Vref 2.0k DUT Shutdown MOTOROLA ANALOG IC DEVICE DATA SG3525A SG3527A Figure 1. Oscillator Charge Time versus RT Figure 2. Oscillator Discharge Time versus RD 200 R D , DEAD TIME RESISTOR (Ω ) 500 RT, TIMING RESISTOR (k Ω ) 100 50 * RD = 0 Ω 20 10 5 6 5.0 7 RD * RT 400 300 200 100 CT 2.0 0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 0.2 1 – 2 + CP RZ = 20 k 20 0 10 100 1.0 k 10 k 100 k 1.0 M Figure 5. Oscillator Schematic (SG3525A) 3.5 100 200 2.5 2.0 1.5 Source Sat, (VC–VOH) 1.0 Sink Sat, (VOL) 0.5 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 IO, OUTPUT SOURCE OR SINK CURRENT (A) Figure 6. Error Amplifier Schematic (SG3525A) 15 VCC Q1 Q5 Q8 7.4k Q3 Q3 6 Q6 5 12 50 3.0 16 Q2 20 VCC = +20 V TJ = +25°C 4.0 0 0.01 10 M f, FREQUENCY (Hz) 3 Sync 7 Discharge 10 9 RZ 40 CT 5.0 Figure 4. Output Saturation Characteristics (SG3525A) 60 RT 2.0 Figure 3. Error Amplifier Open Loop Frequency Response 80 Vref 1.0 DISCHARGE TIME (µs) 100 –20 1.0 0.5 CHARGE TIME (µs) V sat , SATURATION VOLTAGE (V) A VOL, VOLTAGE GAIN (dB) 2.0 2.0k Q9 2.0k Ramp To PWM 14k Q11 Q10 25k 5.0pF Q4 Blanking Q14 To Output 400µA 23k Q7 1.0k 1.0k Q12 Gnd MOTOROLA ANALOG IC DEVICE DATA Q13 3.0k 250 Inverting Q1 Input 1 Noninverting Input 2 200µA Q4 Q2 To PWM Comparator 100µA 5.8V 30 9 Compensation 4 OSC Output 5 SG3525A SG3527A Figure 7. SG3525A Output Circuit (1/2 Circuit Shown) 13 VCC VC Q7 Q5 Q9 Q4 Q10 5.0k Vref 11, 14 Q11 Output Q8 Q6 2.0k Q1 Q2 5.0k Clock 10k F/F Q3 Q6 Omitted in SG3527A 10k PWM Figure 8. Single–Ended Supply Figure 9. Push–Pull Configuration Q1 +Vsupply +Vsupply To Output Filter R1 R1 R2 VC A 13 VC A SG3525A 11 Gnd For single–ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem–pole source transistors on alternate oscillator cycles. In conventional push–pull bipolar designs, forward base drive is controlled by R1–R3. Rapid turn–off times for the power devices are achieved with speed–up capacitors C1 and C2. +Vsupply R1 Q1 11 Q1 T1 13 11 SG3525A 14 C1 T1 VC A SG3525A Q2 12 The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. 6 R3 Figure 11. Driving Transformers in a Half–Bridge Configuration Figure 10. Driving Power FETS Gnd B Q2 B 12 12 VC A T1 Q1 R2 C2 14 14 B 13 11 SG3525A Gnd +Vsupply C1 13 Gnd B 12 R1 T2 Q2 14 C2 R2 Low power transformers can be driven directly by the SG3525A. Automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. MOTOROLA ANALOG IC DEVICE DATA SG3525A SG3527A OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S –T– SEATING PLANE K H G D M J 16 PL 0.25 (0.010) T A M M 16 9 1 8 –B– P NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 8 PL 0.25 (0.010) M B S G R K F X 45 _ C SEATING PLANE M D 16 PL 0.25 (0.010) MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 DW SUFFIX PLASTIC PACKAGE CASE 751B–05 (SO–16L) ISSUE J –A– –T– INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 M T B S MOTOROLA ANALOG IC DEVICE DATA A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 7 SG3525A SG3527A Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 8 ◊ *SG3525A/D* MOTOROLA ANALOG IC DEVICE DATA SG3525A/D