19-2130; Rev 2; 11/10 KIT ATION EVALU ABLE AVAIL 10-Bit Bus LVDS Deserializers The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling (BLVDS) data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel data. The serializer/deserializer combination reduces interconnect, simplifies PCB layout, and reduces board size. The MAX9206/MAX9208 receive serial data at 450Mbps and 600Mbps, respectively, over board traces or twisted-pair cables. These devices combine frequency lock, bit lock, and frame lock to produce a parallel-rate clock and word-aligned 10-bit data. Serialization eliminates parallel bus clock-to-data and data-to-data skew. A power-down mode reduces typical supply current to less than 600µA. Upon power-up (applying power or driving PWRDN high), the MAX9206/MAX9208 establish lock after receiving synchronization signals or serial data from the MAX9205/MAX9207. An output enable allows the outputs to be disabled, putting the parallel data outputs and recovered output clock into a highimpedance state without losing lock. Features o Stand-Alone Deserializer (vs. SERDES) Ideal for Unidirectional Links o Automatic Clock Recovery o Allow Hot Insertion and Synchronization Without System Interruption o BLVDS Serial Input Rated for Point-to-Point and Bus Applications o Fast Pseudorandom Lock o Wide Reference Clock Input Range 16MHz to 45MHz (MAX9206) 40MHz to 60MHz (MAX9208) o High 720ps (p-p) Jitter Tolerance (MAX9206) o Low 30mA Supply Current (MAX9206 at 16MHz) o 10-Bit Parallel LVCMOS/LVTTL Output o Up to 600Mbps Throughput (MAX9208) o Programmable Output Strobe Edge o Pin Compatible to DS92LV1212A and DS92LV1224 Ordering Information The MAX9206/MAX9208 operate from a single +3.3V supply and are specified for operation from -40°C to +85°C. The MAX9206/MAX9208 are available in 28-pin SSOP packages. Applications Cellular Phone Base Stations Add/Drop Muxes Digital Cross-Connects TEMP RANGE PART REF CLOCK RANGE (MHz) -40°C to +85°C 28 SSOP 16 to 40 MAX9206EAI/V+ -40°C to +85°C 28 SSOP 16 to 40 MAX9206EAI+ DSLAMs Network Switches and Routers Backplane Interconnect PINPACKAGE -40°C to +85°C 28 SSOP 40 to 66 +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. MAX9208EAI+ Pin Configuration appears at end of data sheet. 100Ω RI+ 100Ω OUT- RIPCB OR TWISTED PAIR OUTPUT LATCH BUS LVDS OUT+ SERIAL-TO-PARALLEL TCLK_R/F PARALLEL-TO-SERIAL 10 IN_ INPUT LATCH Typical Operating Circuit ROUT_ REFCLK TCLK PLL EN PWRDN TIMING AND CONTROL PLL SYNC 1 SYNC 2 10 MAX9205 MAX9207 MAX9206 MAX9208 TIMING AND CONTROL CLOCK RECOVERY REN LOCK RCLK RCLK_R/F ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9206/MAX9208 General Description MAX9206/MAX9208 10-Bit Bus LVDS Deserializers ABSOLUTE MAXIMUM RATINGS AVCC, DVCC to AGND, DGND................................-0.3V to +4V RI+, RI- to AGND, DGND .........................................-0.3V to +4V All Other Pins to DGND ..............................-0.3V to DVCC + 0.3V ROUT_ Short-Circuit Duration (Note 1) ......................Continuous Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C ESD Rating (Human Body Model, RI+, RI-) .........................±8kV Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VAVCC = VDVCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC = VDVCC = +3.3V, VCM = 1.1V, |VID| = 0.2V, TA = +25°C.) (Notes 2, 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 16MHz 30 45 45MHz 57 75 40MHz 55 75 60MHz 80 100 UNITS POWER SUPPLY Supply Current Power-Down Supply Current ICC ICCX CL = 15pF, worst-case pattern, Figure 1 MAX9206 MAX9208 PWRDWN = low 1 mA mA LVCMOS/LVTTL LOGIC INPUTS (REN, REFCLK, RCLK_R/F, PWRDN) High-Level Input Voltage VIH 2.0 VCC V Low-Level Input Voltage VIL 0 0.8 V Input Current I IN -15 15 μA VIN = 0V, VAVCC, or VDVCC LVCMOS/LVTTL LOGIC OUTPUTS (ROUT_, RCLK, LOCK) High-Level Output Voltage VOH I OH = -5mA 2.2 2.9 VCC V Low-Level Output Voltage VOL I OL = 5mA 0 0.33 0.5 V Output Short-Circuit Current I OS VROUT_ = 0V -15 -38 -85 mA I OZ PWRDN = low, VROUT_ = VRCLK = V LOCK = 0V, VAVCC, or VDVCC -1 1 μA Output High-Impedance Current BLVDS SERIAL INPUT (RI+, RI-) Differential Input High VTH Differential Input Low Threshold VTL Input Current IRI+, IRI- Power-Off Input Current IRI+OFF, IRI-OFF 9 -100 100 -9 mV mV 0.1V |VID | 0.45V -64 64 0.45V < |V ID | 0.6V -82 82 0.1V |VID | 0.45V, VAVCC = VDVCC = 0V 0.45V < |V ID | 0.6V, VAVCC = VDVCC = 0V -64 64 -82 82 μA μA Input Resistor 1 RIN1 VAVCC = VDVCC = 3.6V or 0V, Figure 2 4 k Input Resistor 2 RIN2 VAVCC = VDVCC = 3.6V or 0V, Figure 2 150 k 2 _______________________________________________________________________________________ 10-Bit Bus LVDS Deserializers (VAVCC = VDVCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC = VDVCC = +3.3V, VCM = 1.1V, |VID| = 0.2V, TA = +25°C.) (Notes 4, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE CLOCK TIMING REQUIREMENTS (REFCLK) REFCLK Frequency fRFF REFCLK Frequency Variation RFFV REFCLK Period tRFCP REFCLK Duty Cycle RFDC REFCLK Input Transition Time tRFTT MAX9206 16 45 MAX9208 40 60 -200 200 MAX9206 22.222 62.500 MAX9208 16.666 25 30 MHz ppm ns 50 70 % 3 6 ns SWITCHING CHARACTERISTICS MAX9206 22.222 62.500 MAX9208 16.666 25 Recovered Clock (RCLK) Period (Note 6) tRCP Low-to-High Transition Time tCLH Figure 3 1.5 3 ns High-to-Low Transition Time tCHL Figure 3 2 3 ns Deserializer Delay tDD MAX9206, 45MHz 1.75 x tRCP 1.75 x tRCP 1.75 x tRCP +2 + 3.3 + 6.5 MAX9208, 60MHz 1.75 x tRCP 1.75 x tRCP 1.75 x tRCP + 1.1 + 3.3 + 5.6 Figure 4 ns ns ROUT_ Data Valid Before RCLK tROS Figure 5 0.4 x tRCP 0.5 x tRCP ns ROUT_ Data Valid After RCLK tROH Figure 5 0.4 x tRCP 0.5 x tRCP ns RCLK Duty Cycle tRDC OUTPUT High-to-High Impedance Delay tHZR OUTPUT Low-to-High Impedance Delay 57 % CL = 5pF, Figure 6 8 ns tLZR CL = 5pF, Figure 6 8 ns OUTPUT High-Impedance to High-State Delay tZHR CL = 5pF, Figure 6 6 ns OUTPUT High-Impedance to Low-State Delay tZLR CL = 5pF, Figure 6 6 ns (2048 + 42) x tRFCP ns PLL Lock Time (from PWRDN Transition High) tDSR1 43 Sync patterns at input; supply and REFCLK stable; measured from PWRDN transition high to LOCK transition low; Figure 7 50 _______________________________________________________________________________________ 3 MAX9206/MAX9208 AC ELECTRICAL CHARACTERISTICS MAX9206/MAX9208 10-Bit Bus LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (continued) (VAVCC = VDVCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VAVCC = VDVCC = +3.3V, VCM = 1.1V, |VID| = 0.2V, TA = +25°C.) (Notes 4, 5) PARAMETER SYMBOL CONDITIONS PLL Lock Time (from Start of Sync Patterns) tDSR2 PLL locked to stable REFCLK; supply stable; static input; measured from start of sync patterns at input to LOCK transition low; Figure 8 LOCK High-Z to High-State Delay tZHLK Figure 7 MAX9206 Input Jitter Tolerance tJT Figure 9 MAX9208 MIN 16MHz 1300 45MHz 720 40MHz 720 60MHz 320 TYP MAX UNITS 42 x tRFCP ns 30 ns ps Note 1: Short one output at a time. Do not exceed the Absolute Maximum continuous power dissipation. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Voltages are referenced to ground except VTH, VTL, and VID, which are differential input voltages. Note 3: DC parameters are production tested at TA = +25°C and guaranteed by design and characterization over operating temperature range. Note 4: AC parameters guaranteed by design and characterization. Note 5: CL includes scope probe and test jig capacitance. Note 6: tRCP is determined by the period of TCLK, which is the reference clock of the serializer driving the deserializer. The frequency of TCLK must be within ±400ppm of the REFCLK frequency. 4 _______________________________________________________________________________________ 10-Bit Bus LVDS Deserializers PIN NAME FUNCTION 1, 12, 13 AGND 2 RCLK_R/F 3 REFCLK 4, 11 AVCC 5 RI+ Serial Data Input. Noninverting BLVDS differential input. 6 RI- Serial Data Input. Inverting BLVDS differential input. 7 PWRDN 8 REN Output Enable. LVTTL/LVCMOS level input. Drive REN low to put ROUT_ and RCLK in high impedance. LOCK remains active, indicating the status of the serial input. 9 RCLK Recovered Clock. LVTTL/LVCMOS level output. Use RCLK to strobe ROUT_. 10 LOCK Lock Indicator. LVTTL/LVCMOS level output. LOCK goes low when the PLL has achieved frequency and phase lock to the serial input, and the framing bits have been identified. 14, 20, 22 DGND Digital Ground 15–19, 24–28 ROUT9– ROUT0 21, 23 DVCC Analog Ground Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling edge of RCLK. PLL Reference Clock. LVTTL/LVCMOS level input. Analog Power Supply. Bypass AVCC with a 0.1µF and a 0.001µF capacitor to AGND. Power Down. LVTTL/LVCMOS level input. Drive PWRDN low to stop the PLL and put ROUT_, LOCK, and RCLK in high impedance. Parallel Output Data. LVTTL/LVCMOS level outputs. ROUT_ is valid on the second selected strobe edge of RCLK after LOCK goes low. Digital Power Supply. Bypass DVCC with a 0.1µF and a 0.001µF capacitor to DGND. Test Circuits/Timing Diagrams START BIT START BIT RI 0 1 2 3 4 5 6 7 8 9 END BIT 0 1 2 3 4 5 6 7 8 9 END BIT START BIT 0 1 2 TDD RCLK RCLK_R/F = HIGH ODD ROUT EVEN ROUT Figure 1. Worst-Case ICC Test Pattern _______________________________________________________________________________________ 5 MAX9206/MAX9208 Pin Description 10-Bit Bus LVDS Deserializers MAX9206/MAX9208 Test Circuits/Timing Diagrams (continued) VCC LVCMOS/LVTTL OUTPUT RIN2 CL 15pF TO DESERIALIZING CIRCUITRY VCC - 0.3V RI+ RIN1 80% 80% 20% 20% RIN1 tCHL tCLH RI- Figure 3. LVCMOS/LVTTL Output Load and Transition Times Figure 2. Input Fail-Safe Circuit START BIT 0 RI START SYMBOL N 1 2 3 4 5 6 7 8 END BIT 9 BIT 0 tDD 1 2 SYMBOL N+1 3 4 5 6 7 8 START END BIT 9 BIT 0 1 2 RCLK RCLK_R/F = HIGH SYMBOL N-1 ROUT_ SYMBOL N Figure 4. Input-to-Output Delay +7V FOR tLZR AND tZLR OPEN FOR tHZR AND tZHR 500Ω 450Ω RCLK RCLK_R/F = LOW 50% RCLK RCLK_R/F = HIGH 50% tROS ROUT_ DATA VALID BEFORE RCLK Figure 5. Data Valid Times tROH SCOPE CL REN 50Ω 1.5V tZLR DATA VALID AFTER RCLK tLZR ROUT_ RCLK VOL +0.5V VOL VOH VOH -0.5V tHZR tZHR Figure 6. High-Impedance Test Circuit and Timing 6 _______________________________________________________________________________________ 10-Bit Bus LVDS Deserializers tDSR1 ≤ (2048 + 42)tRFCP PWRDN REFCLK tRFCP SYNC PATTERNS DATA 111111 RI DON'T CARE 000000 tZHLK tDD LOCK HIGH-Z RCLK HIGH-Z ROUT_ HIGH-Z HIGH-Z HIGH-Z tHZR OR tLZR tRCP SYNC HIGH-Z DATA RCLK_R/F = LOW ≤42 x tRFCP 2048 x tRFCP Figure 7. PLL Lock Time from PWRDN REFCLK tRFCP DATA SYNC PATTERNS 111111 RI 000000 tDD LOCK tDSR2 ≤42tRFCP RCLK tRCP SYNC ROUT_ DATA DATA DATA RCLK_R/F = LOW Figure 8. Deserializer PLL Lock Time from Sync Patterns _______________________________________________________________________________________ 7 MAX9206/MAX9208 Test Circuits/Timing Diagrams (continued) MAX9206/MAX9208 10-Bit Bus LVDS Deserializers Detailed Description The MAX9206/MAX9208 deserialize a BLVDS serializer's output into 10-bit wide parallel LVCMOS/LVTTL data and a parallel rate clock. The MAX9206/MAX9208 include a PLL that locks to the frequency and phase of the serial input, and digital circuits that deserialize and deframe the data. The MAX9206/MAX9208 have highinput jitter tolerance while receiving data at speeds from 160Mbps to 600Mbps. Combination with the MAX9205/MAX9207 BLVDS serializers allows data transmission across backplanes using PCB traces, or across twin-ax or twisted-pair cables. The MAX9206/MAX9208 deserializers provide a powersaving, power-down mode when PWRDN is driven low. The output enable, REN, allows the parallel data outputs (ROUT_) and recovered clock (RCLK) to be enabled or disabled while maintaining lock to the serial input. LOCK, along with RCLK, indicates when data is valid at ROUT_. Parallel, deserialized data at ROUT_ is strobed out on the selected strobe edge of RCLK. The strobe edge of RCLK is programmable. The falling edge is selected when RCLK_R/F is low and the rising edge is selected when RCLK_R/F is high. The interface may be point-to-point or a heavily loaded bus. The characteristic impedance of the media and connections can range from 100Ω for a point-to-point interface to 54Ω for a heavily loaded bus. A double-terminated point-to-point interface uses a 100Ω termination resistor at each end of the interface, resulting in a total load of 50Ω. A heavily loaded bus with a termination as low as 54Ω at each end of the bus (resulting in a total load of 27Ω) can be driven. A high state bit and a low state bit, added by the BLVDS serializer, frame each 10 bits of serial data and create a guaranteed transition for clock recovery. The high bit is prepended at the start and the low bit is appended at the end of the 10-bit data. The rising edge formed at the end/start bit boundary functions as an embedded clock. Twelve serial bits (10 data + 2 frame) are transmitted by the serializer and received by the deserializer for each 10 bits of data transferred. The MAX9206 accepts a 16MHz to 45MHz reference clock, and receives serial data at 160Mbps (10 data bits x 16MHz) to 450Mbps (10 data bits x 45MHz). The MAX9208 accepts a 40MHz to 60MHz reference clock, and receives serial data at a rate of 400Mbps to 600Mbps. Initialization Initialize the MAX9206/MAX9208 before receiving data. When power is applied, with REFCLK stable and PWRDN high, RCLK and ROUT_ are held in high 8 impedance, LOCK goes high, and the on-chip PLL locks to REFCLK in 2048 cycles. After locking to REFCLK, ROUT_ is active, RCLK tracks REFCLK, and LOCK remains high. If transitions are detected at the serial input, the PLL locks to the phase and frequency of the serial input, finds the frame bits, and drives LOCK low. If the serial input is sync patterns, LOCK goes low in 42 or fewer cycles of RCLK. When LOCK goes low, RCLK switches from tracking REFCLK to tracking the serializer reference clock (TCLK). Deserialized data at ROUT_ is valid on the second selected strobe edge of RCLK after LOCK goes low. Initialization restarts when power is cycled or on the rising edge of PWRDN. Lock to Pseudorandom Data The MAX9206/MAX9208 lock to pseudorandom serial input data by deductively eliminating rising edges due to data until the embedded end/start edge is found. The end/start edge is identified unless the data contains a permanent, consecutive, frame-to-frame rising edge at the same bit position. Send sync patterns to guarantee lock. A sync pattern is six consecutive ones followed by six consecutive zeros, repeating every RCLK period with only one rising edge (at the end/start boundary). The MAX9205/MAX9207 serializers generate sync patterns when SYNC1 or SYNC2 is driven high. Since sending sync patterns to initialize a deserializer disrupts data transfer to all deserializers receiving the same serial input (Figure 11, for example), lock to pseudorandom data is preferred in many applications. Lock to pseudorandom data allows initialization of a deserializer after hot insertion without disrupting data communication on other links. The MAX9206/MAX9208s’ deductive algorithm provides very fast pseudorandom data lock times. Table 1 compares typical lock times for pseudorandom and sync pattern inputs. Power-Down Drive PWRDN low to enter the power-down mode. In power-down, the PLL is stopped and the outputs (ROUT_, RCLK, and LOCK) are put in high impedance, disabling drive current and also reducing supply current. Output Enable When the deserializer is initialized and REN is high, ROUT_ is active, RCLK tracks the serializer reference clock (TCLK), and LOCK is low. Driving REN low disables the ROUT_ and RCLK output drivers and does not affect state machine timing. ROUT_ and RCLK go _______________________________________________________________________________________ 10-Bit Bus LVDS Deserializers MAX9206/MAX9208 Table 1. Typical Lock Times REFCLK FREQUENCY 16MHz 35MHz 40MHz 40MHz DATA PATTERN PSEUDORANDOM DATA PSEUDORANDOM DATA PSEUDORANDOM DATA SYNC PATTERNS 0.749µs 0.375µs 0.354µs 0.134µs 11.99 13.14 14.18 5.37 0.318µs 0.158µs 0.144µs 0.103µs 5.09 5.52 5.76 4.11 0.13µs 0.068µs 0.061µs 0.061µs 2.08 2.37 2.44 2.45 Maximum Maximum (Clock Cycles) Average Average (Clock Cycles) Minimum Minimum (Clock Cycles) Note: Pseudorandom lock performed with 215-1 PRBS pattern, 10,000 lock time tests. into high impedance but LOCK continues to reflect the status of the serial input. Driving REN high again enables the ROUT_ and RCLK drivers. Losing Lock on Serial Data If one embedded clock edge (rising edge formed by end/start bits) is not detected, LOCK goes high, RCLK tracks REFCLK, and ROUT_ stays active but with invalid data. LOCK stays high for a minimum of two RCLK cycles. Then, if transitions are detected at the serial input, the PLL attempts to lock to the serial input. When the PLL locks to serial input data, LOCK goes low, RCLK tracks the serializer reference clock (TCLK), and ROUT_ is valid on the second selected strobe edge of RCLK after LOCK goes low. A minimum of two embedded clock edges in a row are required to regain lock to the serial input after LOCK goes high. For automatic resynchronization, LOCK can be connected to the MAX9205/MAX9207 serializer SYNC1 or SYNC2 input. With this connection, when LOCK goes high, the serializer sends sync patterns until the deserializer locks to the serial input and drives LOCK low. Input Fail-Safe When the serial input is undriven (a disconnected cable or serializer output in high impedance, for example) an on-chip fail-safe circuit (Figure 2) drives the serial input high. The response time of the fail-safe circuit depends on interconnect characteristics. With an undriven input, LOCK may switch high and low until the fail-safe circuit takes effect. The undriven condition of the link can be detected in spite of LOCK switching since LOCK is high long enough to be sampled (LOCK is high for at least two RCLK cycles after a missed clock edge and RCLK keeps running, allowing sampling). If it is required that LOCK remain high for an undriven input, the on-chip fail-safe circuit can be supplemented with external pullup bias resistors. Deserializer Jitter Tolerance The tJT parameter specifies the total zero-to-peak input jitter the deserializer can tolerate before a sampling error occurs (Figure 9). Zero-to-peak jitter is measured from the mean value of the deterministic jitter distribution. Sources of jitter include the serializer (supply noise, reference clock jitter, pulse skew, and intersymbol interference), the interconnect (intersymbol interference, crosstalk, within-pair skew, ground shift), and the deserializer (supply noise). The sum of the zero-to-peak individual jitter sources must be less than or equal to the minimum value of tJT. For example, at 40MHz, the MAX9205 serializer has 140ps (p-p) maximum deterministic output jitter. The zero-to-peak value is 140ps/2 = 70ps. If the interconnect jitter is 100ps (p-p) with a symmetrical distribution, the zero-to-peak jitter is 50ps. The MAX9206 deserializer jitter tolerance is 720ps at 40MHz. The total zero-topeak input jitter is 70ps + 50ps = 120ps, which is less than the jitter tolerance. In this case, the margin is 720ps - 120ps = 600ps. _______________________________________________________________________________________ 9 MAX9206/MAX9208 10-Bit Bus LVDS Deserializers t RCP /12 t JT t JT V ID = 150mV Figure 9. Input Jitter Tolerance Applications Information simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by a differential receiver. Eliminate reflections and ensure that noise couples as common mode by running differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Avoid 90° turns and minimize the number of vias to further prevent impedance discontinuities. Power-Supply Bypassing Bypass each supply pin with high-frequency surfacemount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smaller valued capacitor the closest to the supply pin. SERIALIZED DATA PARALLEL DATA IN ASIC Figure 10. Double-Termination Point-to-Point ASIC MAX9206 MAX9208 MAX9150 REPEATER 100Ω MAX9206 MAX9208 ASIC MAX9205 MAX9207 100Ω PARALLEL DATA OUT 100Ω MAX9205 MAX9207 Differential Traces and Termination Trace characteristics affect the performance of the MAX9206/MAX9208. Use controlled-impedance media. Avoid the use of unbalanced cables such as ribbon or 100Ω MAX9206 MAX9208 100Ω 100Ω Figure 11. Point-to-Point Broadcast Using MAX9150 Repeater 10 ______________________________________________________________________________________ 10-Bit Bus LVDS Deserializers LOGIC INPUTS CONDITIONS OUTPUTS Low Power applied and stable Power-down mode. PLL is stopped. Current consumption is reduced to 400µA (typ). ROUT_, RCLK, and LOCK are high impedance. Low High Deserializer initialized RCLK and ROUT_ are high impedance. LOCK is active, indicating the serial input status. High High Deserializer initialized RCLK and ROUT_ are active. LOCK is active, indicating the serial input status. REN PWRDN X X = Don’t care. Topologies The MAX9206/MAX9208 deserializers can operate in a variety of topologies. Examples of double-terminated point-to-point and point-to-point broadcast are shown in Figures 10 and 11. Use 1% surface-mount termination resistors. Pin Configuration TOP VIEW + A point-to-point interface terminated at each end in the characteristic impedance of the cable or PCB traces is shown in Figure 10. The total load seen by the serializer is 50Ω. The double termination typically reduces reflections compared to a single 100Ω termination. A single 100Ω termination at the deserializer input is feasible and makes the differential signal swing larger. A point-to-point version of a multidrop bus is shown in Figure 11. The low-jitter MAX9150 10-port repeater is used to reproduce and transmit the serializer output over 10 double-terminated point-to-point links. Compared to a bus, more interconnect is traded for robust hot-plug capability. Board Layout Chip Information PROCESS: CMOS 28 ROUT0 RCLK_R/F 2 27 ROUT1 REFCLK 3 26 ROUT2 AVCC 4 25 ROUT3 RI+ 5 RI- 6 The repeater eliminates nine serializers compared to 10 individual point-to-point serializer-to-deserializer connections. Since repeater jitter is a component of the total jitter seen at the deserializer input (along with other sources of jitter), a low-jitter repeater is essential in most high data-rate applications. A four-layer PCB providing separate power, ground, and signal layers is recommended. Keep the LVTTL/LVCMOS inputs and outputs separated from the BLVDS inputs to prevent coupling into the BLVDS lines. AGND 1 24 ROUT4 MAX9206/ MAX9208 23 DVCC PWRDN 7 22 DGND REN 8 21 DVCC RCLK 9 20 DGND LOCK 10 19 ROUT5 AVCC 11 18 ROUT6 AGND 12 17 ROUT7 AGND 13 16 ROUT8 DGND 14 15 ROUT9 SSOP Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 SSOP A28+4 21-0056 90-0095 ______________________________________________________________________________________ 11 MAX9206/MAX9208 Table 2. Input/Output Function Table MAX9206/MAX9208 10-Bit Bus LVDS Deserializers Revision History REVISION NUMBER REVISION DATE 0 8/01 Initial release 1 12/07 Max clock frequency increased to 45MHz; min values decreased for REFCLK and RCLK period; updated package outline; updated names for pins 2 and 3. 2 11/10 Updated Ordering Information, Absolute Maximum Ratings, and Package Information DESCRIPTION PAGES CHANGED — 1–5, 8, 12 1, 2, 12 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.